Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7061300 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5048807 |
1 |
|
|
T27 |
156 |
|
T28 |
1183 |
|
T32 |
56733 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11469540 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
640567 |
1 |
|
|
T27 |
9 |
|
T28 |
37 |
|
T32 |
7767 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7082879 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5027228 |
1 |
|
|
T27 |
200 |
|
T28 |
890 |
|
T32 |
59467 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2185772 |
1 |
|
|
T27 |
103 |
|
T28 |
391 |
|
T32 |
26028 |
| auto[1] |
auto[0] |
auto[1] |
318442 |
1 |
|
|
T27 |
6 |
|
T28 |
15 |
|
T32 |
4002 |
| auto[1] |
auto[1] |
auto[0] |
2200889 |
1 |
|
|
T27 |
88 |
|
T28 |
462 |
|
T32 |
25672 |
| auto[1] |
auto[1] |
auto[1] |
322125 |
1 |
|
|
T27 |
3 |
|
T28 |
22 |
|
T32 |
3765 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |