Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079670 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5030437 |
1 |
|
|
T27 |
166 |
|
T28 |
1129 |
|
T32 |
59582 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11467645 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
642462 |
1 |
|
|
T27 |
8 |
|
T28 |
42 |
|
T32 |
7491 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7078496 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5031611 |
1 |
|
|
T27 |
168 |
|
T28 |
1001 |
|
T32 |
57804 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2191878 |
1 |
|
|
T27 |
108 |
|
T28 |
354 |
|
T32 |
24527 |
| auto[1] |
auto[0] |
auto[1] |
320518 |
1 |
|
|
T27 |
7 |
|
T28 |
16 |
|
T32 |
3639 |
| auto[1] |
auto[1] |
auto[0] |
2197271 |
1 |
|
|
T27 |
52 |
|
T28 |
605 |
|
T32 |
25786 |
| auto[1] |
auto[1] |
auto[1] |
321944 |
1 |
|
|
T27 |
1 |
|
T28 |
26 |
|
T32 |
3852 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |