Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7073077 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5037030 |
1 |
|
|
T27 |
111 |
|
T28 |
905 |
|
T32 |
58639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10025961 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
2084146 |
1 |
|
|
T27 |
119 |
|
T28 |
848 |
|
T32 |
22370 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7079018 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5031089 |
1 |
|
|
T27 |
175 |
|
T28 |
1093 |
|
T32 |
57173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1463730 |
1 |
|
|
T27 |
35 |
|
T28 |
165 |
|
T32 |
16978 |
| auto[1] |
auto[0] |
auto[1] |
1040550 |
1 |
|
|
T27 |
93 |
|
T28 |
440 |
|
T32 |
10953 |
| auto[1] |
auto[1] |
auto[0] |
1483213 |
1 |
|
|
T27 |
21 |
|
T28 |
80 |
|
T32 |
17825 |
| auto[1] |
auto[1] |
auto[1] |
1043596 |
1 |
|
|
T27 |
26 |
|
T28 |
408 |
|
T32 |
11417 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |