Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7088677 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5021430 |
1 |
|
|
T27 |
193 |
|
T28 |
854 |
|
T32 |
57692 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10047557 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
2062550 |
1 |
|
|
T27 |
100 |
|
T28 |
741 |
|
T32 |
23871 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7135865 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
4974242 |
1 |
|
|
T27 |
148 |
|
T28 |
900 |
|
T32 |
59829 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1462286 |
1 |
|
|
T27 |
30 |
|
T28 |
91 |
|
T32 |
17776 |
| auto[1] |
auto[0] |
auto[1] |
1035273 |
1 |
|
|
T27 |
53 |
|
T28 |
433 |
|
T32 |
11829 |
| auto[1] |
auto[1] |
auto[0] |
1449406 |
1 |
|
|
T27 |
18 |
|
T28 |
68 |
|
T32 |
18182 |
| auto[1] |
auto[1] |
auto[1] |
1027277 |
1 |
|
|
T27 |
47 |
|
T28 |
308 |
|
T32 |
12042 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |