Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7097890 |
1 |
|
|
T24 |
258 |
|
T25 |
298 |
|
T26 |
57695 |
| auto[1] |
5012217 |
1 |
|
|
T27 |
146 |
|
T28 |
1207 |
|
T32 |
58757 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2193031 |
1 |
|
|
T27 |
89 |
|
T28 |
712 |
|
T32 |
25484 |
| auto[1] |
auto[0] |
auto[1] |
319923 |
1 |
|
|
T27 |
9 |
|
T28 |
27 |
|
T32 |
3772 |
| auto[1] |
auto[1] |
auto[0] |
2180906 |
1 |
|
|
T27 |
44 |
|
T28 |
452 |
|
T32 |
25704 |
| auto[1] |
auto[1] |
auto[1] |
318357 |
1 |
|
|
T27 |
4 |
|
T28 |
16 |
|
T32 |
3797 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |