Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 940
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T96 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.264131632 Jun 21 06:28:21 PM PDT 24 Jun 21 06:28:27 PM PDT 24 31966466 ps
T762 /workspace/coverage/cover_reg_top/6.gpio_intr_test.2744788836 Jun 21 06:28:22 PM PDT 24 Jun 21 06:28:28 PM PDT 24 16889870 ps
T763 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2231085963 Jun 21 06:28:09 PM PDT 24 Jun 21 06:28:17 PM PDT 24 20015868 ps
T97 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1756295420 Jun 21 06:28:01 PM PDT 24 Jun 21 06:28:05 PM PDT 24 45408077 ps
T764 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3795988167 Jun 21 06:28:31 PM PDT 24 Jun 21 06:28:33 PM PDT 24 20039469 ps
T765 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3279519333 Jun 21 06:28:42 PM PDT 24 Jun 21 06:28:44 PM PDT 24 49906574 ps
T766 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3565613559 Jun 21 06:28:15 PM PDT 24 Jun 21 06:28:23 PM PDT 24 366033609 ps
T767 /workspace/coverage/cover_reg_top/7.gpio_intr_test.3874463110 Jun 21 06:28:15 PM PDT 24 Jun 21 06:28:22 PM PDT 24 41958434 ps
T768 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1506195465 Jun 21 06:28:03 PM PDT 24 Jun 21 06:28:12 PM PDT 24 34882961 ps
T769 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3419537530 Jun 21 06:28:27 PM PDT 24 Jun 21 06:28:30 PM PDT 24 15213133 ps
T770 /workspace/coverage/cover_reg_top/33.gpio_intr_test.711529278 Jun 21 06:28:32 PM PDT 24 Jun 21 06:28:34 PM PDT 24 15849833 ps
T771 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3777001240 Jun 21 06:28:44 PM PDT 24 Jun 21 06:28:45 PM PDT 24 64229021 ps
T772 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2735934190 Jun 21 06:28:09 PM PDT 24 Jun 21 06:28:18 PM PDT 24 34434423 ps
T773 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3543448681 Jun 21 06:28:37 PM PDT 24 Jun 21 06:28:39 PM PDT 24 41459355 ps
T774 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1643039311 Jun 21 06:28:34 PM PDT 24 Jun 21 06:28:37 PM PDT 24 16321511 ps
T775 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1364534056 Jun 21 06:28:14 PM PDT 24 Jun 21 06:28:23 PM PDT 24 257126766 ps
T776 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2950028919 Jun 21 06:28:32 PM PDT 24 Jun 21 06:28:34 PM PDT 24 38159246 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1554110189 Jun 21 06:28:35 PM PDT 24 Jun 21 06:28:37 PM PDT 24 65216734 ps
T778 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2199646770 Jun 21 06:28:24 PM PDT 24 Jun 21 06:28:29 PM PDT 24 40853942 ps
T779 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1525025347 Jun 21 06:28:23 PM PDT 24 Jun 21 06:28:29 PM PDT 24 61051220 ps
T780 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.673708166 Jun 21 06:28:04 PM PDT 24 Jun 21 06:28:14 PM PDT 24 36114926 ps
T781 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2102723221 Jun 21 06:28:23 PM PDT 24 Jun 21 06:28:28 PM PDT 24 27581951 ps
T782 /workspace/coverage/cover_reg_top/1.gpio_intr_test.445436782 Jun 21 06:28:19 PM PDT 24 Jun 21 06:28:27 PM PDT 24 12370101 ps
T783 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2387697357 Jun 21 06:28:23 PM PDT 24 Jun 21 06:28:29 PM PDT 24 17118629 ps
T784 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2104324271 Jun 21 06:28:22 PM PDT 24 Jun 21 06:28:28 PM PDT 24 14246885 ps
T785 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3243563773 Jun 21 06:28:27 PM PDT 24 Jun 21 06:28:30 PM PDT 24 23354693 ps
T786 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2152289021 Jun 21 06:28:42 PM PDT 24 Jun 21 06:28:44 PM PDT 24 24047354 ps
T109 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.753530259 Jun 21 06:28:26 PM PDT 24 Jun 21 06:28:30 PM PDT 24 198168977 ps
T787 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1371265850 Jun 21 06:28:33 PM PDT 24 Jun 21 06:28:36 PM PDT 24 46034824 ps
T788 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1722270199 Jun 21 06:28:12 PM PDT 24 Jun 21 06:28:21 PM PDT 24 321010953 ps
T50 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3024786681 Jun 21 06:28:39 PM PDT 24 Jun 21 06:28:41 PM PDT 24 408145033 ps
T789 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1956911701 Jun 21 06:28:33 PM PDT 24 Jun 21 06:28:35 PM PDT 24 43126042 ps
T790 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.808364608 Jun 21 06:28:29 PM PDT 24 Jun 21 06:28:31 PM PDT 24 25339151 ps
T791 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1037004928 Jun 21 06:28:14 PM PDT 24 Jun 21 06:28:22 PM PDT 24 70413941 ps
T792 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2061083239 Jun 21 06:28:47 PM PDT 24 Jun 21 06:28:48 PM PDT 24 13892775 ps
T793 /workspace/coverage/cover_reg_top/8.gpio_intr_test.484991669 Jun 21 06:28:16 PM PDT 24 Jun 21 06:28:24 PM PDT 24 26287352 ps
T794 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3714883949 Jun 21 06:28:35 PM PDT 24 Jun 21 06:28:37 PM PDT 24 13261081 ps
T795 /workspace/coverage/cover_reg_top/47.gpio_intr_test.1359248290 Jun 21 06:28:36 PM PDT 24 Jun 21 06:28:38 PM PDT 24 47624527 ps
T796 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1018949263 Jun 21 06:28:08 PM PDT 24 Jun 21 06:28:16 PM PDT 24 44258598 ps
T797 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.756934939 Jun 21 06:28:09 PM PDT 24 Jun 21 06:28:17 PM PDT 24 33507281 ps
T51 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2372065902 Jun 21 06:28:09 PM PDT 24 Jun 21 06:28:18 PM PDT 24 45875566 ps
T798 /workspace/coverage/cover_reg_top/19.gpio_intr_test.993119618 Jun 21 06:28:33 PM PDT 24 Jun 21 06:28:35 PM PDT 24 34749916 ps
T799 /workspace/coverage/cover_reg_top/43.gpio_intr_test.116840895 Jun 21 06:28:39 PM PDT 24 Jun 21 06:28:40 PM PDT 24 14384273 ps
T800 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2977682099 Jun 21 06:28:17 PM PDT 24 Jun 21 06:28:24 PM PDT 24 14442691 ps
T801 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2896367648 Jun 21 06:28:32 PM PDT 24 Jun 21 06:28:35 PM PDT 24 32026062 ps
T802 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2639006664 Jun 21 06:28:32 PM PDT 24 Jun 21 06:28:35 PM PDT 24 126604163 ps
T803 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2905086710 Jun 21 06:28:04 PM PDT 24 Jun 21 06:28:13 PM PDT 24 403722512 ps
T804 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4185562919 Jun 21 06:28:31 PM PDT 24 Jun 21 06:28:33 PM PDT 24 16452911 ps
T805 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3428086241 Jun 21 06:28:45 PM PDT 24 Jun 21 06:28:49 PM PDT 24 281305793 ps
T84 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2175512565 Jun 21 06:28:23 PM PDT 24 Jun 21 06:28:29 PM PDT 24 16108509 ps
T806 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2213512959 Jun 21 06:28:11 PM PDT 24 Jun 21 06:28:19 PM PDT 24 232626400 ps
T807 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.332000459 Jun 21 06:28:01 PM PDT 24 Jun 21 06:28:07 PM PDT 24 18665029 ps
T808 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3502665596 Jun 21 06:28:22 PM PDT 24 Jun 21 06:28:27 PM PDT 24 30128651 ps
T809 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2443860052 Jun 21 06:28:48 PM PDT 24 Jun 21 06:28:50 PM PDT 24 193434782 ps
T810 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3102534731 Jun 21 06:28:15 PM PDT 24 Jun 21 06:28:23 PM PDT 24 39226629 ps
T110 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1171634683 Jun 21 06:28:32 PM PDT 24 Jun 21 06:28:35 PM PDT 24 483951295 ps
T811 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3531908502 Jun 21 06:28:23 PM PDT 24 Jun 21 06:28:29 PM PDT 24 229614135 ps
T812 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3720206459 Jun 21 06:28:46 PM PDT 24 Jun 21 06:28:47 PM PDT 24 24767301 ps
T813 /workspace/coverage/cover_reg_top/32.gpio_intr_test.1545003339 Jun 21 06:28:39 PM PDT 24 Jun 21 06:28:40 PM PDT 24 24437828 ps
T814 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1055594005 Jun 21 06:28:29 PM PDT 24 Jun 21 06:28:32 PM PDT 24 92014682 ps
T815 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3216162216 Jun 21 06:28:15 PM PDT 24 Jun 21 06:28:22 PM PDT 24 16366395 ps
T816 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3461132753 Jun 21 06:28:13 PM PDT 24 Jun 21 06:28:21 PM PDT 24 198089600 ps
T85 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2742817968 Jun 21 06:28:17 PM PDT 24 Jun 21 06:28:25 PM PDT 24 14594248 ps
T817 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1176682535 Jun 21 06:28:05 PM PDT 24 Jun 21 06:28:15 PM PDT 24 315949643 ps
T818 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3885309086 Jun 21 06:28:34 PM PDT 24 Jun 21 06:28:36 PM PDT 24 53562831 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3647137160 Jun 21 06:28:13 PM PDT 24 Jun 21 06:28:20 PM PDT 24 26430520 ps
T819 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.513637089 Jun 21 06:28:22 PM PDT 24 Jun 21 06:28:28 PM PDT 24 59458718 ps
T87 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1863545178 Jun 21 06:28:33 PM PDT 24 Jun 21 06:28:35 PM PDT 24 18354088 ps
T820 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2242690466 Jun 21 06:28:20 PM PDT 24 Jun 21 06:28:28 PM PDT 24 196459749 ps
T821 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2965894747 Jun 21 06:28:19 PM PDT 24 Jun 21 06:28:26 PM PDT 24 45011865 ps
T822 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2967746083 Jun 21 06:28:33 PM PDT 24 Jun 21 06:28:35 PM PDT 24 45649139 ps
T823 /workspace/coverage/cover_reg_top/31.gpio_intr_test.3726668791 Jun 21 06:28:42 PM PDT 24 Jun 21 06:28:44 PM PDT 24 15718252 ps
T824 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1991807169 Jun 21 06:28:42 PM PDT 24 Jun 21 06:28:44 PM PDT 24 74680918 ps
T825 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1129256149 Jun 21 06:28:17 PM PDT 24 Jun 21 06:28:24 PM PDT 24 107737368 ps
T88 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.483215103 Jun 21 06:28:14 PM PDT 24 Jun 21 06:28:24 PM PDT 24 460839899 ps
T826 /workspace/coverage/cover_reg_top/48.gpio_intr_test.961953829 Jun 21 06:28:50 PM PDT 24 Jun 21 06:28:51 PM PDT 24 79777159 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3214857900 Jun 21 06:28:37 PM PDT 24 Jun 21 06:28:39 PM PDT 24 15173637 ps
T828 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.907426335 Jun 21 06:28:15 PM PDT 24 Jun 21 06:28:23 PM PDT 24 154449873 ps
T829 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.390663839 Jun 21 06:28:19 PM PDT 24 Jun 21 06:28:27 PM PDT 24 74913565 ps
T830 /workspace/coverage/cover_reg_top/17.gpio_intr_test.1593514812 Jun 21 06:28:50 PM PDT 24 Jun 21 06:28:51 PM PDT 24 49952037 ps
T831 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1876641381 Jun 21 06:28:25 PM PDT 24 Jun 21 06:28:29 PM PDT 24 91532381 ps
T832 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1083685514 Jun 21 06:28:13 PM PDT 24 Jun 21 06:28:20 PM PDT 24 15454673 ps
T833 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.906364125 Jun 21 06:28:21 PM PDT 24 Jun 21 06:28:28 PM PDT 24 88468923 ps
T834 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3369694199 Jun 21 06:28:32 PM PDT 24 Jun 21 06:28:34 PM PDT 24 10848293 ps
T835 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3922262284 Jun 21 06:28:24 PM PDT 24 Jun 21 06:28:29 PM PDT 24 42755735 ps
T836 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2011021525 Jun 21 06:28:29 PM PDT 24 Jun 21 06:28:32 PM PDT 24 278760327 ps
T837 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2499543513 Jun 21 06:28:30 PM PDT 24 Jun 21 06:28:34 PM PDT 24 546038044 ps
T838 /workspace/coverage/cover_reg_top/27.gpio_intr_test.91582499 Jun 21 06:28:41 PM PDT 24 Jun 21 06:28:42 PM PDT 24 50451632 ps
T839 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.823134636 Jun 21 06:28:18 PM PDT 24 Jun 21 06:28:27 PM PDT 24 37526117 ps
T840 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2205473238 Jun 21 06:28:03 PM PDT 24 Jun 21 06:28:12 PM PDT 24 95355316 ps
T841 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2884547544 Jun 21 06:57:02 PM PDT 24 Jun 21 06:57:09 PM PDT 24 186084416 ps
T842 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.835859584 Jun 21 06:57:14 PM PDT 24 Jun 21 06:57:21 PM PDT 24 74333131 ps
T843 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3464030936 Jun 21 06:57:11 PM PDT 24 Jun 21 06:57:19 PM PDT 24 168753836 ps
T844 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1209769872 Jun 21 06:57:03 PM PDT 24 Jun 21 06:57:10 PM PDT 24 138647523 ps
T845 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2727634004 Jun 21 06:57:28 PM PDT 24 Jun 21 06:57:31 PM PDT 24 26556352 ps
T846 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3238388094 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:34 PM PDT 24 31533093 ps
T847 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574567427 Jun 21 06:57:04 PM PDT 24 Jun 21 06:57:11 PM PDT 24 66094652 ps
T848 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2745289270 Jun 21 06:57:28 PM PDT 24 Jun 21 06:57:31 PM PDT 24 75501294 ps
T849 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1528662648 Jun 21 06:57:13 PM PDT 24 Jun 21 06:57:21 PM PDT 24 50484682 ps
T850 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3725118367 Jun 21 06:57:29 PM PDT 24 Jun 21 06:57:32 PM PDT 24 247502015 ps
T851 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3906853553 Jun 21 06:57:06 PM PDT 24 Jun 21 06:57:14 PM PDT 24 497259115 ps
T852 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1911438083 Jun 21 06:57:37 PM PDT 24 Jun 21 06:57:41 PM PDT 24 54734180 ps
T853 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1145866024 Jun 21 06:57:23 PM PDT 24 Jun 21 06:57:29 PM PDT 24 221427668 ps
T854 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1294701641 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:12 PM PDT 24 55882052 ps
T855 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1631731847 Jun 21 06:57:28 PM PDT 24 Jun 21 06:57:31 PM PDT 24 48998277 ps
T856 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2677262410 Jun 21 06:57:28 PM PDT 24 Jun 21 06:57:32 PM PDT 24 163596272 ps
T857 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1947173505 Jun 21 06:57:20 PM PDT 24 Jun 21 06:57:26 PM PDT 24 22869337 ps
T858 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.388731557 Jun 21 06:57:21 PM PDT 24 Jun 21 06:57:26 PM PDT 24 119567308 ps
T859 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400146906 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 127700019 ps
T860 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3241282446 Jun 21 06:57:28 PM PDT 24 Jun 21 06:57:31 PM PDT 24 94980555 ps
T861 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1194454640 Jun 21 06:57:03 PM PDT 24 Jun 21 06:57:10 PM PDT 24 231919726 ps
T862 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983327068 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:29 PM PDT 24 57056897 ps
T863 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1450297200 Jun 21 06:57:29 PM PDT 24 Jun 21 06:57:33 PM PDT 24 258781486 ps
T864 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2646028369 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:13 PM PDT 24 187469945 ps
T865 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3931701169 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 71292777 ps
T866 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436602634 Jun 21 06:57:12 PM PDT 24 Jun 21 06:57:20 PM PDT 24 41637823 ps
T867 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1341024696 Jun 21 06:57:04 PM PDT 24 Jun 21 06:57:11 PM PDT 24 188262838 ps
T868 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.911478977 Jun 21 06:57:10 PM PDT 24 Jun 21 06:57:19 PM PDT 24 42505619 ps
T869 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4144643223 Jun 21 06:57:04 PM PDT 24 Jun 21 06:57:10 PM PDT 24 50853729 ps
T870 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2651879947 Jun 21 06:57:14 PM PDT 24 Jun 21 06:57:21 PM PDT 24 24746777 ps
T871 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3169351446 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:33 PM PDT 24 665861712 ps
T872 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.774783545 Jun 21 06:57:18 PM PDT 24 Jun 21 06:57:25 PM PDT 24 246462646 ps
T873 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3853672702 Jun 21 06:57:27 PM PDT 24 Jun 21 06:57:31 PM PDT 24 29581997 ps
T874 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1092582333 Jun 21 06:57:12 PM PDT 24 Jun 21 06:57:20 PM PDT 24 305594505 ps
T875 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2795129787 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:13 PM PDT 24 46590077 ps
T876 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1713902144 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:34 PM PDT 24 50076486 ps
T877 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1410341191 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:13 PM PDT 24 65404981 ps
T878 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4269006206 Jun 21 06:57:19 PM PDT 24 Jun 21 06:57:25 PM PDT 24 87029671 ps
T879 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.809176473 Jun 21 06:57:13 PM PDT 24 Jun 21 06:57:20 PM PDT 24 41768723 ps
T880 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4190674771 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:34 PM PDT 24 67482990 ps
T881 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2385389007 Jun 21 06:57:29 PM PDT 24 Jun 21 06:57:32 PM PDT 24 68420713 ps
T882 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2035528995 Jun 21 06:57:04 PM PDT 24 Jun 21 06:57:11 PM PDT 24 63349140 ps
T883 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3648234418 Jun 21 06:57:14 PM PDT 24 Jun 21 06:57:21 PM PDT 24 61319266 ps
T884 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4197165987 Jun 21 06:57:21 PM PDT 24 Jun 21 06:57:27 PM PDT 24 88524272 ps
T885 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2672929247 Jun 21 06:57:20 PM PDT 24 Jun 21 06:57:26 PM PDT 24 101365325 ps
T886 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3526038463 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 117775906 ps
T887 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.770828379 Jun 21 06:57:31 PM PDT 24 Jun 21 06:57:34 PM PDT 24 43927298 ps
T888 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3422207394 Jun 21 06:57:13 PM PDT 24 Jun 21 06:57:21 PM PDT 24 214601604 ps
T889 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2079782728 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:34 PM PDT 24 36063640 ps
T890 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1174080523 Jun 21 06:57:21 PM PDT 24 Jun 21 06:57:28 PM PDT 24 95919264 ps
T891 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4043238323 Jun 21 06:57:11 PM PDT 24 Jun 21 06:57:19 PM PDT 24 80234682 ps
T892 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.928011552 Jun 21 06:57:12 PM PDT 24 Jun 21 06:57:20 PM PDT 24 267156052 ps
T893 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1675267890 Jun 21 06:57:06 PM PDT 24 Jun 21 06:57:13 PM PDT 24 26453915 ps
T894 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460615282 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:13 PM PDT 24 312856969 ps
T895 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3896738563 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:34 PM PDT 24 331748643 ps
T896 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4197875467 Jun 21 06:57:13 PM PDT 24 Jun 21 06:57:21 PM PDT 24 266560565 ps
T897 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164840988 Jun 21 06:57:11 PM PDT 24 Jun 21 06:57:19 PM PDT 24 29479670 ps
T898 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.349843939 Jun 21 06:57:23 PM PDT 24 Jun 21 06:57:28 PM PDT 24 49750598 ps
T899 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3279816058 Jun 21 06:57:09 PM PDT 24 Jun 21 06:57:18 PM PDT 24 73607536 ps
T900 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.378461225 Jun 21 06:57:06 PM PDT 24 Jun 21 06:57:15 PM PDT 24 57271200 ps
T901 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1572317374 Jun 21 06:57:15 PM PDT 24 Jun 21 06:57:22 PM PDT 24 103531620 ps
T902 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1360996264 Jun 21 06:57:11 PM PDT 24 Jun 21 06:57:19 PM PDT 24 96858261 ps
T903 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2726097065 Jun 21 06:57:06 PM PDT 24 Jun 21 06:57:15 PM PDT 24 171013607 ps
T904 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3505322292 Jun 21 06:57:13 PM PDT 24 Jun 21 06:57:21 PM PDT 24 131068335 ps
T905 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.209283022 Jun 21 06:57:18 PM PDT 24 Jun 21 06:57:25 PM PDT 24 54476558 ps
T906 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1321576712 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 37330230 ps
T907 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623010939 Jun 21 06:57:21 PM PDT 24 Jun 21 06:57:27 PM PDT 24 94960952 ps
T908 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1963159753 Jun 21 06:57:31 PM PDT 24 Jun 21 06:57:34 PM PDT 24 86086211 ps
T909 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3236498694 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 245513531 ps
T910 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.478679926 Jun 21 06:57:09 PM PDT 24 Jun 21 06:57:17 PM PDT 24 55851640 ps
T911 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2863670626 Jun 21 06:57:10 PM PDT 24 Jun 21 06:57:19 PM PDT 24 24860131 ps
T912 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2209861580 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:34 PM PDT 24 38136774 ps
T913 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3825018748 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:11 PM PDT 24 28684393 ps
T914 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2109323942 Jun 21 06:57:04 PM PDT 24 Jun 21 06:57:11 PM PDT 24 47841137 ps
T915 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.565568743 Jun 21 06:57:02 PM PDT 24 Jun 21 06:57:09 PM PDT 24 38340988 ps
T916 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2179799336 Jun 21 06:57:19 PM PDT 24 Jun 21 06:57:25 PM PDT 24 36547449 ps
T917 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3626260798 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 46769609 ps
T918 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436134760 Jun 21 06:57:19 PM PDT 24 Jun 21 06:57:26 PM PDT 24 56209481 ps
T919 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.910266768 Jun 21 06:57:06 PM PDT 24 Jun 21 06:57:14 PM PDT 24 102629625 ps
T920 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3253234304 Jun 21 06:57:19 PM PDT 24 Jun 21 06:57:26 PM PDT 24 357817231 ps
T921 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2954415404 Jun 21 06:57:10 PM PDT 24 Jun 21 06:57:18 PM PDT 24 63860397 ps
T922 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3621758696 Jun 21 06:57:30 PM PDT 24 Jun 21 06:57:34 PM PDT 24 30489659 ps
T923 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1461026089 Jun 21 06:57:28 PM PDT 24 Jun 21 06:57:32 PM PDT 24 97253814 ps
T924 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2835484650 Jun 21 06:57:07 PM PDT 24 Jun 21 06:57:16 PM PDT 24 247968402 ps
T925 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.483742823 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 64315450 ps
T926 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.205609810 Jun 21 06:57:28 PM PDT 24 Jun 21 06:57:32 PM PDT 24 183398387 ps
T927 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2320925923 Jun 21 06:57:31 PM PDT 24 Jun 21 06:57:34 PM PDT 24 83762461 ps
T928 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3082453118 Jun 21 06:57:23 PM PDT 24 Jun 21 06:57:28 PM PDT 24 34727351 ps
T929 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520970645 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 156033086 ps
T930 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2847681155 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:13 PM PDT 24 108874530 ps
T931 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2990109285 Jun 21 06:57:02 PM PDT 24 Jun 21 06:57:09 PM PDT 24 39618685 ps
T932 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2196902771 Jun 21 06:57:14 PM PDT 24 Jun 21 06:57:21 PM PDT 24 313470232 ps
T933 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3369958221 Jun 21 06:57:09 PM PDT 24 Jun 21 06:57:18 PM PDT 24 49387642 ps
T934 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2730682258 Jun 21 06:57:22 PM PDT 24 Jun 21 06:57:28 PM PDT 24 637557475 ps
T935 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.277837903 Jun 21 06:57:05 PM PDT 24 Jun 21 06:57:13 PM PDT 24 540277341 ps
T936 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1185142573 Jun 21 06:57:06 PM PDT 24 Jun 21 06:57:14 PM PDT 24 356653473 ps
T937 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2698810504 Jun 21 06:57:19 PM PDT 24 Jun 21 06:57:26 PM PDT 24 64533037 ps
T938 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.226073084 Jun 21 06:57:11 PM PDT 24 Jun 21 06:57:19 PM PDT 24 202657086 ps
T939 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2620007198 Jun 21 06:57:31 PM PDT 24 Jun 21 06:57:34 PM PDT 24 40134731 ps
T940 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2278681396 Jun 21 06:57:13 PM PDT 24 Jun 21 06:57:21 PM PDT 24 194664029 ps

Test location /workspace/coverage/default/16.gpio_full_random.699076012
Short name T33
Test name
Test status
Simulation time 58195949 ps
CPU time 0.89 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:41 PM PDT 24
Peak memory 196592 kb
Host smart-ed1719d6-59f9-4ea3-99be-e391d1a8b7c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699076012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.699076012
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3821929316
Short name T112
Test name
Test status
Simulation time 97578880 ps
CPU time 2.23 seconds
Started Jun 21 06:10:13 PM PDT 24
Finished Jun 21 06:10:16 PM PDT 24
Peak memory 196380 kb
Host smart-bab7aae7-b763-44a3-a15d-3979d8f3ad1d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821929316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3821929316
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.1017703560
Short name T11
Test name
Test status
Simulation time 31390278893 ps
CPU time 946.15 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 198208 kb
Host smart-11a8c3d6-e506-4b88-a5c7-dd692cd69339
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1017703560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.1017703560
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2202398456
Short name T42
Test name
Test status
Simulation time 133595201 ps
CPU time 0.88 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:09:27 PM PDT 24
Peak memory 213644 kb
Host smart-c24faa65-cd25-41d4-b514-c7935f68dbee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202398456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2202398456
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.446420678
Short name T77
Test name
Test status
Simulation time 15204255 ps
CPU time 0.64 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 194676 kb
Host smart-b476da17-cfa4-4dca-be51-aeb27858ff39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446420678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_
csr_rw.446420678
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1398857992
Short name T1
Test name
Test status
Simulation time 297216742 ps
CPU time 3.66 seconds
Started Jun 21 06:12:36 PM PDT 24
Finished Jun 21 06:12:41 PM PDT 24
Peak memory 197980 kb
Host smart-d6e24661-c34f-4a71-bc85-edf5a35ee4f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398857992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1398857992
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1753569660
Short name T114
Test name
Test status
Simulation time 292279188 ps
CPU time 1.21 seconds
Started Jun 21 06:11:01 PM PDT 24
Finished Jun 21 06:11:03 PM PDT 24
Peak memory 197164 kb
Host smart-c10a939f-fc9b-43ed-8272-a37d86bae899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753569660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1753569660
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3256561247
Short name T40
Test name
Test status
Simulation time 462835330 ps
CPU time 1.51 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 197636 kb
Host smart-a0a3e79c-cc9b-4463-ba15-cec3f2523ea5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256561247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3256561247
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1967315139
Short name T44
Test name
Test status
Simulation time 85188296 ps
CPU time 0.59 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:31 PM PDT 24
Peak memory 193844 kb
Host smart-5e0301ab-2294-46f1-9cd0-d5d34fb60746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967315139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1967315139
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1756295420
Short name T97
Test name
Test status
Simulation time 45408077 ps
CPU time 0.68 seconds
Started Jun 21 06:28:01 PM PDT 24
Finished Jun 21 06:28:05 PM PDT 24
Peak memory 194684 kb
Host smart-d2215bae-49a5-483b-9307-8e7d4d453413
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756295420 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1756295420
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1171634683
Short name T110
Test name
Test status
Simulation time 483951295 ps
CPU time 1.42 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 197928 kb
Host smart-5f91f579-4760-494e-b3e1-8e7b9124242b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171634683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1171634683
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1358550516
Short name T78
Test name
Test status
Simulation time 38695779 ps
CPU time 0.65 seconds
Started Jun 21 06:28:04 PM PDT 24
Finished Jun 21 06:28:12 PM PDT 24
Peak memory 194568 kb
Host smart-ccf32070-e7ba-4cec-bbc7-6f7dca1172e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358550516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1358550516
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.2205473238
Short name T840
Test name
Test status
Simulation time 95355316 ps
CPU time 1.46 seconds
Started Jun 21 06:28:03 PM PDT 24
Finished Jun 21 06:28:12 PM PDT 24
Peak memory 197824 kb
Host smart-0fa42274-2bcc-46f1-b509-bebf94c672a9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205473238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.2205473238
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1124101792
Short name T75
Test name
Test status
Simulation time 17719072 ps
CPU time 0.61 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 194496 kb
Host smart-6ecc2f45-af55-44d0-8a66-9107aba1be87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124101792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1124101792
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.53946151
Short name T730
Test name
Test status
Simulation time 156733408 ps
CPU time 1.03 seconds
Started Jun 21 06:28:16 PM PDT 24
Finished Jun 21 06:28:24 PM PDT 24
Peak memory 197680 kb
Host smart-2512f1e5-72e1-4ac6-a00f-f42c6cc8aa3f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53946151 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.53946151
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2104324271
Short name T784
Test name
Test status
Simulation time 14246885 ps
CPU time 0.61 seconds
Started Jun 21 06:28:22 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 194716 kb
Host smart-1665f827-948f-4c30-b94e-5b9d4873ede9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104324271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2104324271
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2965894747
Short name T821
Test name
Test status
Simulation time 45011865 ps
CPU time 0.59 seconds
Started Jun 21 06:28:19 PM PDT 24
Finished Jun 21 06:28:26 PM PDT 24
Peak memory 194192 kb
Host smart-4856467e-af1a-48a7-84ba-e9c0e7ccd14c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965894747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2965894747
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.673708166
Short name T780
Test name
Test status
Simulation time 36114926 ps
CPU time 0.84 seconds
Started Jun 21 06:28:04 PM PDT 24
Finished Jun 21 06:28:14 PM PDT 24
Peak memory 196712 kb
Host smart-52355910-f065-4bde-bd18-01dfa79566e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673708166 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.673708166
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1176682535
Short name T817
Test name
Test status
Simulation time 315949643 ps
CPU time 1.64 seconds
Started Jun 21 06:28:05 PM PDT 24
Finished Jun 21 06:28:15 PM PDT 24
Peak memory 197800 kb
Host smart-45d4d29f-6c2e-43f9-9975-ec8d7b82b7b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176682535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1176682535
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1318725526
Short name T47
Test name
Test status
Simulation time 46899455 ps
CPU time 0.86 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:21 PM PDT 24
Peak memory 196744 kb
Host smart-8807ea5e-f16b-4f49-a70d-fdff94eeed9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318725526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1318725526
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3647137160
Short name T86
Test name
Test status
Simulation time 26430520 ps
CPU time 0.75 seconds
Started Jun 21 06:28:13 PM PDT 24
Finished Jun 21 06:28:20 PM PDT 24
Peak memory 195420 kb
Host smart-654ad6e5-16a8-4d97-a7e5-9157fb779392
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647137160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3647137160
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3697009624
Short name T80
Test name
Test status
Simulation time 2199431399 ps
CPU time 2.5 seconds
Started Jun 21 06:28:20 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 197860 kb
Host smart-542dab38-cf8a-465c-983f-cc42d01ec5cb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697009624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3697009624
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2659444019
Short name T74
Test name
Test status
Simulation time 44957510 ps
CPU time 0.6 seconds
Started Jun 21 06:28:20 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 194336 kb
Host smart-85665efc-4dce-4eac-854e-f3854c674554
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659444019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2659444019
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.756934939
Short name T797
Test name
Test status
Simulation time 33507281 ps
CPU time 0.91 seconds
Started Jun 21 06:28:09 PM PDT 24
Finished Jun 21 06:28:17 PM PDT 24
Peak memory 197612 kb
Host smart-e9015e79-4bbf-468f-af54-023fb751938c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756934939 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.756934939
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1018949263
Short name T796
Test name
Test status
Simulation time 44258598 ps
CPU time 0.67 seconds
Started Jun 21 06:28:08 PM PDT 24
Finished Jun 21 06:28:16 PM PDT 24
Peak memory 194476 kb
Host smart-c5f0a5c8-c38b-4e7b-930f-55b45782ae9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018949263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1018949263
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.445436782
Short name T782
Test name
Test status
Simulation time 12370101 ps
CPU time 0.61 seconds
Started Jun 21 06:28:19 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 193520 kb
Host smart-51bffc17-c160-44b8-833f-7b34030a3589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445436782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.445436782
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1876561500
Short name T757
Test name
Test status
Simulation time 33416662 ps
CPU time 0.86 seconds
Started Jun 21 06:28:12 PM PDT 24
Finished Jun 21 06:28:20 PM PDT 24
Peak memory 197620 kb
Host smart-08d95579-a369-4f8e-95d9-1832af7c5248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876561500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1876561500
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3719094917
Short name T38
Test name
Test status
Simulation time 49271369 ps
CPU time 0.87 seconds
Started Jun 21 06:28:02 PM PDT 24
Finished Jun 21 06:28:10 PM PDT 24
Peak memory 197664 kb
Host smart-51a687f3-314f-4757-bd5a-9fdc1ab271d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719094917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3719094917
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3531908502
Short name T811
Test name
Test status
Simulation time 229614135 ps
CPU time 1.18 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 197796 kb
Host smart-72825635-2d79-4223-8a0f-9d84f2b6c397
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531908502 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3531908502
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.476551865
Short name T83
Test name
Test status
Simulation time 133284755 ps
CPU time 0.62 seconds
Started Jun 21 06:28:41 PM PDT 24
Finished Jun 21 06:28:43 PM PDT 24
Peak memory 194756 kb
Host smart-0a058bee-15dd-49a4-bd44-102cb3ba6da2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476551865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.476551865
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.4066052574
Short name T758
Test name
Test status
Simulation time 12658815 ps
CPU time 0.6 seconds
Started Jun 21 06:28:17 PM PDT 24
Finished Jun 21 06:28:25 PM PDT 24
Peak memory 193452 kb
Host smart-d8996153-0a28-4f60-a408-556be4851413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066052574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.4066052574
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3279519333
Short name T765
Test name
Test status
Simulation time 49906574 ps
CPU time 0.78 seconds
Started Jun 21 06:28:42 PM PDT 24
Finished Jun 21 06:28:44 PM PDT 24
Peak memory 196380 kb
Host smart-3ebfbce1-cd24-4dc6-a0f2-93497d86b75f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279519333 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3279519333
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2242690466
Short name T820
Test name
Test status
Simulation time 196459749 ps
CPU time 1.24 seconds
Started Jun 21 06:28:20 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 197824 kb
Host smart-a153a4af-a517-4c10-bc5b-57e87b9c091b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242690466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2242690466
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.753530259
Short name T109
Test name
Test status
Simulation time 198168977 ps
CPU time 1.41 seconds
Started Jun 21 06:28:26 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 197828 kb
Host smart-828f361c-9e7c-4913-8dc2-75c82bfd0263
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753530259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.753530259
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2896367648
Short name T801
Test name
Test status
Simulation time 32026062 ps
CPU time 1.39 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 197928 kb
Host smart-23f1cb2b-d5eb-4964-9ef7-2b8f1bbcc983
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896367648 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2896367648
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.808364608
Short name T790
Test name
Test status
Simulation time 25339151 ps
CPU time 0.6 seconds
Started Jun 21 06:28:29 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 194544 kb
Host smart-d304dfd4-fb8b-469b-b11b-bec84c6058d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808364608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.808364608
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3714883949
Short name T794
Test name
Test status
Simulation time 13261081 ps
CPU time 0.64 seconds
Started Jun 21 06:28:35 PM PDT 24
Finished Jun 21 06:28:37 PM PDT 24
Peak memory 193372 kb
Host smart-05b75405-7d32-40f2-9267-dd21663ebb3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714883949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3714883949
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.3978647591
Short name T90
Test name
Test status
Simulation time 17535171 ps
CPU time 0.77 seconds
Started Jun 21 06:28:26 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 196600 kb
Host smart-7f107a31-2afb-4785-ac55-4fe2664e1df5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978647591 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.3978647591
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2039850951
Short name T727
Test name
Test status
Simulation time 83572425 ps
CPU time 1.63 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 197868 kb
Host smart-46b47c3a-da17-4740-8436-9d78603572bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039850951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2039850951
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2082194386
Short name T738
Test name
Test status
Simulation time 632716345 ps
CPU time 1.09 seconds
Started Jun 21 06:28:30 PM PDT 24
Finished Jun 21 06:28:33 PM PDT 24
Peak memory 197828 kb
Host smart-8773b5a6-2dc9-4b0e-b655-58f9756bd790
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082194386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2082194386
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.4131148335
Short name T742
Test name
Test status
Simulation time 18740413 ps
CPU time 0.68 seconds
Started Jun 21 06:28:27 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 196208 kb
Host smart-b42136c9-a161-4932-9a62-23a12cdca076
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131148335 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.4131148335
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1022390633
Short name T752
Test name
Test status
Simulation time 44467734 ps
CPU time 0.61 seconds
Started Jun 21 06:28:17 PM PDT 24
Finished Jun 21 06:28:25 PM PDT 24
Peak memory 194516 kb
Host smart-7ef40308-fb34-4e27-aa8e-e2326dc9b2cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022390633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1022390633
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3194142847
Short name T726
Test name
Test status
Simulation time 36001476 ps
CPU time 0.62 seconds
Started Jun 21 06:28:40 PM PDT 24
Finished Jun 21 06:28:42 PM PDT 24
Peak memory 193468 kb
Host smart-fea5f33d-f24b-4c29-8202-e9d7a7e736f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194142847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3194142847
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2199646770
Short name T778
Test name
Test status
Simulation time 40853942 ps
CPU time 0.78 seconds
Started Jun 21 06:28:24 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 196564 kb
Host smart-8622bfe8-2ff4-4916-b481-e7ea7889e9cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199646770 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2199646770
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3795988167
Short name T764
Test name
Test status
Simulation time 20039469 ps
CPU time 1.04 seconds
Started Jun 21 06:28:31 PM PDT 24
Finished Jun 21 06:28:33 PM PDT 24
Peak memory 197580 kb
Host smart-5367d16b-dfa9-441e-9f64-8d8ea4f878fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795988167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3795988167
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3894745876
Short name T48
Test name
Test status
Simulation time 189807616 ps
CPU time 1.41 seconds
Started Jun 21 06:28:27 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 197844 kb
Host smart-b7bd64dc-0323-4da3-ad65-3035dc145602
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894745876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3894745876
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1981588366
Short name T719
Test name
Test status
Simulation time 74240180 ps
CPU time 0.79 seconds
Started Jun 21 06:28:31 PM PDT 24
Finished Jun 21 06:28:33 PM PDT 24
Peak memory 197604 kb
Host smart-0b5704b6-f897-4846-8b2f-13b59caf95a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981588366 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1981588366
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.2742817968
Short name T85
Test name
Test status
Simulation time 14594248 ps
CPU time 0.59 seconds
Started Jun 21 06:28:17 PM PDT 24
Finished Jun 21 06:28:25 PM PDT 24
Peak memory 195140 kb
Host smart-131f6964-a304-49e6-b0fd-766ee4d93ae4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742817968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.2742817968
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2102723221
Short name T781
Test name
Test status
Simulation time 27581951 ps
CPU time 0.58 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 193508 kb
Host smart-0a46624f-26d9-4123-bd6b-de34a085a35a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102723221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2102723221
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1554110189
Short name T777
Test name
Test status
Simulation time 65216734 ps
CPU time 0.76 seconds
Started Jun 21 06:28:35 PM PDT 24
Finished Jun 21 06:28:37 PM PDT 24
Peak memory 195752 kb
Host smart-e0b259e1-6709-463b-a06c-c370011ce712
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554110189 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1554110189
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1697681678
Short name T725
Test name
Test status
Simulation time 130326604 ps
CPU time 2.62 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 197820 kb
Host smart-e71719cd-5eed-4deb-8966-f8aaf7a3badb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697681678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1697681678
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1921356047
Short name T741
Test name
Test status
Simulation time 251164836 ps
CPU time 1.11 seconds
Started Jun 21 06:28:27 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 197828 kb
Host smart-d6da64b3-0e04-4678-b824-37fe39982ee0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921356047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1921356047
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2950028919
Short name T776
Test name
Test status
Simulation time 38159246 ps
CPU time 0.83 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:34 PM PDT 24
Peak memory 197656 kb
Host smart-f837d4de-408c-4fa5-8737-a2b4a2e74381
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950028919 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2950028919
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.576661823
Short name T745
Test name
Test status
Simulation time 13063001 ps
CPU time 0.62 seconds
Started Jun 21 06:28:21 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 194748 kb
Host smart-98bb5587-45a4-4094-9cf3-7325a69e7b2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576661823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio
_csr_rw.576661823
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.207618279
Short name T724
Test name
Test status
Simulation time 19053462 ps
CPU time 0.58 seconds
Started Jun 21 06:28:30 PM PDT 24
Finished Jun 21 06:28:33 PM PDT 24
Peak memory 193408 kb
Host smart-f3331961-69a9-4703-ad3f-2433346ee79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207618279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.207618279
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.1167142046
Short name T91
Test name
Test status
Simulation time 79912504 ps
CPU time 0.77 seconds
Started Jun 21 06:28:22 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 195984 kb
Host smart-fcc64636-b89a-4ec6-bde5-55a81107b312
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167142046 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.1167142046
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.823134636
Short name T839
Test name
Test status
Simulation time 37526117 ps
CPU time 2.05 seconds
Started Jun 21 06:28:18 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 197868 kb
Host smart-9b9b6c18-9961-4a75-801c-00677d7423af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823134636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.823134636
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1818608746
Short name T735
Test name
Test status
Simulation time 50697575 ps
CPU time 0.82 seconds
Started Jun 21 06:28:16 PM PDT 24
Finished Jun 21 06:28:23 PM PDT 24
Peak memory 196928 kb
Host smart-f515deac-e053-4ea9-8b5b-1e8309239274
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818608746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1818608746
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2499543513
Short name T837
Test name
Test status
Simulation time 546038044 ps
CPU time 1.65 seconds
Started Jun 21 06:28:30 PM PDT 24
Finished Jun 21 06:28:34 PM PDT 24
Peak memory 197924 kb
Host smart-dd403ed9-6b7c-4139-a286-f00dab74782f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499543513 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2499543513
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2323603534
Short name T756
Test name
Test status
Simulation time 17260101 ps
CPU time 0.63 seconds
Started Jun 21 06:28:37 PM PDT 24
Finished Jun 21 06:28:38 PM PDT 24
Peak memory 193024 kb
Host smart-c3a1efb8-42bc-42d7-aff2-d76ea634959b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323603534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2323603534
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2977682099
Short name T800
Test name
Test status
Simulation time 14442691 ps
CPU time 0.61 seconds
Started Jun 21 06:28:17 PM PDT 24
Finished Jun 21 06:28:24 PM PDT 24
Peak memory 193448 kb
Host smart-aa5a94d7-697f-4fd4-b7e9-c19ee278c9f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977682099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2977682099
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3542551860
Short name T93
Test name
Test status
Simulation time 18693729 ps
CPU time 0.82 seconds
Started Jun 21 06:28:28 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 195944 kb
Host smart-16443647-f75d-4be6-aafd-4517201a8dc1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542551860 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3542551860
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.501636643
Short name T729
Test name
Test status
Simulation time 24508796 ps
CPU time 1.2 seconds
Started Jun 21 06:28:21 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 197856 kb
Host smart-679a7c04-a2c7-42bc-850a-99fb6a4dfc7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501636643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.501636643
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1055594005
Short name T814
Test name
Test status
Simulation time 92014682 ps
CPU time 1.27 seconds
Started Jun 21 06:28:29 PM PDT 24
Finished Jun 21 06:28:32 PM PDT 24
Peak memory 197580 kb
Host smart-97f0dcbe-5d40-4c2b-a38d-5baa4bccdf43
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055594005 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1055594005
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3059646147
Short name T748
Test name
Test status
Simulation time 13558032 ps
CPU time 0.67 seconds
Started Jun 21 06:28:27 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 194752 kb
Host smart-4a966e54-ba4e-46cc-a629-8cd13cb07438
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059646147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3059646147
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3214857900
Short name T827
Test name
Test status
Simulation time 15173637 ps
CPU time 0.65 seconds
Started Jun 21 06:28:37 PM PDT 24
Finished Jun 21 06:28:39 PM PDT 24
Peak memory 194136 kb
Host smart-84030306-ae4f-438d-beb5-a0ab37aea05d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214857900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3214857900
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.264131632
Short name T96
Test name
Test status
Simulation time 31966466 ps
CPU time 0.75 seconds
Started Jun 21 06:28:21 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 195920 kb
Host smart-1c544825-24d1-42bc-8da5-186dcf5ae614
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264131632 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.264131632
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3885309086
Short name T818
Test name
Test status
Simulation time 53562831 ps
CPU time 1.24 seconds
Started Jun 21 06:28:34 PM PDT 24
Finished Jun 21 06:28:36 PM PDT 24
Peak memory 197792 kb
Host smart-94a2478a-47d1-49df-8c01-b16858142ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885309086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3885309086
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.3024786681
Short name T50
Test name
Test status
Simulation time 408145033 ps
CPU time 1.47 seconds
Started Jun 21 06:28:39 PM PDT 24
Finished Jun 21 06:28:41 PM PDT 24
Peak memory 197736 kb
Host smart-99745470-d5a1-4f97-a23d-46e31d93f0f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024786681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.3024786681
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.1371265850
Short name T787
Test name
Test status
Simulation time 46034824 ps
CPU time 0.95 seconds
Started Jun 21 06:28:33 PM PDT 24
Finished Jun 21 06:28:36 PM PDT 24
Peak memory 197684 kb
Host smart-bed70584-0592-4c4d-b37a-8754bdde2ca9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371265850 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.1371265850
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2175512565
Short name T84
Test name
Test status
Simulation time 16108509 ps
CPU time 0.65 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 194632 kb
Host smart-24c06443-3277-42e3-baf9-2b1db769404e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175512565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2175512565
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.1593514812
Short name T830
Test name
Test status
Simulation time 49952037 ps
CPU time 0.63 seconds
Started Jun 21 06:28:50 PM PDT 24
Finished Jun 21 06:28:51 PM PDT 24
Peak memory 193428 kb
Host smart-53a7288d-2a04-40c5-adac-af11fd8530ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593514812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.1593514812
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3116059943
Short name T92
Test name
Test status
Simulation time 26752334 ps
CPU time 0.72 seconds
Started Jun 21 06:28:46 PM PDT 24
Finished Jun 21 06:28:48 PM PDT 24
Peak memory 194500 kb
Host smart-ce31366e-da46-492f-9547-f04e5c04425d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116059943 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3116059943
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1525673414
Short name T761
Test name
Test status
Simulation time 188261420 ps
CPU time 2.66 seconds
Started Jun 21 06:28:31 PM PDT 24
Finished Jun 21 06:28:36 PM PDT 24
Peak memory 197920 kb
Host smart-4e16c22e-55a8-4dc4-a77f-3176aab0f519
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525673414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1525673414
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2011021525
Short name T836
Test name
Test status
Simulation time 278760327 ps
CPU time 1.16 seconds
Started Jun 21 06:28:29 PM PDT 24
Finished Jun 21 06:28:32 PM PDT 24
Peak memory 197548 kb
Host smart-61466020-3507-4b34-84b0-7ec19d929cab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011021525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2011021525
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.4259818002
Short name T733
Test name
Test status
Simulation time 37898228 ps
CPU time 0.98 seconds
Started Jun 21 06:28:41 PM PDT 24
Finished Jun 21 06:28:43 PM PDT 24
Peak memory 197680 kb
Host smart-29014b1e-bc6d-4b09-bd21-b2bb2926646c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259818002 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.4259818002
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2061083239
Short name T792
Test name
Test status
Simulation time 13892775 ps
CPU time 0.61 seconds
Started Jun 21 06:28:47 PM PDT 24
Finished Jun 21 06:28:48 PM PDT 24
Peak memory 194540 kb
Host smart-df32e39f-1071-4659-bc17-0b803aa11f4b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061083239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2061083239
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3922262284
Short name T835
Test name
Test status
Simulation time 42755735 ps
CPU time 0.59 seconds
Started Jun 21 06:28:24 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 194028 kb
Host smart-6b23d127-425f-4ae8-94a3-420d1bdf8eff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922262284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3922262284
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1274177053
Short name T95
Test name
Test status
Simulation time 17187531 ps
CPU time 0.75 seconds
Started Jun 21 06:28:37 PM PDT 24
Finished Jun 21 06:28:38 PM PDT 24
Peak memory 195976 kb
Host smart-cc499a2b-7dff-4637-805d-6fa7b849ea89
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274177053 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1274177053
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3428086241
Short name T805
Test name
Test status
Simulation time 281305793 ps
CPU time 2.6 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:28:49 PM PDT 24
Peak memory 197856 kb
Host smart-e3f5ae82-9e17-47ac-ae82-141fcd168515
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428086241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3428086241
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2955519426
Short name T46
Test name
Test status
Simulation time 92141654 ps
CPU time 1.14 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:34 PM PDT 24
Peak memory 197836 kb
Host smart-89dac25c-2f17-4411-af5f-2a4b524dc66a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955519426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2955519426
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2443860052
Short name T809
Test name
Test status
Simulation time 193434782 ps
CPU time 0.89 seconds
Started Jun 21 06:28:48 PM PDT 24
Finished Jun 21 06:28:50 PM PDT 24
Peak memory 197616 kb
Host smart-f9fe1c76-255b-4695-9f9d-46910f68ef91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443860052 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2443860052
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2090086045
Short name T72
Test name
Test status
Simulation time 10406716 ps
CPU time 0.59 seconds
Started Jun 21 06:28:45 PM PDT 24
Finished Jun 21 06:28:46 PM PDT 24
Peak memory 193044 kb
Host smart-7825d4af-2123-464f-9a86-6830173f6a60
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090086045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2090086045
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.993119618
Short name T798
Test name
Test status
Simulation time 34749916 ps
CPU time 0.63 seconds
Started Jun 21 06:28:33 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 193488 kb
Host smart-a593393a-1a02-4496-85a8-db410f78db9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993119618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.993119618
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1991807169
Short name T824
Test name
Test status
Simulation time 74680918 ps
CPU time 0.81 seconds
Started Jun 21 06:28:42 PM PDT 24
Finished Jun 21 06:28:44 PM PDT 24
Peak memory 195900 kb
Host smart-8fcfa564-3fc0-452d-addd-7ee416a0e042
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991807169 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1991807169
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3543448681
Short name T773
Test name
Test status
Simulation time 41459355 ps
CPU time 1.17 seconds
Started Jun 21 06:28:37 PM PDT 24
Finished Jun 21 06:28:39 PM PDT 24
Peak memory 197756 kb
Host smart-eda22763-3ca1-4293-a897-caaff6fa2c10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543448681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3543448681
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.1956911701
Short name T789
Test name
Test status
Simulation time 43126042 ps
CPU time 0.84 seconds
Started Jun 21 06:28:33 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 196616 kb
Host smart-26ac8fce-0baa-4d73-af1e-3ec03584c904
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956911701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.1956911701
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1863545178
Short name T87
Test name
Test status
Simulation time 18354088 ps
CPU time 0.81 seconds
Started Jun 21 06:28:33 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 195676 kb
Host smart-a076aa28-592f-45c2-91b6-5710aead183d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863545178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1863545178
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1191524789
Short name T743
Test name
Test status
Simulation time 264296727 ps
CPU time 3.21 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:24 PM PDT 24
Peak memory 197000 kb
Host smart-e73f10d0-3c08-417d-a19f-007aa033ef0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191524789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1191524789
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.523855712
Short name T79
Test name
Test status
Simulation time 35993403 ps
CPU time 0.65 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 194744 kb
Host smart-2762cf7e-ddab-413c-9175-1ffc5eff7ea8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523855712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.523855712
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.762837668
Short name T746
Test name
Test status
Simulation time 49395952 ps
CPU time 0.64 seconds
Started Jun 21 06:28:22 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 196464 kb
Host smart-375a6b55-52e5-4c82-ae00-06340702419d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762837668 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.762837668
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2511209620
Short name T73
Test name
Test status
Simulation time 12787269 ps
CPU time 0.59 seconds
Started Jun 21 06:28:03 PM PDT 24
Finished Jun 21 06:28:11 PM PDT 24
Peak memory 194956 kb
Host smart-51b12271-0dc0-4453-b4c6-a0372d9b7566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511209620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2511209620
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.263055207
Short name T740
Test name
Test status
Simulation time 45831380 ps
CPU time 0.55 seconds
Started Jun 21 06:28:18 PM PDT 24
Finished Jun 21 06:28:26 PM PDT 24
Peak memory 194076 kb
Host smart-50e17e6e-0bf1-4f1d-931d-d1570af1db66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263055207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.263055207
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3430828756
Short name T89
Test name
Test status
Simulation time 146310957 ps
CPU time 0.85 seconds
Started Jun 21 06:28:09 PM PDT 24
Finished Jun 21 06:28:18 PM PDT 24
Peak memory 196040 kb
Host smart-59eadd62-94ba-45ac-b77d-73d12c9464a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430828756 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3430828756
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1506195465
Short name T768
Test name
Test status
Simulation time 34882961 ps
CPU time 1.62 seconds
Started Jun 21 06:28:03 PM PDT 24
Finished Jun 21 06:28:12 PM PDT 24
Peak memory 197832 kb
Host smart-fecc5e21-9997-4704-a18b-7766a317f0cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506195465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1506195465
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.358246912
Short name T36
Test name
Test status
Simulation time 51473035 ps
CPU time 0.93 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 197540 kb
Host smart-1bb0a594-e7cc-4a29-90ce-f2e3683efc99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358246912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.358246912
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2699425275
Short name T731
Test name
Test status
Simulation time 22781272 ps
CPU time 0.61 seconds
Started Jun 21 06:28:37 PM PDT 24
Finished Jun 21 06:28:38 PM PDT 24
Peak memory 193404 kb
Host smart-221d52e9-e80c-4f38-9653-58aa9b9dbb14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699425275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2699425275
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.111217138
Short name T720
Test name
Test status
Simulation time 14430259 ps
CPU time 0.63 seconds
Started Jun 21 06:28:53 PM PDT 24
Finished Jun 21 06:28:55 PM PDT 24
Peak memory 194068 kb
Host smart-99f8d5df-f937-4970-bcc4-7caf0e817422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111217138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.111217138
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1590867781
Short name T751
Test name
Test status
Simulation time 13059020 ps
CPU time 0.54 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:34 PM PDT 24
Peak memory 193388 kb
Host smart-d3973337-15ad-4f89-908e-5b921159a1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590867781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1590867781
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3720206459
Short name T812
Test name
Test status
Simulation time 24767301 ps
CPU time 0.62 seconds
Started Jun 21 06:28:46 PM PDT 24
Finished Jun 21 06:28:47 PM PDT 24
Peak memory 194160 kb
Host smart-ab0d37c2-dfee-4698-86b2-f8e004e7b06f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720206459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3720206459
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2455650141
Short name T760
Test name
Test status
Simulation time 24507886 ps
CPU time 0.61 seconds
Started Jun 21 06:28:35 PM PDT 24
Finished Jun 21 06:28:38 PM PDT 24
Peak memory 193408 kb
Host smart-6b46948b-68a9-4c38-a420-ff9684f09803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455650141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2455650141
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.575662417
Short name T747
Test name
Test status
Simulation time 45657745 ps
CPU time 0.59 seconds
Started Jun 21 06:28:46 PM PDT 24
Finished Jun 21 06:28:47 PM PDT 24
Peak memory 193372 kb
Host smart-07e983d4-0517-4bcc-98e4-94f1dcdec262
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575662417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.575662417
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1643039311
Short name T774
Test name
Test status
Simulation time 16321511 ps
CPU time 0.6 seconds
Started Jun 21 06:28:34 PM PDT 24
Finished Jun 21 06:28:37 PM PDT 24
Peak memory 193416 kb
Host smart-c61de264-48b7-4577-a3a8-31ca8d5d9b61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643039311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1643039311
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.91582499
Short name T838
Test name
Test status
Simulation time 50451632 ps
CPU time 0.61 seconds
Started Jun 21 06:28:41 PM PDT 24
Finished Jun 21 06:28:42 PM PDT 24
Peak memory 194184 kb
Host smart-ecdd80be-2e62-4563-8340-e26f2276c046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91582499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.91582499
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3369694199
Short name T834
Test name
Test status
Simulation time 10848293 ps
CPU time 0.56 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:34 PM PDT 24
Peak memory 193364 kb
Host smart-f729e21e-fdf2-436e-be1c-17ff59d5325c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369694199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3369694199
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.735427365
Short name T723
Test name
Test status
Simulation time 11409793 ps
CPU time 0.63 seconds
Started Jun 21 06:28:29 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 193448 kb
Host smart-a61bd94b-52a1-43ae-81b3-689d468f3e66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735427365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.735427365
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1129256149
Short name T825
Test name
Test status
Simulation time 107737368 ps
CPU time 0.69 seconds
Started Jun 21 06:28:17 PM PDT 24
Finished Jun 21 06:28:24 PM PDT 24
Peak memory 194588 kb
Host smart-c906a85f-0267-46f2-8034-b6de58839c82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129256149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1129256149
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.483215103
Short name T88
Test name
Test status
Simulation time 460839899 ps
CPU time 2.95 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:24 PM PDT 24
Peak memory 197004 kb
Host smart-851d94dd-72cf-4d2a-ac7c-82b460b2e0ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483215103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.483215103
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4185562919
Short name T804
Test name
Test status
Simulation time 16452911 ps
CPU time 0.58 seconds
Started Jun 21 06:28:31 PM PDT 24
Finished Jun 21 06:28:33 PM PDT 24
Peak memory 194188 kb
Host smart-99f600bd-3299-4227-ad1b-c3504b7f078e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185562919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4185562919
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.358046950
Short name T728
Test name
Test status
Simulation time 34019545 ps
CPU time 0.85 seconds
Started Jun 21 06:28:13 PM PDT 24
Finished Jun 21 06:28:20 PM PDT 24
Peak memory 197672 kb
Host smart-c789c3a7-8c49-4126-afc1-9b3580b19d19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358046950 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.358046950
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3768895059
Short name T76
Test name
Test status
Simulation time 12868399 ps
CPU time 0.6 seconds
Started Jun 21 06:27:59 PM PDT 24
Finished Jun 21 06:28:02 PM PDT 24
Peak memory 194064 kb
Host smart-3c1865f0-6413-4292-a4e2-686833f123f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768895059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3768895059
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1525025347
Short name T779
Test name
Test status
Simulation time 61051220 ps
CPU time 0.6 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 193536 kb
Host smart-1b74a1da-0104-4cb1-a285-f2e1f53b4abc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525025347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1525025347
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2387697357
Short name T783
Test name
Test status
Simulation time 17118629 ps
CPU time 0.81 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 196676 kb
Host smart-cc3e7b61-e280-4a59-9b37-fb8279739b32
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387697357 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2387697357
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2213512959
Short name T806
Test name
Test status
Simulation time 232626400 ps
CPU time 1.13 seconds
Started Jun 21 06:28:11 PM PDT 24
Finished Jun 21 06:28:19 PM PDT 24
Peak memory 197916 kb
Host smart-a9566074-6375-4473-ba8b-6ee1331ca120
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213512959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2213512959
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2905086710
Short name T803
Test name
Test status
Simulation time 403722512 ps
CPU time 1.42 seconds
Started Jun 21 06:28:04 PM PDT 24
Finished Jun 21 06:28:13 PM PDT 24
Peak memory 197800 kb
Host smart-927dd54d-aa66-4b41-a0e8-3059160bbb93
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905086710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2905086710
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.436097813
Short name T734
Test name
Test status
Simulation time 151721182 ps
CPU time 0.6 seconds
Started Jun 21 06:28:30 PM PDT 24
Finished Jun 21 06:28:32 PM PDT 24
Peak memory 193948 kb
Host smart-2d801479-6a5c-4db4-b297-0963e9f558d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436097813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.436097813
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3726668791
Short name T823
Test name
Test status
Simulation time 15718252 ps
CPU time 0.66 seconds
Started Jun 21 06:28:42 PM PDT 24
Finished Jun 21 06:28:44 PM PDT 24
Peak memory 194104 kb
Host smart-3d5a5b39-7bcb-4a6e-b31b-8dece444187f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726668791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3726668791
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1545003339
Short name T813
Test name
Test status
Simulation time 24437828 ps
CPU time 0.62 seconds
Started Jun 21 06:28:39 PM PDT 24
Finished Jun 21 06:28:40 PM PDT 24
Peak memory 194108 kb
Host smart-153ef8d2-f268-4a99-ae82-f38c6e632080
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545003339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1545003339
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.711529278
Short name T770
Test name
Test status
Simulation time 15849833 ps
CPU time 0.6 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:34 PM PDT 24
Peak memory 194044 kb
Host smart-4bb1342b-9635-4b2b-948f-6106c694c27b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711529278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.711529278
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3279905626
Short name T721
Test name
Test status
Simulation time 15440463 ps
CPU time 0.62 seconds
Started Jun 21 06:28:40 PM PDT 24
Finished Jun 21 06:28:41 PM PDT 24
Peak memory 194108 kb
Host smart-a699ff51-ea95-4e3e-85f1-766fd1cb805f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279905626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3279905626
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3419537530
Short name T769
Test name
Test status
Simulation time 15213133 ps
CPU time 0.62 seconds
Started Jun 21 06:28:27 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 194132 kb
Host smart-8767063a-1009-4044-91a0-c8337a096d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419537530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3419537530
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3777001240
Short name T771
Test name
Test status
Simulation time 64229021 ps
CPU time 0.59 seconds
Started Jun 21 06:28:44 PM PDT 24
Finished Jun 21 06:28:45 PM PDT 24
Peak memory 193360 kb
Host smart-53ecabc7-f026-4326-a077-d4cec6af6989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777001240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3777001240
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2967746083
Short name T822
Test name
Test status
Simulation time 45649139 ps
CPU time 0.63 seconds
Started Jun 21 06:28:33 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 193468 kb
Host smart-d250602d-195b-48d5-9ed4-2642927a274d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967746083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2967746083
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3699557744
Short name T737
Test name
Test status
Simulation time 61655053 ps
CPU time 0.67 seconds
Started Jun 21 06:28:40 PM PDT 24
Finished Jun 21 06:28:41 PM PDT 24
Peak memory 194128 kb
Host smart-2fffdef8-ad5d-43fb-980e-934cab938bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699557744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3699557744
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2010288622
Short name T717
Test name
Test status
Simulation time 15705241 ps
CPU time 0.64 seconds
Started Jun 21 06:28:34 PM PDT 24
Finished Jun 21 06:28:36 PM PDT 24
Peak memory 194084 kb
Host smart-13bf5183-b437-44c7-848c-b87d5993bdcc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010288622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2010288622
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.46331464
Short name T754
Test name
Test status
Simulation time 62532061 ps
CPU time 0.65 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:21 PM PDT 24
Peak memory 194868 kb
Host smart-83844abe-6cc7-4d4a-906b-7299f77c7289
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46331464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
gpio_csr_aliasing.46331464
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3215816533
Short name T759
Test name
Test status
Simulation time 415500298 ps
CPU time 2.31 seconds
Started Jun 21 06:28:17 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 197792 kb
Host smart-ac66bae1-8943-46e3-a7ef-053f70415212
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215816533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3215816533
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3216162216
Short name T815
Test name
Test status
Simulation time 16366395 ps
CPU time 0.62 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 194512 kb
Host smart-8ff4235f-fa6b-464f-b510-cc029c702bb4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216162216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3216162216
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3102534731
Short name T810
Test name
Test status
Simulation time 39226629 ps
CPU time 1.89 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:23 PM PDT 24
Peak memory 197892 kb
Host smart-6faccf73-1158-4a6a-99c2-6bbc55e92384
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102534731 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3102534731
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.332000459
Short name T807
Test name
Test status
Simulation time 18665029 ps
CPU time 0.57 seconds
Started Jun 21 06:28:01 PM PDT 24
Finished Jun 21 06:28:07 PM PDT 24
Peak memory 194180 kb
Host smart-662bb434-cbdd-4c51-8ea4-f837a513be65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332000459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.332000459
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1083685514
Short name T832
Test name
Test status
Simulation time 15454673 ps
CPU time 0.62 seconds
Started Jun 21 06:28:13 PM PDT 24
Finished Jun 21 06:28:20 PM PDT 24
Peak memory 193524 kb
Host smart-c84b1fe7-c16f-4b83-8efd-74b7cc60dc29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083685514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1083685514
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2735934190
Short name T772
Test name
Test status
Simulation time 34434423 ps
CPU time 0.81 seconds
Started Jun 21 06:28:09 PM PDT 24
Finished Jun 21 06:28:18 PM PDT 24
Peak memory 195748 kb
Host smart-a91e1f4c-cba7-44dc-aa9f-17990769d10b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735934190 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2735934190
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1037004928
Short name T791
Test name
Test status
Simulation time 70413941 ps
CPU time 1.44 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 197824 kb
Host smart-f64c6b77-5f83-4e27-86a9-ccbd48066357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037004928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1037004928
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.386318634
Short name T49
Test name
Test status
Simulation time 125813509 ps
CPU time 1.23 seconds
Started Jun 21 06:28:13 PM PDT 24
Finished Jun 21 06:28:21 PM PDT 24
Peak memory 197844 kb
Host smart-ed71b943-82cd-4ec5-8681-bffc5f73e07c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386318634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.386318634
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3243563773
Short name T785
Test name
Test status
Simulation time 23354693 ps
CPU time 0.58 seconds
Started Jun 21 06:28:27 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 193404 kb
Host smart-fbcfdfb0-1ec8-4ce0-8c80-ec35adadc650
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243563773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3243563773
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1996849967
Short name T749
Test name
Test status
Simulation time 15513455 ps
CPU time 0.65 seconds
Started Jun 21 06:28:43 PM PDT 24
Finished Jun 21 06:28:44 PM PDT 24
Peak memory 194064 kb
Host smart-7a634961-ec39-4b80-94c2-361da7ba4b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996849967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1996849967
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.111481270
Short name T736
Test name
Test status
Simulation time 22408455 ps
CPU time 0.61 seconds
Started Jun 21 06:28:23 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 194156 kb
Host smart-f30821f7-1b20-4b8b-adbe-c51622e2cdba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111481270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.111481270
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.116840895
Short name T799
Test name
Test status
Simulation time 14384273 ps
CPU time 0.59 seconds
Started Jun 21 06:28:39 PM PDT 24
Finished Jun 21 06:28:40 PM PDT 24
Peak memory 193416 kb
Host smart-3192bd48-ef28-4c61-876d-a7fbd2d5f38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116840895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.116840895
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1521046272
Short name T744
Test name
Test status
Simulation time 27070934 ps
CPU time 0.63 seconds
Started Jun 21 06:28:28 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 193476 kb
Host smart-6ec6e271-29d3-40d4-9e93-1cf140882c0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521046272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1521046272
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.3417993749
Short name T750
Test name
Test status
Simulation time 41146375 ps
CPU time 0.58 seconds
Started Jun 21 06:28:27 PM PDT 24
Finished Jun 21 06:28:30 PM PDT 24
Peak memory 193464 kb
Host smart-8de8cb70-1bfc-44f8-9018-f21e06334ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417993749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.3417993749
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3818008972
Short name T739
Test name
Test status
Simulation time 13243072 ps
CPU time 0.6 seconds
Started Jun 21 06:28:34 PM PDT 24
Finished Jun 21 06:28:36 PM PDT 24
Peak memory 193396 kb
Host smart-64b24711-b4b1-4a8f-af10-27edb8a4d53a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818008972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3818008972
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.1359248290
Short name T795
Test name
Test status
Simulation time 47624527 ps
CPU time 0.6 seconds
Started Jun 21 06:28:36 PM PDT 24
Finished Jun 21 06:28:38 PM PDT 24
Peak memory 193468 kb
Host smart-8ce87e8a-5ec5-4fb9-9373-e4bf7cdd056b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359248290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.1359248290
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.961953829
Short name T826
Test name
Test status
Simulation time 79777159 ps
CPU time 0.69 seconds
Started Jun 21 06:28:50 PM PDT 24
Finished Jun 21 06:28:51 PM PDT 24
Peak memory 194108 kb
Host smart-9245b24e-e42d-45cd-9446-3c9a314a60d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961953829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.961953829
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2152289021
Short name T786
Test name
Test status
Simulation time 24047354 ps
CPU time 0.67 seconds
Started Jun 21 06:28:42 PM PDT 24
Finished Jun 21 06:28:44 PM PDT 24
Peak memory 193368 kb
Host smart-aa7d19bd-3bcb-4557-9743-0cfd31055501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152289021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2152289021
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1837932115
Short name T722
Test name
Test status
Simulation time 70158121 ps
CPU time 0.88 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:23 PM PDT 24
Peak memory 197592 kb
Host smart-07d8168d-76b1-4c39-b85d-88a4b74cf416
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837932115 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1837932115
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.2248637558
Short name T108
Test name
Test status
Simulation time 20647410 ps
CPU time 0.64 seconds
Started Jun 21 06:28:16 PM PDT 24
Finished Jun 21 06:28:23 PM PDT 24
Peak memory 194312 kb
Host smart-f51ffc60-568b-4ccb-a64c-293f625f7b03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248637558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.2248637558
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2807062617
Short name T753
Test name
Test status
Simulation time 73035568 ps
CPU time 0.61 seconds
Started Jun 21 06:28:12 PM PDT 24
Finished Jun 21 06:28:19 PM PDT 24
Peak memory 193524 kb
Host smart-6168132e-7b40-4fbb-af87-be1a89341d3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807062617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2807062617
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2639006664
Short name T802
Test name
Test status
Simulation time 126604163 ps
CPU time 0.82 seconds
Started Jun 21 06:28:32 PM PDT 24
Finished Jun 21 06:28:35 PM PDT 24
Peak memory 196172 kb
Host smart-82e5590a-6ae1-4676-a722-7224f5094a2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639006664 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2639006664
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3565613559
Short name T766
Test name
Test status
Simulation time 366033609 ps
CPU time 1.77 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:23 PM PDT 24
Peak memory 197832 kb
Host smart-aa5849a3-4baa-4545-a22b-2a3e324922d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565613559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3565613559
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2047119139
Short name T37
Test name
Test status
Simulation time 878852659 ps
CPU time 1.38 seconds
Started Jun 21 06:28:20 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 197832 kb
Host smart-18b4fb8a-37e8-4a75-a4b4-e78bbed59f4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047119139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2047119139
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.390663839
Short name T829
Test name
Test status
Simulation time 74913565 ps
CPU time 0.99 seconds
Started Jun 21 06:28:19 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 197620 kb
Host smart-f31d1d2b-4fc7-4960-a00d-97fb1dcbf65c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390663839 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.390663839
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2744788836
Short name T762
Test name
Test status
Simulation time 16889870 ps
CPU time 0.6 seconds
Started Jun 21 06:28:22 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 194092 kb
Host smart-5f6279d8-4565-4495-bc5a-94ac26a3691f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744788836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2744788836
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.3588849145
Short name T94
Test name
Test status
Simulation time 49613266 ps
CPU time 0.7 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:21 PM PDT 24
Peak memory 196520 kb
Host smart-5a592abd-14f8-48af-a3b7-18c9757967f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588849145 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.3588849145
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.1364534056
Short name T775
Test name
Test status
Simulation time 257126766 ps
CPU time 2.26 seconds
Started Jun 21 06:28:14 PM PDT 24
Finished Jun 21 06:28:23 PM PDT 24
Peak memory 197824 kb
Host smart-ad9f10a9-2429-41f8-9090-03c8f935179b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364534056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.1364534056
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3461132753
Short name T816
Test name
Test status
Simulation time 198089600 ps
CPU time 1.38 seconds
Started Jun 21 06:28:13 PM PDT 24
Finished Jun 21 06:28:21 PM PDT 24
Peak memory 197636 kb
Host smart-1d72a10b-a615-421e-94b7-981f7b60b798
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461132753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3461132753
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3132650807
Short name T718
Test name
Test status
Simulation time 68371525 ps
CPU time 0.71 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 197312 kb
Host smart-2494220e-f93d-414e-9460-06cfc3bc00ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132650807 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3132650807
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1250370020
Short name T82
Test name
Test status
Simulation time 79945557 ps
CPU time 0.62 seconds
Started Jun 21 06:28:19 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 195252 kb
Host smart-899013e3-6afb-46b0-a885-a9f8e33386c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250370020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1250370020
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3874463110
Short name T767
Test name
Test status
Simulation time 41958434 ps
CPU time 0.57 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:22 PM PDT 24
Peak memory 193492 kb
Host smart-7029c586-574b-4e4a-8e38-14977854a875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874463110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3874463110
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.907426335
Short name T828
Test name
Test status
Simulation time 154449873 ps
CPU time 0.8 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:23 PM PDT 24
Peak memory 195828 kb
Host smart-cffdc569-0bd3-4355-a50e-cd9810f3b20e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907426335 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.907426335
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2007094455
Short name T732
Test name
Test status
Simulation time 173690623 ps
CPU time 1.92 seconds
Started Jun 21 06:28:15 PM PDT 24
Finished Jun 21 06:28:24 PM PDT 24
Peak memory 197724 kb
Host smart-e1d516c2-be06-47c5-bdb2-274b815c7e5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007094455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2007094455
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1876641381
Short name T831
Test name
Test status
Simulation time 91532381 ps
CPU time 0.77 seconds
Started Jun 21 06:28:25 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 197616 kb
Host smart-9181f62f-bebd-4b62-971b-35715de3d33c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876641381 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1876641381
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.3502665596
Short name T808
Test name
Test status
Simulation time 30128651 ps
CPU time 0.57 seconds
Started Jun 21 06:28:22 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 194288 kb
Host smart-0e3ac588-27ac-4568-993f-b4e1c47b6790
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502665596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.3502665596
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.484991669
Short name T793
Test name
Test status
Simulation time 26287352 ps
CPU time 0.58 seconds
Started Jun 21 06:28:16 PM PDT 24
Finished Jun 21 06:28:24 PM PDT 24
Peak memory 194076 kb
Host smart-1c8be8a4-926f-4094-89f8-8f6c028b143c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484991669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.484991669
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.773276333
Short name T81
Test name
Test status
Simulation time 21418118 ps
CPU time 0.7 seconds
Started Jun 21 06:28:13 PM PDT 24
Finished Jun 21 06:28:20 PM PDT 24
Peak memory 194280 kb
Host smart-d7830cde-512a-42f2-b7df-eb8af1a8a5a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773276333 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.773276333
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1722270199
Short name T788
Test name
Test status
Simulation time 321010953 ps
CPU time 2.95 seconds
Started Jun 21 06:28:12 PM PDT 24
Finished Jun 21 06:28:21 PM PDT 24
Peak memory 197796 kb
Host smart-abed2eaf-cd2f-4021-a96d-5e30db030f70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722270199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1722270199
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2372065902
Short name T51
Test name
Test status
Simulation time 45875566 ps
CPU time 0.9 seconds
Started Jun 21 06:28:09 PM PDT 24
Finished Jun 21 06:28:18 PM PDT 24
Peak memory 197580 kb
Host smart-06d6b8cc-3e86-46f2-b40a-954c428bb351
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372065902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2372065902
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.729323284
Short name T715
Test name
Test status
Simulation time 168257897 ps
CPU time 0.72 seconds
Started Jun 21 06:28:28 PM PDT 24
Finished Jun 21 06:28:31 PM PDT 24
Peak memory 197600 kb
Host smart-38e85b4a-39d3-4d2f-a5d8-626f5655a215
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729323284 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.729323284
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2231085963
Short name T763
Test name
Test status
Simulation time 20015868 ps
CPU time 0.57 seconds
Started Jun 21 06:28:09 PM PDT 24
Finished Jun 21 06:28:17 PM PDT 24
Peak memory 193032 kb
Host smart-f17ad9f1-7f41-43ce-bae1-b30a36c6bbf0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231085963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2231085963
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.727532382
Short name T755
Test name
Test status
Simulation time 27561380 ps
CPU time 0.64 seconds
Started Jun 21 06:28:21 PM PDT 24
Finished Jun 21 06:28:27 PM PDT 24
Peak memory 194072 kb
Host smart-558ead25-94b4-4d46-b164-92821d258ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727532382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.727532382
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.513637089
Short name T819
Test name
Test status
Simulation time 59458718 ps
CPU time 0.76 seconds
Started Jun 21 06:28:22 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 195852 kb
Host smart-9b8a68be-4648-44f5-b1d2-6e408057cbda
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513637089 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.513637089
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3487360237
Short name T716
Test name
Test status
Simulation time 462641770 ps
CPU time 1.78 seconds
Started Jun 21 06:28:22 PM PDT 24
Finished Jun 21 06:28:29 PM PDT 24
Peak memory 197824 kb
Host smart-4cd2ed5d-ef01-460c-a51d-00a660023167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487360237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3487360237
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.906364125
Short name T833
Test name
Test status
Simulation time 88468923 ps
CPU time 1.29 seconds
Started Jun 21 06:28:21 PM PDT 24
Finished Jun 21 06:28:28 PM PDT 24
Peak memory 197788 kb
Host smart-a20f555e-5c2d-4e10-b400-815ab14953d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906364125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.906364125
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4033761300
Short name T452
Test name
Test status
Simulation time 13110775 ps
CPU time 0.56 seconds
Started Jun 21 06:09:18 PM PDT 24
Finished Jun 21 06:09:19 PM PDT 24
Peak memory 193772 kb
Host smart-b12ec4c7-c763-4e96-aead-8d28266a6666
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033761300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4033761300
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2676813166
Short name T440
Test name
Test status
Simulation time 184747946 ps
CPU time 0.71 seconds
Started Jun 21 06:09:15 PM PDT 24
Finished Jun 21 06:09:16 PM PDT 24
Peak memory 194772 kb
Host smart-19c76471-b31e-4e6c-b333-074cef3f968f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676813166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2676813166
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2987569072
Short name T554
Test name
Test status
Simulation time 1189749804 ps
CPU time 20.09 seconds
Started Jun 21 06:09:20 PM PDT 24
Finished Jun 21 06:09:42 PM PDT 24
Peak memory 198016 kb
Host smart-ed3c6135-57e0-43c8-b193-a7a9684c29df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987569072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2987569072
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3030734569
Short name T578
Test name
Test status
Simulation time 283199676 ps
CPU time 1.09 seconds
Started Jun 21 06:09:14 PM PDT 24
Finished Jun 21 06:09:16 PM PDT 24
Peak memory 196408 kb
Host smart-8b3f47a9-670d-4f0b-85b8-5ec34061f85d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030734569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3030734569
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3304571582
Short name T581
Test name
Test status
Simulation time 66311871 ps
CPU time 1.23 seconds
Started Jun 21 06:09:15 PM PDT 24
Finished Jun 21 06:09:17 PM PDT 24
Peak memory 195852 kb
Host smart-5fbc5b06-797d-40f5-9b3b-4b89e9a5f3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304571582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3304571582
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.288310453
Short name T649
Test name
Test status
Simulation time 117838957 ps
CPU time 2.77 seconds
Started Jun 21 06:09:16 PM PDT 24
Finished Jun 21 06:09:19 PM PDT 24
Peak memory 198164 kb
Host smart-171aeb0b-dffa-47d6-a7d8-838ef65a2193
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288310453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.288310453
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3998686172
Short name T280
Test name
Test status
Simulation time 125813916 ps
CPU time 2.71 seconds
Started Jun 21 06:09:15 PM PDT 24
Finished Jun 21 06:09:18 PM PDT 24
Peak memory 195808 kb
Host smart-6dd7f0cd-56dc-4429-a66e-f6de59d39948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998686172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3998686172
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3477862012
Short name T325
Test name
Test status
Simulation time 140349018 ps
CPU time 0.77 seconds
Started Jun 21 06:09:15 PM PDT 24
Finished Jun 21 06:09:16 PM PDT 24
Peak memory 196040 kb
Host smart-777278ac-37ee-469c-bc60-4496279ffae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477862012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3477862012
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4117995635
Short name T565
Test name
Test status
Simulation time 180187207 ps
CPU time 1.25 seconds
Started Jun 21 06:09:13 PM PDT 24
Finished Jun 21 06:09:15 PM PDT 24
Peak memory 195844 kb
Host smart-0c4220c5-0f05-492c-b7f5-006731376c31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117995635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4117995635
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1059635056
Short name T520
Test name
Test status
Simulation time 51316815 ps
CPU time 2.4 seconds
Started Jun 21 06:09:15 PM PDT 24
Finished Jun 21 06:09:18 PM PDT 24
Peak memory 198020 kb
Host smart-f3bd60a1-b3ec-4657-bba4-121449c6a2cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059635056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1059635056
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.3562133793
Short name T43
Test name
Test status
Simulation time 189830231 ps
CPU time 0.97 seconds
Started Jun 21 06:09:18 PM PDT 24
Finished Jun 21 06:09:20 PM PDT 24
Peak memory 214704 kb
Host smart-597c23d8-2dc6-456e-bf15-5765facc86da
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562133793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.3562133793
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.248791559
Short name T497
Test name
Test status
Simulation time 51780357 ps
CPU time 1.11 seconds
Started Jun 21 06:09:04 PM PDT 24
Finished Jun 21 06:09:06 PM PDT 24
Peak memory 195788 kb
Host smart-2209f66a-fd60-4d55-ace1-db797db9adc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248791559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.248791559
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3929133608
Short name T139
Test name
Test status
Simulation time 85180679 ps
CPU time 0.96 seconds
Started Jun 21 06:09:04 PM PDT 24
Finished Jun 21 06:09:06 PM PDT 24
Peak memory 195292 kb
Host smart-1bc5242a-28ce-43b6-86a6-e8c79645f680
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929133608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3929133608
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.106468226
Short name T682
Test name
Test status
Simulation time 10942638198 ps
CPU time 55.59 seconds
Started Jun 21 06:09:21 PM PDT 24
Finished Jun 21 06:10:17 PM PDT 24
Peak memory 198160 kb
Host smart-99ee4268-17e0-4b20-aae5-d62bcebb67bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106468226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.106468226
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.7129176
Short name T256
Test name
Test status
Simulation time 17547682 ps
CPU time 0.55 seconds
Started Jun 21 06:09:27 PM PDT 24
Finished Jun 21 06:09:28 PM PDT 24
Peak memory 193880 kb
Host smart-3094ecb8-560d-4474-a866-7c345a6d5eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7129176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.7129176
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.4073659974
Short name T512
Test name
Test status
Simulation time 94919335 ps
CPU time 0.74 seconds
Started Jun 21 06:09:14 PM PDT 24
Finished Jun 21 06:09:15 PM PDT 24
Peak memory 194940 kb
Host smart-4a667521-7118-4111-8b09-eb37decff5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073659974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.4073659974
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3436534690
Short name T276
Test name
Test status
Simulation time 278239143 ps
CPU time 7.82 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:35 PM PDT 24
Peak memory 198008 kb
Host smart-e81d8d78-4d57-46c3-91b3-102e7acd1574
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436534690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3436534690
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.820663118
Short name T585
Test name
Test status
Simulation time 223343475 ps
CPU time 0.84 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:09:26 PM PDT 24
Peak memory 195800 kb
Host smart-b4dfdfb4-92ee-4eef-b421-be2e8b3c7a00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820663118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.820663118
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2322704063
Short name T318
Test name
Test status
Simulation time 181860349 ps
CPU time 1.26 seconds
Started Jun 21 06:09:20 PM PDT 24
Finished Jun 21 06:09:22 PM PDT 24
Peak memory 198148 kb
Host smart-8df4ebe6-7f75-4bf5-a2e3-42ffc4ff952c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322704063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2322704063
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1128235797
Short name T695
Test name
Test status
Simulation time 55358268 ps
CPU time 2.27 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:09:27 PM PDT 24
Peak memory 198172 kb
Host smart-3634f7a9-1af3-4911-8ab1-071ffd22a2fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128235797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1128235797
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.4051842336
Short name T270
Test name
Test status
Simulation time 349257124 ps
CPU time 2.78 seconds
Started Jun 21 06:09:14 PM PDT 24
Finished Jun 21 06:09:18 PM PDT 24
Peak memory 197348 kb
Host smart-e77e7ee7-f216-4bf7-9c38-ae8e3902352c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051842336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
4051842336
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.185874122
Short name T366
Test name
Test status
Simulation time 34528718 ps
CPU time 0.82 seconds
Started Jun 21 06:09:16 PM PDT 24
Finished Jun 21 06:09:18 PM PDT 24
Peak memory 195488 kb
Host smart-22086a61-4803-423b-bc6b-02ec022ff7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185874122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.185874122
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1341403323
Short name T455
Test name
Test status
Simulation time 215974497 ps
CPU time 1.25 seconds
Started Jun 21 06:09:16 PM PDT 24
Finished Jun 21 06:09:18 PM PDT 24
Peak memory 197036 kb
Host smart-15092d46-f270-4547-9719-89086d59b3c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341403323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1341403323
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3063970066
Short name T397
Test name
Test status
Simulation time 272358372 ps
CPU time 4.82 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:31 PM PDT 24
Peak memory 197984 kb
Host smart-1ba36958-fd04-4cd8-b825-014a5ed20105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063970066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3063970066
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.455111519
Short name T371
Test name
Test status
Simulation time 214061409 ps
CPU time 1.28 seconds
Started Jun 21 06:09:15 PM PDT 24
Finished Jun 21 06:09:17 PM PDT 24
Peak memory 195680 kb
Host smart-886dc3a3-19b0-4d27-95fc-6a032f56eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455111519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.455111519
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2841865133
Short name T294
Test name
Test status
Simulation time 249326963 ps
CPU time 1.3 seconds
Started Jun 21 06:09:21 PM PDT 24
Finished Jun 21 06:09:23 PM PDT 24
Peak memory 196620 kb
Host smart-f79cd807-8b80-4b2b-a23f-f7a2079853ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841865133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2841865133
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.2878774366
Short name T537
Test name
Test status
Simulation time 10142191459 ps
CPU time 64.67 seconds
Started Jun 21 06:09:23 PM PDT 24
Finished Jun 21 06:10:28 PM PDT 24
Peak memory 198184 kb
Host smart-afc68c06-902f-4424-bdaa-b4b384f6e140
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878774366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.2878774366
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.3880085374
Short name T68
Test name
Test status
Simulation time 69343424493 ps
CPU time 954.65 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:25:21 PM PDT 24
Peak memory 198256 kb
Host smart-5221a7ba-4174-44eb-9559-22b7042b2cf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3880085374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.3880085374
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1556778810
Short name T241
Test name
Test status
Simulation time 43722243 ps
CPU time 0.62 seconds
Started Jun 21 06:10:14 PM PDT 24
Finished Jun 21 06:10:15 PM PDT 24
Peak memory 194868 kb
Host smart-5c2a12b3-39c7-42ec-8a66-b711ae2ef6f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556778810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1556778810
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2439193507
Short name T231
Test name
Test status
Simulation time 26556498 ps
CPU time 0.73 seconds
Started Jun 21 06:10:11 PM PDT 24
Finished Jun 21 06:10:12 PM PDT 24
Peak memory 194180 kb
Host smart-6a0123a7-8cc1-4578-a3ef-6b23686bcaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439193507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2439193507
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.1846312762
Short name T668
Test name
Test status
Simulation time 1183825959 ps
CPU time 15.73 seconds
Started Jun 21 06:10:12 PM PDT 24
Finished Jun 21 06:10:29 PM PDT 24
Peak memory 196264 kb
Host smart-419e2278-54fb-42ac-842b-1fd3d42d8568
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846312762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.1846312762
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1626908018
Short name T702
Test name
Test status
Simulation time 44444893 ps
CPU time 0.86 seconds
Started Jun 21 06:10:11 PM PDT 24
Finished Jun 21 06:10:13 PM PDT 24
Peak memory 196628 kb
Host smart-c68272e5-5eaa-429b-8b94-6112177f5c1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626908018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1626908018
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1857827428
Short name T472
Test name
Test status
Simulation time 71049127 ps
CPU time 1.13 seconds
Started Jun 21 06:10:11 PM PDT 24
Finished Jun 21 06:10:13 PM PDT 24
Peak memory 196136 kb
Host smart-f6122786-b18c-4cf8-afcb-92b20de32f94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857827428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1857827428
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3508117614
Short name T401
Test name
Test status
Simulation time 175019855 ps
CPU time 1.55 seconds
Started Jun 21 06:10:12 PM PDT 24
Finished Jun 21 06:10:15 PM PDT 24
Peak memory 196072 kb
Host smart-9ca8d3d4-563b-4ce5-87c3-f3493a5583b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508117614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3508117614
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2995459320
Short name T136
Test name
Test status
Simulation time 22024928 ps
CPU time 0.76 seconds
Started Jun 21 06:10:12 PM PDT 24
Finished Jun 21 06:10:15 PM PDT 24
Peak memory 195268 kb
Host smart-d18bb42e-1411-4eee-a54e-3ec90348b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995459320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2995459320
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2857115369
Short name T321
Test name
Test status
Simulation time 693453825 ps
CPU time 1.29 seconds
Started Jun 21 06:10:13 PM PDT 24
Finished Jun 21 06:10:16 PM PDT 24
Peak memory 197108 kb
Host smart-8c702be3-3cee-49f0-b43b-be28d8eb2d99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857115369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2857115369
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.3889271910
Short name T282
Test name
Test status
Simulation time 392137026 ps
CPU time 4.62 seconds
Started Jun 21 06:10:14 PM PDT 24
Finished Jun 21 06:10:19 PM PDT 24
Peak memory 197936 kb
Host smart-7990c658-d90c-476e-9077-bc5ecf6f2540
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889271910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.3889271910
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1766716820
Short name T597
Test name
Test status
Simulation time 25533292 ps
CPU time 0.91 seconds
Started Jun 21 06:10:11 PM PDT 24
Finished Jun 21 06:10:13 PM PDT 24
Peak memory 196484 kb
Host smart-bba03686-dc0e-478b-9ebb-b774ba790567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766716820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1766716820
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3165641932
Short name T407
Test name
Test status
Simulation time 156069290 ps
CPU time 1.7 seconds
Started Jun 21 06:10:12 PM PDT 24
Finished Jun 21 06:10:15 PM PDT 24
Peak memory 196796 kb
Host smart-642382a5-d9e0-4303-a471-f16d5290e64d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165641932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3165641932
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3965526875
Short name T414
Test name
Test status
Simulation time 6695012516 ps
CPU time 178.16 seconds
Started Jun 21 06:10:13 PM PDT 24
Finished Jun 21 06:13:12 PM PDT 24
Peak memory 198184 kb
Host smart-b83fb80d-f7d6-44bd-9e8a-8a34357f21af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965526875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3965526875
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3346626808
Short name T57
Test name
Test status
Simulation time 14824248 ps
CPU time 0.61 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:23 PM PDT 24
Peak memory 194496 kb
Host smart-8e52a681-b290-435e-99b2-931612d33e11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346626808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3346626808
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2541639960
Short name T471
Test name
Test status
Simulation time 24645312 ps
CPU time 0.75 seconds
Started Jun 21 06:10:13 PM PDT 24
Finished Jun 21 06:10:15 PM PDT 24
Peak memory 194152 kb
Host smart-15aad3a4-6779-4915-94f4-502e5d8fb445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541639960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2541639960
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1829029745
Short name T226
Test name
Test status
Simulation time 2788664990 ps
CPU time 10.56 seconds
Started Jun 21 06:10:11 PM PDT 24
Finished Jun 21 06:10:22 PM PDT 24
Peak memory 196904 kb
Host smart-51696012-9acf-4d56-bac9-95dfea67bcd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829029745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1829029745
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.1785116067
Short name T255
Test name
Test status
Simulation time 577782317 ps
CPU time 0.96 seconds
Started Jun 21 06:10:19 PM PDT 24
Finished Jun 21 06:10:21 PM PDT 24
Peak memory 196880 kb
Host smart-5f809313-ddb6-49ed-8030-3ee529e5d6c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785116067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.1785116067
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.6598316
Short name T517
Test name
Test status
Simulation time 72941292 ps
CPU time 0.93 seconds
Started Jun 21 06:10:10 PM PDT 24
Finished Jun 21 06:10:12 PM PDT 24
Peak memory 196832 kb
Host smart-4db5338c-352c-43ba-b1b6-e33d535c6167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6598316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.6598316
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.3082924107
Short name T111
Test name
Test status
Simulation time 88618642 ps
CPU time 1.02 seconds
Started Jun 21 06:10:13 PM PDT 24
Finished Jun 21 06:10:15 PM PDT 24
Peak memory 196252 kb
Host smart-f32184e1-4a09-43e2-999d-307c65377367
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082924107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.3082924107
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.943780908
Short name T145
Test name
Test status
Simulation time 379741868 ps
CPU time 1.64 seconds
Started Jun 21 06:10:15 PM PDT 24
Finished Jun 21 06:10:17 PM PDT 24
Peak memory 196212 kb
Host smart-931493eb-8c6f-4b1f-a6f6-2ec931b9425e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943780908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
943780908
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2127136433
Short name T604
Test name
Test status
Simulation time 36044103 ps
CPU time 1.28 seconds
Started Jun 21 06:10:10 PM PDT 24
Finished Jun 21 06:10:12 PM PDT 24
Peak memory 197052 kb
Host smart-03d26f2b-3342-4725-9add-bffa7b37172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127136433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2127136433
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.2443563777
Short name T309
Test name
Test status
Simulation time 79003342 ps
CPU time 0.74 seconds
Started Jun 21 06:10:12 PM PDT 24
Finished Jun 21 06:10:13 PM PDT 24
Peak memory 195404 kb
Host smart-4f809dd8-f789-4314-a57a-8a6bb4c0c7b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443563777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.2443563777
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.459855545
Short name T237
Test name
Test status
Simulation time 202724851 ps
CPU time 2.06 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:24 PM PDT 24
Peak memory 198024 kb
Host smart-07e4b6bb-9af4-4575-8967-07cabd69d6f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459855545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.459855545
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3470998032
Short name T58
Test name
Test status
Simulation time 40164541 ps
CPU time 0.89 seconds
Started Jun 21 06:10:10 PM PDT 24
Finished Jun 21 06:10:12 PM PDT 24
Peak memory 196256 kb
Host smart-69ff7b38-de83-438e-bd43-6498d358e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470998032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3470998032
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3792955228
Short name T662
Test name
Test status
Simulation time 31267886 ps
CPU time 0.86 seconds
Started Jun 21 06:10:12 PM PDT 24
Finished Jun 21 06:10:14 PM PDT 24
Peak memory 195276 kb
Host smart-28279eb8-96cc-4514-9c29-a4fe16045bf6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792955228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3792955228
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.868288313
Short name T203
Test name
Test status
Simulation time 4608555186 ps
CPU time 103.63 seconds
Started Jun 21 06:10:19 PM PDT 24
Finished Jun 21 06:12:03 PM PDT 24
Peak memory 198132 kb
Host smart-3717ab7a-cebc-4d45-b91f-04777b9cbc3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868288313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.868288313
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2362462632
Short name T481
Test name
Test status
Simulation time 188038424 ps
CPU time 0.63 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:23 PM PDT 24
Peak memory 194532 kb
Host smart-6390ecdb-cddf-4289-b420-7079fbc57966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362462632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2362462632
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3114589151
Short name T187
Test name
Test status
Simulation time 20219242 ps
CPU time 0.66 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:22 PM PDT 24
Peak memory 194008 kb
Host smart-871d3efc-35bc-4f23-9c9d-0fbf31d6ddad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114589151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3114589151
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3796299706
Short name T176
Test name
Test status
Simulation time 1541866818 ps
CPU time 14.25 seconds
Started Jun 21 06:10:19 PM PDT 24
Finished Jun 21 06:10:34 PM PDT 24
Peak memory 196856 kb
Host smart-d95c5ac9-e80c-4eeb-9097-361e72633403
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796299706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3796299706
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.4147109731
Short name T166
Test name
Test status
Simulation time 53014147 ps
CPU time 0.79 seconds
Started Jun 21 06:10:22 PM PDT 24
Finished Jun 21 06:10:24 PM PDT 24
Peak memory 195676 kb
Host smart-0c1bb535-cb69-4274-94ac-7c588d789e06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147109731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.4147109731
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3873345286
Short name T349
Test name
Test status
Simulation time 1241496695 ps
CPU time 1.15 seconds
Started Jun 21 06:10:20 PM PDT 24
Finished Jun 21 06:10:22 PM PDT 24
Peak memory 195804 kb
Host smart-e9882995-f3b9-4867-b11b-94d38cb2be25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873345286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3873345286
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3648106216
Short name T290
Test name
Test status
Simulation time 145563479 ps
CPU time 1.64 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:23 PM PDT 24
Peak memory 196948 kb
Host smart-0d13538c-792e-4abf-9066-9c364b96aebe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648106216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3648106216
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.453451447
Short name T614
Test name
Test status
Simulation time 155287964 ps
CPU time 1.4 seconds
Started Jun 21 06:10:23 PM PDT 24
Finished Jun 21 06:10:26 PM PDT 24
Peak memory 195952 kb
Host smart-8fd0560e-5f75-42d7-a16a-7e79fb9ce39a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453451447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
453451447
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3471738303
Short name T400
Test name
Test status
Simulation time 139421728 ps
CPU time 0.84 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:22 PM PDT 24
Peak memory 196728 kb
Host smart-43f36f5c-6791-47e2-815f-7336f4326e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471738303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3471738303
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1053936045
Short name T543
Test name
Test status
Simulation time 40653276 ps
CPU time 1.01 seconds
Started Jun 21 06:10:24 PM PDT 24
Finished Jun 21 06:10:26 PM PDT 24
Peak memory 196040 kb
Host smart-49171c7f-d39d-4636-9c28-510c13879a3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053936045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1053936045
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.55613550
Short name T559
Test name
Test status
Simulation time 222909272 ps
CPU time 1.32 seconds
Started Jun 21 06:10:20 PM PDT 24
Finished Jun 21 06:10:22 PM PDT 24
Peak memory 197972 kb
Host smart-fe141570-c522-4d22-85f3-2ba3e58db921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55613550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand
om_long_reg_writes_reg_reads.55613550
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3081482499
Short name T595
Test name
Test status
Simulation time 24857282 ps
CPU time 0.81 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:22 PM PDT 24
Peak memory 195172 kb
Host smart-28b07a20-c4b1-4fa5-b592-922bd6baf79a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081482499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3081482499
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1601185366
Short name T197
Test name
Test status
Simulation time 78167789 ps
CPU time 1.44 seconds
Started Jun 21 06:10:22 PM PDT 24
Finished Jun 21 06:10:24 PM PDT 24
Peak memory 196284 kb
Host smart-0efa04ce-d16b-446a-a73c-cf85e521ab6e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601185366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1601185366
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.970416199
Short name T98
Test name
Test status
Simulation time 11593267895 ps
CPU time 51.09 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:11:13 PM PDT 24
Peak memory 198264 kb
Host smart-05f5db25-7eac-45c1-9668-e9b544454806
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970416199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.970416199
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1346588029
Short name T245
Test name
Test status
Simulation time 42252600 ps
CPU time 0.59 seconds
Started Jun 21 06:10:28 PM PDT 24
Finished Jun 21 06:10:29 PM PDT 24
Peak memory 194020 kb
Host smart-f1a79317-0af2-466d-a88f-90500d952d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346588029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1346588029
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.862776646
Short name T409
Test name
Test status
Simulation time 19654968 ps
CPU time 0.74 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:23 PM PDT 24
Peak memory 195152 kb
Host smart-0750c030-c9de-4fe0-835c-a15d5e1d25ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862776646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.862776646
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2241549191
Short name T420
Test name
Test status
Simulation time 2374232246 ps
CPU time 16.72 seconds
Started Jun 21 06:10:31 PM PDT 24
Finished Jun 21 06:10:48 PM PDT 24
Peak memory 197036 kb
Host smart-d9c0c2b9-0c78-4982-857c-7a7eb1c94230
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241549191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2241549191
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2239198200
Short name T656
Test name
Test status
Simulation time 299533853 ps
CPU time 0.96 seconds
Started Jun 21 06:10:29 PM PDT 24
Finished Jun 21 06:10:31 PM PDT 24
Peak memory 197960 kb
Host smart-43678e3c-11f2-4a64-aec4-215ea70d8412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239198200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2239198200
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2075865754
Short name T142
Test name
Test status
Simulation time 62462440 ps
CPU time 0.74 seconds
Started Jun 21 06:10:31 PM PDT 24
Finished Jun 21 06:10:33 PM PDT 24
Peak memory 195076 kb
Host smart-d40e50e9-597e-45bb-bc8e-a4a62ccb3651
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075865754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2075865754
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.841018159
Short name T310
Test name
Test status
Simulation time 70452659 ps
CPU time 1.55 seconds
Started Jun 21 06:10:28 PM PDT 24
Finished Jun 21 06:10:30 PM PDT 24
Peak memory 196716 kb
Host smart-0c93e7f2-e2e6-41b8-866c-2597c6ae9e5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841018159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 13.gpio_intr_with_filter_rand_intr_event.841018159
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3681371209
Short name T316
Test name
Test status
Simulation time 32087427 ps
CPU time 0.96 seconds
Started Jun 21 06:10:29 PM PDT 24
Finished Jun 21 06:10:31 PM PDT 24
Peak memory 195548 kb
Host smart-e9a954da-5352-4fe4-b179-634043e1bc11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681371209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3681371209
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.578700386
Short name T293
Test name
Test status
Simulation time 121511513 ps
CPU time 1.28 seconds
Started Jun 21 06:10:19 PM PDT 24
Finished Jun 21 06:10:21 PM PDT 24
Peak memory 197092 kb
Host smart-60e3d20c-54d4-430a-b440-f629c6a0de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578700386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.578700386
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1664566729
Short name T454
Test name
Test status
Simulation time 23916085 ps
CPU time 1.06 seconds
Started Jun 21 06:10:21 PM PDT 24
Finished Jun 21 06:10:24 PM PDT 24
Peak memory 195888 kb
Host smart-96f6ba28-d09d-4119-bd5b-387368188bf7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664566729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1664566729
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.405284012
Short name T447
Test name
Test status
Simulation time 124243954 ps
CPU time 5.59 seconds
Started Jun 21 06:10:29 PM PDT 24
Finished Jun 21 06:10:35 PM PDT 24
Peak memory 198024 kb
Host smart-20fb8ff8-c4a0-444a-8237-142875b73e27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405284012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ran
dom_long_reg_writes_reg_reads.405284012
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2867246133
Short name T260
Test name
Test status
Simulation time 36299504 ps
CPU time 0.86 seconds
Started Jun 21 06:10:22 PM PDT 24
Finished Jun 21 06:10:24 PM PDT 24
Peak memory 195816 kb
Host smart-6c37848a-eaee-4a55-933f-91f8c94f8936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867246133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2867246133
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.636201164
Short name T602
Test name
Test status
Simulation time 556735238 ps
CPU time 0.78 seconds
Started Jun 21 06:10:22 PM PDT 24
Finished Jun 21 06:10:24 PM PDT 24
Peak memory 195188 kb
Host smart-75ba3dfa-a03b-43ae-bc9a-24a83c91990d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636201164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.636201164
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1312124382
Short name T572
Test name
Test status
Simulation time 48026828504 ps
CPU time 33.33 seconds
Started Jun 21 06:10:30 PM PDT 24
Finished Jun 21 06:11:04 PM PDT 24
Peak memory 198140 kb
Host smart-38010478-7737-4de9-b692-e21d658f7ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312124382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1312124382
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1185713725
Short name T319
Test name
Test status
Simulation time 52516572 ps
CPU time 0.56 seconds
Started Jun 21 06:10:29 PM PDT 24
Finished Jun 21 06:10:31 PM PDT 24
Peak memory 194524 kb
Host smart-3fccd9ce-c8af-4da4-9b9f-7b658498165a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185713725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1185713725
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.292423376
Short name T373
Test name
Test status
Simulation time 89627713 ps
CPU time 0.84 seconds
Started Jun 21 06:10:30 PM PDT 24
Finished Jun 21 06:10:32 PM PDT 24
Peak memory 195488 kb
Host smart-eecf448c-52d2-4e05-b1b6-cc26c3a96512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292423376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.292423376
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1993587179
Short name T30
Test name
Test status
Simulation time 979516736 ps
CPU time 18.03 seconds
Started Jun 21 06:10:28 PM PDT 24
Finished Jun 21 06:10:47 PM PDT 24
Peak memory 197128 kb
Host smart-c036cd9c-9797-466b-90f3-e8265a3fd121
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993587179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1993587179
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.748498654
Short name T22
Test name
Test status
Simulation time 31254426 ps
CPU time 0.68 seconds
Started Jun 21 06:10:31 PM PDT 24
Finished Jun 21 06:10:33 PM PDT 24
Peak memory 194512 kb
Host smart-b0bd17ff-78e3-4e62-9ef2-768be48428c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748498654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.748498654
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.2898441700
Short name T618
Test name
Test status
Simulation time 86832364 ps
CPU time 1.19 seconds
Started Jun 21 06:10:32 PM PDT 24
Finished Jun 21 06:10:34 PM PDT 24
Peak memory 196208 kb
Host smart-1794ad8d-2bc0-45ed-8d7c-48fde8355fd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898441700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.2898441700
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.86669891
Short name T522
Test name
Test status
Simulation time 191258710 ps
CPU time 2.36 seconds
Started Jun 21 06:10:33 PM PDT 24
Finished Jun 21 06:10:36 PM PDT 24
Peak memory 198184 kb
Host smart-a3a8a75b-3af8-491a-a050-a7e55f5f8a6a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86669891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 14.gpio_intr_with_filter_rand_intr_event.86669891
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2043197512
Short name T598
Test name
Test status
Simulation time 27749511 ps
CPU time 1.06 seconds
Started Jun 21 06:10:29 PM PDT 24
Finished Jun 21 06:10:30 PM PDT 24
Peak memory 195616 kb
Host smart-2b1ad378-0d79-4fb6-818a-da2dccaf608a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043197512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2043197512
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1629078451
Short name T483
Test name
Test status
Simulation time 122452185 ps
CPU time 0.79 seconds
Started Jun 21 06:10:31 PM PDT 24
Finished Jun 21 06:10:33 PM PDT 24
Peak memory 196140 kb
Host smart-bf2f2406-c18c-4f2f-b437-2955bf936492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629078451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1629078451
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4178652105
Short name T174
Test name
Test status
Simulation time 59065707 ps
CPU time 0.81 seconds
Started Jun 21 06:10:30 PM PDT 24
Finished Jun 21 06:10:32 PM PDT 24
Peak memory 196076 kb
Host smart-8447f605-3adb-489b-be5a-6d88ad915168
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178652105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4178652105
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2718552068
Short name T7
Test name
Test status
Simulation time 322276761 ps
CPU time 4.56 seconds
Started Jun 21 06:10:29 PM PDT 24
Finished Jun 21 06:10:35 PM PDT 24
Peak memory 198028 kb
Host smart-21ba5f4e-9eab-4d88-8345-e0c512397027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718552068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2718552068
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1314976072
Short name T128
Test name
Test status
Simulation time 32947418 ps
CPU time 0.98 seconds
Started Jun 21 06:10:30 PM PDT 24
Finished Jun 21 06:10:32 PM PDT 24
Peak memory 195612 kb
Host smart-3fecfaad-94cb-427b-8fbc-be5518f90c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314976072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1314976072
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.653280450
Short name T190
Test name
Test status
Simulation time 36011937 ps
CPU time 1.06 seconds
Started Jun 21 06:10:27 PM PDT 24
Finished Jun 21 06:10:29 PM PDT 24
Peak memory 195556 kb
Host smart-a4dfc2d8-877e-4d18-9441-be95101d79c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653280450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.653280450
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3275548507
Short name T647
Test name
Test status
Simulation time 37080040915 ps
CPU time 107.34 seconds
Started Jun 21 06:10:32 PM PDT 24
Finished Jun 21 06:12:20 PM PDT 24
Peak memory 198160 kb
Host smart-4ea402fb-01f1-4dc2-b6ea-c08fa5904ab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275548507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3275548507
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1727248448
Short name T69
Test name
Test status
Simulation time 61932876989 ps
CPU time 525.44 seconds
Started Jun 21 06:10:29 PM PDT 24
Finished Jun 21 06:19:15 PM PDT 24
Peak memory 198212 kb
Host smart-83f27c66-ba6f-4a4a-9af7-a8565b6a2153
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1727248448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1727248448
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2372044019
Short name T253
Test name
Test status
Simulation time 11559613 ps
CPU time 0.55 seconds
Started Jun 21 06:10:42 PM PDT 24
Finished Jun 21 06:10:44 PM PDT 24
Peak memory 193792 kb
Host smart-978a8d74-1901-442f-adc7-1cc4b06a6e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372044019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2372044019
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2148723467
Short name T619
Test name
Test status
Simulation time 243056843 ps
CPU time 0.74 seconds
Started Jun 21 06:10:37 PM PDT 24
Finished Jun 21 06:10:38 PM PDT 24
Peak memory 194204 kb
Host smart-f02bcfec-6bb7-4206-a33d-adb17e0f27ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148723467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2148723467
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3092361887
Short name T161
Test name
Test status
Simulation time 359041834 ps
CPU time 12.15 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:51 PM PDT 24
Peak memory 197144 kb
Host smart-6f6d2399-34a3-478a-8302-8a6196b768c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092361887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3092361887
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3272339186
Short name T20
Test name
Test status
Simulation time 381862120 ps
CPU time 1.09 seconds
Started Jun 21 06:10:36 PM PDT 24
Finished Jun 21 06:10:38 PM PDT 24
Peak memory 196432 kb
Host smart-39131a38-e206-4874-a892-42eed97b08c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272339186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3272339186
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.810335814
Short name T160
Test name
Test status
Simulation time 54336976 ps
CPU time 0.9 seconds
Started Jun 21 06:10:36 PM PDT 24
Finished Jun 21 06:10:37 PM PDT 24
Peak memory 196660 kb
Host smart-44f2c26a-9adb-494f-b115-bd39ed1171a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810335814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.810335814
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2667428075
Short name T549
Test name
Test status
Simulation time 239897298 ps
CPU time 2.75 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:10:44 PM PDT 24
Peak memory 198096 kb
Host smart-9845759f-b17a-4d0d-a8be-6ff030635bcb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667428075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2667428075
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.3357741739
Short name T356
Test name
Test status
Simulation time 35966552 ps
CPU time 1.25 seconds
Started Jun 21 06:10:37 PM PDT 24
Finished Jun 21 06:10:39 PM PDT 24
Peak memory 197388 kb
Host smart-d4de25ef-ff58-4dd6-94de-00b14536623e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357741739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.3357741739
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2194424707
Short name T516
Test name
Test status
Simulation time 126957917 ps
CPU time 0.93 seconds
Started Jun 21 06:10:35 PM PDT 24
Finished Jun 21 06:10:37 PM PDT 24
Peak memory 195940 kb
Host smart-703fb53b-b6fe-429a-ace2-f78dc1436c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194424707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2194424707
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1417598230
Short name T623
Test name
Test status
Simulation time 14968183 ps
CPU time 0.71 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:10:41 PM PDT 24
Peak memory 194144 kb
Host smart-fd464bb6-231a-485e-b11e-ca6947268264
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417598230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1417598230
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.2085150192
Short name T527
Test name
Test status
Simulation time 341634134 ps
CPU time 3.59 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:10:44 PM PDT 24
Peak memory 198028 kb
Host smart-422a5ccb-062d-4fc6-8b60-85a1bea9e8ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085150192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.2085150192
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.454103017
Short name T524
Test name
Test status
Simulation time 34112854 ps
CPU time 0.88 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:40 PM PDT 24
Peak memory 195956 kb
Host smart-e9e24fc5-b567-492f-b4de-7365fbdb1fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454103017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.454103017
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3604976028
Short name T523
Test name
Test status
Simulation time 198330571 ps
CPU time 1.2 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:41 PM PDT 24
Peak memory 196292 kb
Host smart-a3996af3-50e6-4fcc-92b7-bbb18383cdce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604976028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3604976028
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3062835025
Short name T466
Test name
Test status
Simulation time 20575451530 ps
CPU time 65.42 seconds
Started Jun 21 06:10:42 PM PDT 24
Finished Jun 21 06:11:49 PM PDT 24
Peak memory 198144 kb
Host smart-8aa29da2-6f77-467e-b6f6-1889590e3f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062835025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3062835025
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3231431709
Short name T162
Test name
Test status
Simulation time 19680202 ps
CPU time 0.55 seconds
Started Jun 21 06:10:37 PM PDT 24
Finished Jun 21 06:10:38 PM PDT 24
Peak memory 193824 kb
Host smart-fd4197a9-d938-485f-9e05-c463eb9c7c76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231431709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3231431709
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1980628747
Short name T535
Test name
Test status
Simulation time 139641879 ps
CPU time 0.82 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:41 PM PDT 24
Peak memory 195412 kb
Host smart-64ec60ab-3430-45a1-a173-6f8f7e9f5e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980628747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1980628747
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1626939600
Short name T467
Test name
Test status
Simulation time 783687545 ps
CPU time 22.09 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:11:03 PM PDT 24
Peak memory 195476 kb
Host smart-2d7e7b8c-5ff2-4b62-a7bd-617a95c84d95
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626939600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1626939600
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3577042339
Short name T677
Test name
Test status
Simulation time 326886815 ps
CPU time 1.37 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:41 PM PDT 24
Peak memory 197048 kb
Host smart-0a456ed5-7204-41e1-9292-0a378a261b4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577042339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3577042339
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1108906511
Short name T698
Test name
Test status
Simulation time 35703430 ps
CPU time 1.5 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:10:42 PM PDT 24
Peak memory 196568 kb
Host smart-c6469483-35ab-4de3-a586-f9a195b512f2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108906511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1108906511
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1410965923
Short name T427
Test name
Test status
Simulation time 451895353 ps
CPU time 3.2 seconds
Started Jun 21 06:10:42 PM PDT 24
Finished Jun 21 06:10:46 PM PDT 24
Peak memory 198056 kb
Host smart-ac3a3745-8514-424e-af11-2ebdb5cf934f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410965923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1410965923
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2567838815
Short name T153
Test name
Test status
Simulation time 35475490 ps
CPU time 1.25 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:10:42 PM PDT 24
Peak memory 195892 kb
Host smart-20da5b7e-9a86-43ae-ae1d-a3d815832d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567838815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2567838815
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.221481595
Short name T140
Test name
Test status
Simulation time 54103438 ps
CPU time 0.77 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:40 PM PDT 24
Peak memory 195388 kb
Host smart-4396367f-af34-4664-aa08-96d0f5516d50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221481595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.221481595
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4050644578
Short name T674
Test name
Test status
Simulation time 1678753474 ps
CPU time 5.49 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:45 PM PDT 24
Peak memory 197992 kb
Host smart-c5ac841c-5b88-45c9-b0f1-02090c416d34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050644578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4050644578
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1308417006
Short name T138
Test name
Test status
Simulation time 49338293 ps
CPU time 0.97 seconds
Started Jun 21 06:10:37 PM PDT 24
Finished Jun 21 06:10:40 PM PDT 24
Peak memory 195592 kb
Host smart-e7d12852-df8b-4ea6-8b8b-0e2b6bc40e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308417006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1308417006
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.703820826
Short name T490
Test name
Test status
Simulation time 46531344 ps
CPU time 1.27 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:40 PM PDT 24
Peak memory 196784 kb
Host smart-b33de36a-f327-491e-b666-269c8db075d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703820826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.703820826
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.97834919
Short name T462
Test name
Test status
Simulation time 11240625631 ps
CPU time 162.04 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:13:23 PM PDT 24
Peak memory 198176 kb
Host smart-2182d4fe-69d7-4772-8f5a-2e5927c46785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97834919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gp
io_stress_all.97834919
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.108171782
Short name T107
Test name
Test status
Simulation time 56671229529 ps
CPU time 488.37 seconds
Started Jun 21 06:10:37 PM PDT 24
Finished Jun 21 06:18:46 PM PDT 24
Peak memory 198336 kb
Host smart-4ddbafd3-ad53-4391-b29f-cd80f20e2c0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=108171782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.108171782
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2534529326
Short name T45
Test name
Test status
Simulation time 11739109 ps
CPU time 0.58 seconds
Started Jun 21 06:10:45 PM PDT 24
Finished Jun 21 06:10:47 PM PDT 24
Peak memory 193808 kb
Host smart-c2fa0fee-e139-4e9b-bf70-47df5823de66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534529326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2534529326
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.4122538706
Short name T382
Test name
Test status
Simulation time 191815820 ps
CPU time 0.87 seconds
Started Jun 21 06:10:44 PM PDT 24
Finished Jun 21 06:10:46 PM PDT 24
Peak memory 197128 kb
Host smart-57b1bf69-ce27-4bcf-8815-7ac44b206e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122538706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.4122538706
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.278362506
Short name T330
Test name
Test status
Simulation time 1757723832 ps
CPU time 6.63 seconds
Started Jun 21 06:10:45 PM PDT 24
Finished Jun 21 06:10:52 PM PDT 24
Peak memory 197032 kb
Host smart-d09e764d-f39b-4919-800b-452dbc31bdb1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278362506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.278362506
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2967010231
Short name T351
Test name
Test status
Simulation time 112753662 ps
CPU time 0.95 seconds
Started Jun 21 06:10:45 PM PDT 24
Finished Jun 21 06:10:47 PM PDT 24
Peak memory 197244 kb
Host smart-ecce92b7-1044-4be7-9f21-5fb52b9bd900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967010231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2967010231
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3169881220
Short name T149
Test name
Test status
Simulation time 105871583 ps
CPU time 1.06 seconds
Started Jun 21 06:10:46 PM PDT 24
Finished Jun 21 06:10:49 PM PDT 24
Peak memory 195948 kb
Host smart-ba5be32d-744b-4045-8708-f16dbf0c7d4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169881220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3169881220
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3524801359
Short name T529
Test name
Test status
Simulation time 70369017 ps
CPU time 2.98 seconds
Started Jun 21 06:10:45 PM PDT 24
Finished Jun 21 06:10:48 PM PDT 24
Peak memory 198088 kb
Host smart-196d45a9-5584-4cdb-a425-23140a06c3ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524801359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3524801359
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2269121999
Short name T295
Test name
Test status
Simulation time 124043338 ps
CPU time 2.77 seconds
Started Jun 21 06:10:44 PM PDT 24
Finished Jun 21 06:10:48 PM PDT 24
Peak memory 197248 kb
Host smart-ae1aac56-9a47-4fa3-b1f1-d10f452986d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269121999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2269121999
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1450218965
Short name T624
Test name
Test status
Simulation time 70028441 ps
CPU time 0.69 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:40 PM PDT 24
Peak memory 194988 kb
Host smart-c32929fb-f4c5-47a8-b773-ad966b8468bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450218965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1450218965
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3754554924
Short name T31
Test name
Test status
Simulation time 44016189 ps
CPU time 0.68 seconds
Started Jun 21 06:10:36 PM PDT 24
Finished Jun 21 06:10:37 PM PDT 24
Peak memory 195292 kb
Host smart-52c76d29-b0ee-44a9-93c1-1178cb39ab6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754554924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3754554924
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.10210216
Short name T665
Test name
Test status
Simulation time 489280796 ps
CPU time 3.38 seconds
Started Jun 21 06:10:44 PM PDT 24
Finished Jun 21 06:10:48 PM PDT 24
Peak memory 197992 kb
Host smart-a0a8c13e-94b5-444b-b546-67a4b9c5f627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10210216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand
om_long_reg_writes_reg_reads.10210216
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3448473765
Short name T126
Test name
Test status
Simulation time 89821823 ps
CPU time 1.04 seconds
Started Jun 21 06:10:38 PM PDT 24
Finished Jun 21 06:10:40 PM PDT 24
Peak memory 196304 kb
Host smart-3429dbe1-18cd-4ff9-9b0b-facbed75bf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448473765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3448473765
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.12643177
Short name T394
Test name
Test status
Simulation time 39895355 ps
CPU time 1.22 seconds
Started Jun 21 06:10:39 PM PDT 24
Finished Jun 21 06:10:42 PM PDT 24
Peak memory 196548 kb
Host smart-7f99abb8-121a-49f0-b567-c8e298c56da8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12643177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.12643177
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.4092965104
Short name T498
Test name
Test status
Simulation time 1876832006 ps
CPU time 58.38 seconds
Started Jun 21 06:10:44 PM PDT 24
Finished Jun 21 06:11:44 PM PDT 24
Peak memory 198108 kb
Host smart-ade71a38-eab3-4aa7-8dd1-ddc7d9bec040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092965104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.4092965104
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1161475006
Short name T64
Test name
Test status
Simulation time 241351091102 ps
CPU time 1653.3 seconds
Started Jun 21 06:10:44 PM PDT 24
Finished Jun 21 06:38:18 PM PDT 24
Peak memory 206456 kb
Host smart-ec7bbe10-4900-4015-a78e-89e8c3f2a0d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1161475006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1161475006
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2248420815
Short name T247
Test name
Test status
Simulation time 54470783 ps
CPU time 0.57 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:10:54 PM PDT 24
Peak memory 193836 kb
Host smart-078ad7a4-e23f-4175-87f1-1ca1aedd7c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248420815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2248420815
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.3943316434
Short name T620
Test name
Test status
Simulation time 159513479 ps
CPU time 0.94 seconds
Started Jun 21 06:10:43 PM PDT 24
Finished Jun 21 06:10:45 PM PDT 24
Peak memory 196372 kb
Host smart-a90f93c5-767f-4223-b0f3-1ad17e4378fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943316434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.3943316434
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.275528713
Short name T209
Test name
Test status
Simulation time 2677714139 ps
CPU time 19.78 seconds
Started Jun 21 06:10:46 PM PDT 24
Finished Jun 21 06:11:07 PM PDT 24
Peak memory 196764 kb
Host smart-f8025490-c7a2-49e1-92ba-bd13e81dc79f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275528713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.275528713
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3452909009
Short name T182
Test name
Test status
Simulation time 254162998 ps
CPU time 1 seconds
Started Jun 21 06:10:46 PM PDT 24
Finished Jun 21 06:10:48 PM PDT 24
Peak memory 196584 kb
Host smart-7380fe34-af83-491b-b54c-8d8c09fa5eba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452909009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3452909009
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1767278633
Short name T611
Test name
Test status
Simulation time 277362235 ps
CPU time 0.83 seconds
Started Jun 21 06:10:45 PM PDT 24
Finished Jun 21 06:10:47 PM PDT 24
Peak memory 195588 kb
Host smart-010576ea-6918-4b26-a670-9aaf44923f30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767278633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1767278633
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.3090002470
Short name T628
Test name
Test status
Simulation time 67935748 ps
CPU time 2.88 seconds
Started Jun 21 06:10:48 PM PDT 24
Finished Jun 21 06:10:51 PM PDT 24
Peak memory 198172 kb
Host smart-04426c63-2cfe-48e5-869d-6ac8438dad1b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090002470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.3090002470
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1015446320
Short name T213
Test name
Test status
Simulation time 582841446 ps
CPU time 3.2 seconds
Started Jun 21 06:10:46 PM PDT 24
Finished Jun 21 06:10:50 PM PDT 24
Peak memory 197028 kb
Host smart-f6a09d81-39a6-4e1e-8326-72f9069d0988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015446320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1015446320
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.719150651
Short name T175
Test name
Test status
Simulation time 32523903 ps
CPU time 0.98 seconds
Started Jun 21 06:10:46 PM PDT 24
Finished Jun 21 06:10:48 PM PDT 24
Peak memory 196044 kb
Host smart-eb923dd3-ab9b-4fc2-85d5-91d725640da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719150651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.719150651
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.4068459599
Short name T103
Test name
Test status
Simulation time 20958644 ps
CPU time 0.7 seconds
Started Jun 21 06:10:45 PM PDT 24
Finished Jun 21 06:10:47 PM PDT 24
Peak memory 196056 kb
Host smart-bbff2614-e232-47c4-b753-21a5424ffda7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068459599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.4068459599
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.3002049955
Short name T28
Test name
Test status
Simulation time 1249926988 ps
CPU time 5 seconds
Started Jun 21 06:10:46 PM PDT 24
Finished Jun 21 06:10:52 PM PDT 24
Peak memory 197968 kb
Host smart-579148d5-8c77-4f23-9136-fc93f2d4c592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002049955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.3002049955
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2112477700
Short name T432
Test name
Test status
Simulation time 40469548 ps
CPU time 0.78 seconds
Started Jun 21 06:10:48 PM PDT 24
Finished Jun 21 06:10:49 PM PDT 24
Peak memory 195228 kb
Host smart-e3c72f88-9bb3-4507-839b-d395ffa78e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112477700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2112477700
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.569964585
Short name T633
Test name
Test status
Simulation time 402895139 ps
CPU time 1.04 seconds
Started Jun 21 06:10:44 PM PDT 24
Finished Jun 21 06:10:46 PM PDT 24
Peak memory 196464 kb
Host smart-22154cc8-4630-4615-914e-1fbe65f951f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569964585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.569964585
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1570987580
Short name T389
Test name
Test status
Simulation time 3477047459 ps
CPU time 93.35 seconds
Started Jun 21 06:10:53 PM PDT 24
Finished Jun 21 06:12:27 PM PDT 24
Peak memory 198200 kb
Host smart-e366909d-3f75-4186-b2f9-acfcea1fa897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570987580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1570987580
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.1441356105
Short name T34
Test name
Test status
Simulation time 52921082624 ps
CPU time 700.31 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:22:33 PM PDT 24
Peak memory 198204 kb
Host smart-47e3b2ea-1706-4640-8d14-e72d3c37db7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1441356105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.1441356105
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3561856764
Short name T208
Test name
Test status
Simulation time 52164745 ps
CPU time 0.57 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:10:53 PM PDT 24
Peak memory 193816 kb
Host smart-14a47765-fbd5-435f-9b95-97361eb6b0b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561856764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3561856764
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3531871960
Short name T228
Test name
Test status
Simulation time 33380107 ps
CPU time 0.92 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:10:54 PM PDT 24
Peak memory 196456 kb
Host smart-03cbfe65-e4af-48d4-a101-e3c0f078fd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531871960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3531871960
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.1776062130
Short name T669
Test name
Test status
Simulation time 429242747 ps
CPU time 24.08 seconds
Started Jun 21 06:10:54 PM PDT 24
Finished Jun 21 06:11:19 PM PDT 24
Peak memory 197004 kb
Host smart-cd238441-c408-4100-b6a1-18ab7d6cc9a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776062130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.1776062130
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3999520322
Short name T376
Test name
Test status
Simulation time 275814534 ps
CPU time 1.06 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:10:54 PM PDT 24
Peak memory 196420 kb
Host smart-e5fd8f96-191b-4c5b-9e5e-93de3474e20d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999520322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3999520322
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2057770609
Short name T648
Test name
Test status
Simulation time 90625374 ps
CPU time 0.76 seconds
Started Jun 21 06:10:56 PM PDT 24
Finished Jun 21 06:10:58 PM PDT 24
Peak memory 195084 kb
Host smart-bc769e70-917f-4cf5-b20f-85771a881e25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057770609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2057770609
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.611960796
Short name T377
Test name
Test status
Simulation time 225902615 ps
CPU time 2.68 seconds
Started Jun 21 06:10:54 PM PDT 24
Finished Jun 21 06:10:57 PM PDT 24
Peak memory 198128 kb
Host smart-bf6ef0c6-4458-4de3-87bf-5ab81d9b82ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611960796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.611960796
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1218435230
Short name T476
Test name
Test status
Simulation time 63142576 ps
CPU time 1.45 seconds
Started Jun 21 06:10:57 PM PDT 24
Finished Jun 21 06:10:59 PM PDT 24
Peak memory 195812 kb
Host smart-ebf9c704-5541-4e7c-9de2-eb04b9f42af7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218435230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1218435230
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4029924148
Short name T233
Test name
Test status
Simulation time 77219035 ps
CPU time 1.01 seconds
Started Jun 21 06:10:53 PM PDT 24
Finished Jun 21 06:10:55 PM PDT 24
Peak memory 195880 kb
Host smart-62327030-a0b3-4770-8d8e-6295da852e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029924148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4029924148
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3468133668
Short name T198
Test name
Test status
Simulation time 146134785 ps
CPU time 0.99 seconds
Started Jun 21 06:10:53 PM PDT 24
Finished Jun 21 06:10:55 PM PDT 24
Peak memory 196564 kb
Host smart-65e1688a-afda-46d6-b802-7128c7c566e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468133668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3468133668
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.491515571
Short name T460
Test name
Test status
Simulation time 3792070258 ps
CPU time 4.14 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:10:56 PM PDT 24
Peak memory 197988 kb
Host smart-fd09fbdb-79db-4cf5-8cdc-9ad100194017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491515571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.491515571
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1549605788
Short name T129
Test name
Test status
Simulation time 58574928 ps
CPU time 1.25 seconds
Started Jun 21 06:10:53 PM PDT 24
Finished Jun 21 06:10:56 PM PDT 24
Peak memory 195824 kb
Host smart-d841375a-50e5-41be-870a-75592d41f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549605788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1549605788
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3740797857
Short name T212
Test name
Test status
Simulation time 198592871 ps
CPU time 1.33 seconds
Started Jun 21 06:10:53 PM PDT 24
Finished Jun 21 06:10:55 PM PDT 24
Peak memory 196860 kb
Host smart-d6ce66ce-c991-4871-b235-a4c1d62c7dc7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740797857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3740797857
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.1383328029
Short name T696
Test name
Test status
Simulation time 5868136390 ps
CPU time 90.91 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:12:24 PM PDT 24
Peak memory 198112 kb
Host smart-3fff8372-8413-4655-a7e8-9bc3ff643346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383328029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.1383328029
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.599940843
Short name T353
Test name
Test status
Simulation time 13054997 ps
CPU time 0.55 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:09:26 PM PDT 24
Peak memory 192700 kb
Host smart-d433bf4a-c721-4b4b-aaef-e69bd2afb34b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599940843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.599940843
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3039471265
Short name T266
Test name
Test status
Simulation time 21586041 ps
CPU time 0.84 seconds
Started Jun 21 06:09:28 PM PDT 24
Finished Jun 21 06:09:29 PM PDT 24
Peak memory 196068 kb
Host smart-235e0ed0-456b-4c65-9a9d-8061fd882b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039471265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3039471265
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.462481896
Short name T186
Test name
Test status
Simulation time 2523162106 ps
CPU time 19.68 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:46 PM PDT 24
Peak memory 198088 kb
Host smart-ba0a5360-a72b-4208-b6dc-d8e2ce4e01c5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462481896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stress
.462481896
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2011881668
Short name T690
Test name
Test status
Simulation time 90582801 ps
CPU time 0.72 seconds
Started Jun 21 06:09:27 PM PDT 24
Finished Jun 21 06:09:29 PM PDT 24
Peak memory 195460 kb
Host smart-ab8e92ad-cc78-41a7-91a7-5db879e52182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011881668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2011881668
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1449167341
Short name T558
Test name
Test status
Simulation time 37658736 ps
CPU time 0.93 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:28 PM PDT 24
Peak memory 196460 kb
Host smart-3e187025-bfcd-4e3d-b08b-a6b5e9ce3a38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449167341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1449167341
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.4213429367
Short name T487
Test name
Test status
Simulation time 245778283 ps
CPU time 2.57 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:30 PM PDT 24
Peak memory 196344 kb
Host smart-d1cfc918-daab-435c-b716-0eee792e93fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213429367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.4213429367
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2070426307
Short name T39
Test name
Test status
Simulation time 84242310 ps
CPU time 0.98 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:28 PM PDT 24
Peak memory 196188 kb
Host smart-d2186fd0-a054-4601-9627-eaee3d40b648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070426307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2070426307
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2327471621
Short name T557
Test name
Test status
Simulation time 118571265 ps
CPU time 1.36 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:09:27 PM PDT 24
Peak memory 198084 kb
Host smart-6e0a2298-f085-479d-a1ae-47439f5f3c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327471621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2327471621
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3203553802
Short name T346
Test name
Test status
Simulation time 70259837 ps
CPU time 1.37 seconds
Started Jun 21 06:09:28 PM PDT 24
Finished Jun 21 06:09:30 PM PDT 24
Peak memory 195836 kb
Host smart-5bc93589-c4c7-4420-8cef-005ec42d5b22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203553802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3203553802
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1691099229
Short name T369
Test name
Test status
Simulation time 124200198 ps
CPU time 5.25 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:09:32 PM PDT 24
Peak memory 197944 kb
Host smart-baf99ecd-fdf2-4077-8064-bc638f042a60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691099229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1691099229
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1348312374
Short name T52
Test name
Test status
Simulation time 502473505 ps
CPU time 0.95 seconds
Started Jun 21 06:09:24 PM PDT 24
Finished Jun 21 06:09:25 PM PDT 24
Peak memory 214776 kb
Host smart-c466818d-7a4a-418e-947e-7a7d65e186f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348312374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1348312374
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.218315369
Short name T230
Test name
Test status
Simulation time 94922238 ps
CPU time 1.52 seconds
Started Jun 21 06:09:25 PM PDT 24
Finished Jun 21 06:09:28 PM PDT 24
Peak memory 196988 kb
Host smart-6c1a500c-29a9-4449-9a34-b86d9e1f23a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218315369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.218315369
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3952946299
Short name T574
Test name
Test status
Simulation time 221667186 ps
CPU time 1.12 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:28 PM PDT 24
Peak memory 195920 kb
Host smart-babd2a30-0803-477c-b614-180f47175f61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952946299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3952946299
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.663750776
Short name T636
Test name
Test status
Simulation time 30723079436 ps
CPU time 224.02 seconds
Started Jun 21 06:09:27 PM PDT 24
Finished Jun 21 06:13:12 PM PDT 24
Peak memory 198160 kb
Host smart-ea7f28c9-d9e2-46ba-846c-dfd9bc4d60d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663750776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.663750776
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.751039709
Short name T508
Test name
Test status
Simulation time 22331409 ps
CPU time 0.59 seconds
Started Jun 21 06:11:01 PM PDT 24
Finished Jun 21 06:11:03 PM PDT 24
Peak memory 193832 kb
Host smart-6e4d6085-2ba0-4deb-bff3-10be381a3d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751039709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.751039709
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.575205664
Short name T435
Test name
Test status
Simulation time 42371090 ps
CPU time 0.62 seconds
Started Jun 21 06:10:53 PM PDT 24
Finished Jun 21 06:10:54 PM PDT 24
Peak memory 193992 kb
Host smart-a49ce8d2-a231-441a-ba8f-1b6180597e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575205664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.575205664
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.4095028575
Short name T580
Test name
Test status
Simulation time 137695733 ps
CPU time 6.72 seconds
Started Jun 21 06:11:06 PM PDT 24
Finished Jun 21 06:11:13 PM PDT 24
Peak memory 196920 kb
Host smart-d6415428-c864-418a-be33-bd0315fa9aee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095028575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.4095028575
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2690032283
Short name T19
Test name
Test status
Simulation time 39609739 ps
CPU time 0.79 seconds
Started Jun 21 06:11:02 PM PDT 24
Finished Jun 21 06:11:03 PM PDT 24
Peak memory 195916 kb
Host smart-d74c7cb8-1af0-426c-b8dd-73217d01d4a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690032283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2690032283
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4166433534
Short name T220
Test name
Test status
Simulation time 168421666 ps
CPU time 1.53 seconds
Started Jun 21 06:11:06 PM PDT 24
Finished Jun 21 06:11:09 PM PDT 24
Peak memory 197100 kb
Host smart-1de3c639-7ae2-4f4a-a961-4e7cbdcbf46d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166433534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4166433534
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1550361527
Short name T101
Test name
Test status
Simulation time 127591146 ps
CPU time 1.02 seconds
Started Jun 21 06:11:00 PM PDT 24
Finished Jun 21 06:11:02 PM PDT 24
Peak memory 196240 kb
Host smart-3792234d-e249-41b5-b622-19363b882a9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550361527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1550361527
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1573926616
Short name T396
Test name
Test status
Simulation time 68073788 ps
CPU time 1.81 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:11:06 PM PDT 24
Peak memory 196772 kb
Host smart-00b75e26-977b-4efa-b7b4-1c40ad743fce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573926616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1573926616
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.509778589
Short name T236
Test name
Test status
Simulation time 34424709 ps
CPU time 0.92 seconds
Started Jun 21 06:10:56 PM PDT 24
Finished Jun 21 06:10:58 PM PDT 24
Peak memory 196068 kb
Host smart-d54db9d3-eaea-4b21-8413-5f19077c104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509778589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.509778589
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.342238784
Short name T482
Test name
Test status
Simulation time 22941507 ps
CPU time 0.72 seconds
Started Jun 21 06:10:55 PM PDT 24
Finished Jun 21 06:10:57 PM PDT 24
Peak memory 194256 kb
Host smart-abf9d0d7-d9d5-4ff0-bf8d-7d0724d08dc6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342238784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.342238784
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1187765753
Short name T426
Test name
Test status
Simulation time 632621610 ps
CPU time 6.48 seconds
Started Jun 21 06:11:02 PM PDT 24
Finished Jun 21 06:11:10 PM PDT 24
Peak memory 198048 kb
Host smart-02dd63d5-a1d8-4ae5-afa2-b6057e9bf7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187765753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1187765753
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.2534628044
Short name T664
Test name
Test status
Simulation time 75854044 ps
CPU time 1.15 seconds
Started Jun 21 06:10:52 PM PDT 24
Finished Jun 21 06:10:54 PM PDT 24
Peak memory 195840 kb
Host smart-61ee1f0c-0522-4a1f-9d92-058950e45c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534628044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.2534628044
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.845888636
Short name T326
Test name
Test status
Simulation time 37104938 ps
CPU time 0.9 seconds
Started Jun 21 06:10:54 PM PDT 24
Finished Jun 21 06:10:56 PM PDT 24
Peak memory 196976 kb
Host smart-d043db7a-2956-45c5-90bf-37f9e6094673
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845888636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.845888636
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3782278600
Short name T342
Test name
Test status
Simulation time 9802354883 ps
CPU time 141.97 seconds
Started Jun 21 06:11:01 PM PDT 24
Finished Jun 21 06:13:24 PM PDT 24
Peak memory 198180 kb
Host smart-3c218481-b3c6-4e6b-a3b3-c93288204bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782278600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3782278600
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1558727848
Short name T368
Test name
Test status
Simulation time 39121148 ps
CPU time 0.61 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:11:05 PM PDT 24
Peak memory 194500 kb
Host smart-ab16676f-cbf3-40e6-b14e-947706a1d952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558727848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1558727848
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3788889506
Short name T301
Test name
Test status
Simulation time 24219371 ps
CPU time 0.86 seconds
Started Jun 21 06:11:01 PM PDT 24
Finished Jun 21 06:11:02 PM PDT 24
Peak memory 195176 kb
Host smart-9717ddad-4843-4f2a-8fff-d1056c5c074a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788889506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3788889506
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.1418591832
Short name T222
Test name
Test status
Simulation time 498864396 ps
CPU time 24.78 seconds
Started Jun 21 06:11:02 PM PDT 24
Finished Jun 21 06:11:28 PM PDT 24
Peak memory 196992 kb
Host smart-3bf6976e-05f3-44a7-941e-65b4d139c446
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418591832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.1418591832
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.106134487
Short name T180
Test name
Test status
Simulation time 46386197 ps
CPU time 0.68 seconds
Started Jun 21 06:11:02 PM PDT 24
Finished Jun 21 06:11:04 PM PDT 24
Peak memory 194436 kb
Host smart-c3105846-af13-4f2e-b64d-78296b0c0d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106134487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.106134487
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2999183147
Short name T626
Test name
Test status
Simulation time 107756469 ps
CPU time 1.42 seconds
Started Jun 21 06:11:04 PM PDT 24
Finished Jun 21 06:11:06 PM PDT 24
Peak memory 195812 kb
Host smart-c0ed3468-0072-4b16-84c6-35bb9c861732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999183147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2999183147
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.698347668
Short name T238
Test name
Test status
Simulation time 47887159 ps
CPU time 2.19 seconds
Started Jun 21 06:11:06 PM PDT 24
Finished Jun 21 06:11:09 PM PDT 24
Peak memory 198080 kb
Host smart-29e1cad9-2b63-44e8-988b-e5d2e2304074
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698347668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.698347668
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.987519817
Short name T379
Test name
Test status
Simulation time 44960091 ps
CPU time 1.47 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:11:06 PM PDT 24
Peak memory 196172 kb
Host smart-5870d6bc-5785-4e8c-8689-509a3dad334e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987519817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger.
987519817
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.4080598111
Short name T271
Test name
Test status
Simulation time 37215991 ps
CPU time 1.49 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:11:06 PM PDT 24
Peak memory 197012 kb
Host smart-83f57523-8849-4109-a8c3-ee41a0e95247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080598111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.4080598111
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.42700643
Short name T673
Test name
Test status
Simulation time 88475070 ps
CPU time 1.04 seconds
Started Jun 21 06:11:02 PM PDT 24
Finished Jun 21 06:11:05 PM PDT 24
Peak memory 195960 kb
Host smart-b7e41b6a-c08e-41c6-a5d6-bf8f37834f3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42700643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup_
pulldown.42700643
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2538172322
Short name T223
Test name
Test status
Simulation time 250273225 ps
CPU time 4.92 seconds
Started Jun 21 06:11:04 PM PDT 24
Finished Jun 21 06:11:10 PM PDT 24
Peak memory 197920 kb
Host smart-d65a78f0-7ec4-4eb1-9333-3b43406ad986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538172322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2538172322
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3084620686
Short name T609
Test name
Test status
Simulation time 92736098 ps
CPU time 1.06 seconds
Started Jun 21 06:11:00 PM PDT 24
Finished Jun 21 06:11:01 PM PDT 24
Peak memory 195604 kb
Host smart-c8665a86-7aca-4935-ba95-74de7f31e48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084620686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3084620686
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2302956443
Short name T645
Test name
Test status
Simulation time 69341662 ps
CPU time 0.85 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:11:05 PM PDT 24
Peak memory 195936 kb
Host smart-522b39c1-f592-4a03-a274-c2f7848234cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302956443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2302956443
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3011846892
Short name T504
Test name
Test status
Simulation time 11433270185 ps
CPU time 112.04 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 198088 kb
Host smart-286812e0-edf5-4681-8b0f-3482cc0cf110
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011846892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3011846892
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.2935671390
Short name T641
Test name
Test status
Simulation time 427963526974 ps
CPU time 1825.92 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:41:30 PM PDT 24
Peak memory 206408 kb
Host smart-23ad12a8-d3a1-4466-b812-2814312ba1ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2935671390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.2935671390
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2383655222
Short name T340
Test name
Test status
Simulation time 14201804 ps
CPU time 0.64 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:11:14 PM PDT 24
Peak memory 194024 kb
Host smart-17acaea4-0cda-46ce-9485-33f68d33552e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383655222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2383655222
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1049402846
Short name T105
Test name
Test status
Simulation time 456117123 ps
CPU time 0.86 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:11:14 PM PDT 24
Peak memory 196204 kb
Host smart-62c1cc19-b13e-4a56-a9fd-3fe61930275b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049402846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1049402846
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1474086234
Short name T652
Test name
Test status
Simulation time 571796490 ps
CPU time 9.99 seconds
Started Jun 21 06:11:11 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 197212 kb
Host smart-439ba18d-84dd-4d6f-882e-f2695d440155
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474086234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1474086234
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3400981121
Short name T5
Test name
Test status
Simulation time 411336330 ps
CPU time 1.17 seconds
Started Jun 21 06:11:09 PM PDT 24
Finished Jun 21 06:11:13 PM PDT 24
Peak memory 198044 kb
Host smart-c2744990-1f06-4320-9083-5349cf59381f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400981121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3400981121
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3952026927
Short name T363
Test name
Test status
Simulation time 31261103 ps
CPU time 0.79 seconds
Started Jun 21 06:11:14 PM PDT 24
Finished Jun 21 06:11:17 PM PDT 24
Peak memory 195384 kb
Host smart-ee3c616e-cc33-43fd-8565-4312877cfafe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952026927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3952026927
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3611811060
Short name T264
Test name
Test status
Simulation time 65340313 ps
CPU time 2.51 seconds
Started Jun 21 06:11:12 PM PDT 24
Finished Jun 21 06:11:18 PM PDT 24
Peak memory 198084 kb
Host smart-df705b21-b61b-4c1d-ac2f-e638f0878cea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611811060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3611811060
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2682879933
Short name T304
Test name
Test status
Simulation time 428347119 ps
CPU time 3.82 seconds
Started Jun 21 06:11:09 PM PDT 24
Finished Jun 21 06:11:16 PM PDT 24
Peak memory 195820 kb
Host smart-687b827f-6d97-4d28-b8b1-f2b2493787f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682879933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2682879933
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.4115168056
Short name T566
Test name
Test status
Simulation time 128708311 ps
CPU time 1.34 seconds
Started Jun 21 06:11:03 PM PDT 24
Finished Jun 21 06:11:06 PM PDT 24
Peak memory 198080 kb
Host smart-77d12476-8909-42bb-8f36-47acbf9bcd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115168056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.4115168056
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2462951931
Short name T168
Test name
Test status
Simulation time 264738498 ps
CPU time 1.29 seconds
Started Jun 21 06:11:00 PM PDT 24
Finished Jun 21 06:11:02 PM PDT 24
Peak memory 196124 kb
Host smart-45cd8d5e-f667-4d1b-bb3d-ce79c09e0861
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462951931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2462951931
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4135267335
Short name T445
Test name
Test status
Simulation time 400020462 ps
CPU time 4.83 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:11:18 PM PDT 24
Peak memory 198016 kb
Host smart-960a5cb0-eae1-4fcd-a7ff-fd430c268e6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135267335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4135267335
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3563849169
Short name T16
Test name
Test status
Simulation time 188483746 ps
CPU time 0.99 seconds
Started Jun 21 06:11:01 PM PDT 24
Finished Jun 21 06:11:02 PM PDT 24
Peak memory 195388 kb
Host smart-b762a97b-70cd-4d83-8990-1e29ab54ca9f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563849169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3563849169
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2684773191
Short name T165
Test name
Test status
Simulation time 2506724880 ps
CPU time 62.69 seconds
Started Jun 21 06:11:11 PM PDT 24
Finished Jun 21 06:12:17 PM PDT 24
Peak memory 198100 kb
Host smart-bfa091c9-6590-4002-becd-399a3fcdc1ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684773191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2684773191
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1224744800
Short name T35
Test name
Test status
Simulation time 509340758278 ps
CPU time 1562.46 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:37:16 PM PDT 24
Peak memory 198160 kb
Host smart-dac7c6f0-d8f3-4525-b6df-17cc672282d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1224744800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1224744800
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.883250391
Short name T538
Test name
Test status
Simulation time 32284738 ps
CPU time 0.6 seconds
Started Jun 21 06:11:09 PM PDT 24
Finished Jun 21 06:11:13 PM PDT 24
Peak memory 194536 kb
Host smart-5ab1d83a-4e05-407b-9b8e-796053bce482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883250391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.883250391
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1752117929
Short name T115
Test name
Test status
Simulation time 35229304 ps
CPU time 0.74 seconds
Started Jun 21 06:11:09 PM PDT 24
Finished Jun 21 06:11:13 PM PDT 24
Peak memory 195888 kb
Host smart-f3d88bbf-dad0-4dff-b8fa-4cba965713c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752117929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1752117929
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.844300004
Short name T152
Test name
Test status
Simulation time 2863210625 ps
CPU time 5.81 seconds
Started Jun 21 06:11:12 PM PDT 24
Finished Jun 21 06:11:21 PM PDT 24
Peak memory 197564 kb
Host smart-daf5a794-a9ff-4a99-b333-d759f0a8d897
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844300004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.844300004
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3811819551
Short name T442
Test name
Test status
Simulation time 27855337 ps
CPU time 0.73 seconds
Started Jun 21 06:11:13 PM PDT 24
Finished Jun 21 06:11:16 PM PDT 24
Peak memory 194636 kb
Host smart-d56b080e-406c-4e2b-bfe1-3a71adfcbcdd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811819551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3811819551
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.758841484
Short name T700
Test name
Test status
Simulation time 82121835 ps
CPU time 1.34 seconds
Started Jun 21 06:11:13 PM PDT 24
Finished Jun 21 06:11:17 PM PDT 24
Peak memory 195832 kb
Host smart-993147ad-4c2b-47a0-af40-be46b7f6006b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758841484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.758841484
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3447117830
Short name T393
Test name
Test status
Simulation time 177788079 ps
CPU time 2.46 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:11:16 PM PDT 24
Peak memory 197312 kb
Host smart-b6889bfd-8cb8-48e7-840e-c7d503278f8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447117830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3447117830
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.757573090
Short name T185
Test name
Test status
Simulation time 108723995 ps
CPU time 1.98 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:11:16 PM PDT 24
Peak memory 196752 kb
Host smart-4119d8b8-c1be-489c-854c-d8eb1d7b4113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757573090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
757573090
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3282207726
Short name T163
Test name
Test status
Simulation time 19999241 ps
CPU time 0.78 seconds
Started Jun 21 06:11:11 PM PDT 24
Finished Jun 21 06:11:15 PM PDT 24
Peak memory 195340 kb
Host smart-77e28640-c059-4670-b478-9e614a17d87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282207726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3282207726
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.4099022229
Short name T650
Test name
Test status
Simulation time 53236544 ps
CPU time 1.07 seconds
Started Jun 21 06:11:09 PM PDT 24
Finished Jun 21 06:11:13 PM PDT 24
Peak memory 196864 kb
Host smart-f1cec670-8889-41cb-9abc-5c2cff2cc5e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099022229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.4099022229
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.270324878
Short name T672
Test name
Test status
Simulation time 638350317 ps
CPU time 5.86 seconds
Started Jun 21 06:11:09 PM PDT 24
Finished Jun 21 06:11:17 PM PDT 24
Peak memory 197964 kb
Host smart-3df6ab94-93ad-482f-aa31-4c8f1161a95e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270324878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.270324878
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.394244425
Short name T148
Test name
Test status
Simulation time 169677506 ps
CPU time 1.17 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:11:14 PM PDT 24
Peak memory 195580 kb
Host smart-32966fa4-c464-44d3-b8ca-9001f66307bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394244425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.394244425
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.4148575914
Short name T169
Test name
Test status
Simulation time 73749694 ps
CPU time 1.14 seconds
Started Jun 21 06:11:10 PM PDT 24
Finished Jun 21 06:11:14 PM PDT 24
Peak memory 195556 kb
Host smart-f00f765a-5dda-4882-b92a-70a465b45a49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148575914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.4148575914
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.3477349355
Short name T704
Test name
Test status
Simulation time 11954398563 ps
CPU time 160.58 seconds
Started Jun 21 06:11:11 PM PDT 24
Finished Jun 21 06:13:55 PM PDT 24
Peak memory 198188 kb
Host smart-4b3747b6-2cbb-46a1-a1b9-bdd8323770f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477349355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.3477349355
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.283421829
Short name T265
Test name
Test status
Simulation time 35346280 ps
CPU time 0.63 seconds
Started Jun 21 06:11:22 PM PDT 24
Finished Jun 21 06:11:25 PM PDT 24
Peak memory 194528 kb
Host smart-59154dca-1d0e-4b9b-81e6-d53824bf707e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283421829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.283421829
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.385742574
Short name T272
Test name
Test status
Simulation time 33353182 ps
CPU time 0.78 seconds
Started Jun 21 06:11:18 PM PDT 24
Finished Jun 21 06:11:20 PM PDT 24
Peak memory 195268 kb
Host smart-9d47d354-b0c7-4bb0-9560-2c7819208601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385742574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.385742574
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2379635277
Short name T710
Test name
Test status
Simulation time 237210744 ps
CPU time 12.45 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:33 PM PDT 24
Peak memory 197004 kb
Host smart-eddf1626-8b7f-40ac-bc18-52616866b2b3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379635277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2379635277
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.925296476
Short name T441
Test name
Test status
Simulation time 43579056 ps
CPU time 0.65 seconds
Started Jun 21 06:11:20 PM PDT 24
Finished Jun 21 06:11:23 PM PDT 24
Peak memory 194400 kb
Host smart-d6d7b86a-5a63-41c6-9d09-b54204802782
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925296476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.925296476
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1283326810
Short name T27
Test name
Test status
Simulation time 89866332 ps
CPU time 1.33 seconds
Started Jun 21 06:11:20 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 197076 kb
Host smart-26e4f048-9389-4419-9b4c-290c6d8142b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283326810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1283326810
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3009859261
Short name T576
Test name
Test status
Simulation time 319654816 ps
CPU time 3.29 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 196344 kb
Host smart-e076ed7b-a137-49fc-a50a-687523886df6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009859261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3009859261
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2106195703
Short name T494
Test name
Test status
Simulation time 108291054 ps
CPU time 2.19 seconds
Started Jun 21 06:11:22 PM PDT 24
Finished Jun 21 06:11:26 PM PDT 24
Peak memory 196248 kb
Host smart-61d3a381-bc76-47d9-979d-50573bfdc45b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106195703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2106195703
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2104970499
Short name T287
Test name
Test status
Simulation time 297276871 ps
CPU time 0.93 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:22 PM PDT 24
Peak memory 196588 kb
Host smart-53b7a41e-a49c-4c04-954b-13d9ff4471a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104970499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2104970499
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.937011114
Short name T177
Test name
Test status
Simulation time 244140342 ps
CPU time 1.32 seconds
Started Jun 21 06:11:22 PM PDT 24
Finished Jun 21 06:11:26 PM PDT 24
Peak memory 196976 kb
Host smart-823443f5-84a9-459f-9524-ed274b01b084
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937011114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.937011114
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.33264725
Short name T555
Test name
Test status
Simulation time 186109229 ps
CPU time 2.15 seconds
Started Jun 21 06:11:20 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 197996 kb
Host smart-fedd7a8f-924f-4ae4-ae01-bba8053348f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33264725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand
om_long_reg_writes_reg_reads.33264725
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3175349560
Short name T156
Test name
Test status
Simulation time 169730184 ps
CPU time 0.82 seconds
Started Jun 21 06:11:11 PM PDT 24
Finished Jun 21 06:11:15 PM PDT 24
Peak memory 195324 kb
Host smart-08d79393-9119-4e3d-bb4a-77e601a456be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175349560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3175349560
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1161083998
Short name T486
Test name
Test status
Simulation time 108566983 ps
CPU time 1.17 seconds
Started Jun 21 06:11:21 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 195588 kb
Host smart-38451268-221f-455f-8dde-a19fb98ac4bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161083998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1161083998
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2485626464
Short name T478
Test name
Test status
Simulation time 4619170999 ps
CPU time 29.46 seconds
Started Jun 21 06:11:18 PM PDT 24
Finished Jun 21 06:11:49 PM PDT 24
Peak memory 198104 kb
Host smart-4bd6987e-b038-4213-b608-d7c4c463e0e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485626464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2485626464
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4057623632
Short name T410
Test name
Test status
Simulation time 41866538 ps
CPU time 0.57 seconds
Started Jun 21 06:11:18 PM PDT 24
Finished Jun 21 06:11:20 PM PDT 24
Peak memory 193828 kb
Host smart-2953a39b-e118-4f63-a263-8cf0a1260aac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057623632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4057623632
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3327976499
Short name T430
Test name
Test status
Simulation time 58742904 ps
CPU time 0.86 seconds
Started Jun 21 06:11:18 PM PDT 24
Finished Jun 21 06:11:21 PM PDT 24
Peak memory 195344 kb
Host smart-442811ec-b027-4f7f-8716-036c03475a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327976499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3327976499
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3903276593
Short name T563
Test name
Test status
Simulation time 1046914417 ps
CPU time 7.58 seconds
Started Jun 21 06:11:22 PM PDT 24
Finished Jun 21 06:11:31 PM PDT 24
Peak memory 197032 kb
Host smart-12cf7e07-8fea-4da3-8739-858cc6ef6fb0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903276593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3903276593
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.2793380608
Short name T448
Test name
Test status
Simulation time 323956250 ps
CPU time 0.99 seconds
Started Jun 21 06:11:23 PM PDT 24
Finished Jun 21 06:11:26 PM PDT 24
Peak memory 197072 kb
Host smart-2e2f08f1-6aa3-4c50-9f98-ee9fb81fadfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793380608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.2793380608
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3419669060
Short name T13
Test name
Test status
Simulation time 32372102 ps
CPU time 0.95 seconds
Started Jun 21 06:11:22 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 196756 kb
Host smart-0b0cbc35-33f1-43da-938e-a8098759133b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419669060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3419669060
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.318019381
Short name T154
Test name
Test status
Simulation time 255947431 ps
CPU time 2.46 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:23 PM PDT 24
Peak memory 198128 kb
Host smart-3febbcc4-67c2-4cbe-a35c-aef8bb8f1363
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318019381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.318019381
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.890194428
Short name T712
Test name
Test status
Simulation time 481802263 ps
CPU time 2.66 seconds
Started Jun 21 06:11:20 PM PDT 24
Finished Jun 21 06:11:25 PM PDT 24
Peak memory 195856 kb
Host smart-cb841f45-b4ae-4703-a265-1da95bae92a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890194428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
890194428
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2255088070
Short name T183
Test name
Test status
Simulation time 24434381 ps
CPU time 0.98 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:22 PM PDT 24
Peak memory 196724 kb
Host smart-259c41be-fc78-451d-85c1-91bcf7092c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255088070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2255088070
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1874959508
Short name T291
Test name
Test status
Simulation time 21518080 ps
CPU time 0.84 seconds
Started Jun 21 06:11:21 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 195452 kb
Host smart-11c42297-5070-47db-8897-1fa0440adeaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874959508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1874959508
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1536158526
Short name T671
Test name
Test status
Simulation time 100992646 ps
CPU time 4.91 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:25 PM PDT 24
Peak memory 197948 kb
Host smart-ad525a9a-0191-4317-9264-322261de7048
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536158526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1536158526
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.596288905
Short name T666
Test name
Test status
Simulation time 51488953 ps
CPU time 1.42 seconds
Started Jun 21 06:11:22 PM PDT 24
Finished Jun 21 06:11:25 PM PDT 24
Peak memory 198028 kb
Host smart-f9ff2617-4de9-4c5c-83d9-81e296e89bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596288905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.596288905
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1853000867
Short name T561
Test name
Test status
Simulation time 69066542 ps
CPU time 1.31 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:22 PM PDT 24
Peak memory 196748 kb
Host smart-c292b999-e0fd-4667-b966-4a3537a2b5a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853000867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1853000867
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.339531054
Short name T334
Test name
Test status
Simulation time 3282660044 ps
CPU time 96.95 seconds
Started Jun 21 06:11:22 PM PDT 24
Finished Jun 21 06:13:01 PM PDT 24
Peak memory 198124 kb
Host smart-d15fe270-7464-4770-b5c0-5261a8275fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339531054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.g
pio_stress_all.339531054
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1877130626
Short name T599
Test name
Test status
Simulation time 31679984 ps
CPU time 0.71 seconds
Started Jun 21 06:11:21 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 194028 kb
Host smart-a6938fe8-18f1-4fd2-88fd-9509b827f7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877130626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1877130626
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.3100171735
Short name T449
Test name
Test status
Simulation time 498090177 ps
CPU time 8.67 seconds
Started Jun 21 06:11:26 PM PDT 24
Finished Jun 21 06:11:35 PM PDT 24
Peak memory 195612 kb
Host smart-5370f366-1a61-45b5-bb56-962f9fd1e807
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100171735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.3100171735
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1944311177
Short name T375
Test name
Test status
Simulation time 75707343 ps
CPU time 0.65 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:30 PM PDT 24
Peak memory 194420 kb
Host smart-76a084c2-231b-4616-9ef7-a9428e639fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944311177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1944311177
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3085390532
Short name T277
Test name
Test status
Simulation time 552077595 ps
CPU time 0.91 seconds
Started Jun 21 06:11:20 PM PDT 24
Finished Jun 21 06:11:23 PM PDT 24
Peak memory 196588 kb
Host smart-48d7d1b1-cbbd-4a97-b59f-078e79f49b56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085390532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3085390532
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3029169093
Short name T456
Test name
Test status
Simulation time 243913376 ps
CPU time 2.49 seconds
Started Jun 21 06:11:20 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 198164 kb
Host smart-ca5df8ab-73ca-4d06-99a3-c13225a0115b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029169093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3029169093
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3121238302
Short name T157
Test name
Test status
Simulation time 165798661 ps
CPU time 1.98 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:23 PM PDT 24
Peak memory 196908 kb
Host smart-c44e58ff-2ec1-438a-ae6a-1afbb7f1095f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121238302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3121238302
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1416935116
Short name T339
Test name
Test status
Simulation time 170160839 ps
CPU time 0.88 seconds
Started Jun 21 06:11:23 PM PDT 24
Finished Jun 21 06:11:26 PM PDT 24
Peak memory 196608 kb
Host smart-ee57447c-67c6-43fd-b005-fa8a6c0ff94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416935116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1416935116
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1528917658
Short name T556
Test name
Test status
Simulation time 45078333 ps
CPU time 1.18 seconds
Started Jun 21 06:11:19 PM PDT 24
Finished Jun 21 06:11:22 PM PDT 24
Peak memory 196132 kb
Host smart-22650c4e-68a7-454f-8cba-a9fd76423886
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528917658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1528917658
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3408075344
Short name T104
Test name
Test status
Simulation time 1243561721 ps
CPU time 5.44 seconds
Started Jun 21 06:11:27 PM PDT 24
Finished Jun 21 06:11:34 PM PDT 24
Peak memory 197976 kb
Host smart-6efb99dd-4699-4823-8f7f-72fb7f5b9519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408075344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3408075344
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.778239830
Short name T464
Test name
Test status
Simulation time 83455920 ps
CPU time 1.45 seconds
Started Jun 21 06:11:21 PM PDT 24
Finished Jun 21 06:11:24 PM PDT 24
Peak memory 196856 kb
Host smart-7ef0eafe-092d-4b23-bfb6-66abcd01d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778239830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.778239830
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3598450439
Short name T297
Test name
Test status
Simulation time 49821967 ps
CPU time 1.01 seconds
Started Jun 21 06:11:20 PM PDT 24
Finished Jun 21 06:11:23 PM PDT 24
Peak memory 195852 kb
Host smart-d379099f-499f-4dea-be16-26073105deca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598450439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3598450439
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.46427575
Short name T131
Test name
Test status
Simulation time 9460821761 ps
CPU time 62.32 seconds
Started Jun 21 06:11:32 PM PDT 24
Finished Jun 21 06:12:35 PM PDT 24
Peak memory 198168 kb
Host smart-be46cd03-7670-49c7-b780-ee0bbde35dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46427575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gp
io_stress_all.46427575
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.233405329
Short name T575
Test name
Test status
Simulation time 23557151 ps
CPU time 0.57 seconds
Started Jun 21 06:11:30 PM PDT 24
Finished Jun 21 06:11:32 PM PDT 24
Peak memory 193860 kb
Host smart-ebc2c05e-272d-4176-a036-f0d61dbdae87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233405329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.233405329
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3947797238
Short name T622
Test name
Test status
Simulation time 120321906 ps
CPU time 0.76 seconds
Started Jun 21 06:11:26 PM PDT 24
Finished Jun 21 06:11:28 PM PDT 24
Peak memory 196024 kb
Host smart-1b003b37-d8e0-4803-b5c9-efa6b9edd6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947797238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3947797238
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.2712653738
Short name T411
Test name
Test status
Simulation time 821960057 ps
CPU time 12.15 seconds
Started Jun 21 06:11:30 PM PDT 24
Finished Jun 21 06:11:43 PM PDT 24
Peak memory 196540 kb
Host smart-da980e9c-55d6-465c-8e54-753e2b8c5226
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712653738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.2712653738
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2591147715
Short name T221
Test name
Test status
Simulation time 170747680 ps
CPU time 0.76 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:30 PM PDT 24
Peak memory 195936 kb
Host smart-b2f74d6c-56e2-4b9b-b1f8-78899b8a1873
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591147715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2591147715
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.146023104
Short name T408
Test name
Test status
Simulation time 193137674 ps
CPU time 1.29 seconds
Started Jun 21 06:11:26 PM PDT 24
Finished Jun 21 06:11:28 PM PDT 24
Peak memory 197088 kb
Host smart-d3ecd82e-ec00-4f65-b11e-d923733d6488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146023104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.146023104
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.3196087542
Short name T262
Test name
Test status
Simulation time 337376957 ps
CPU time 2.25 seconds
Started Jun 21 06:11:27 PM PDT 24
Finished Jun 21 06:11:30 PM PDT 24
Peak memory 198164 kb
Host smart-b8909277-992b-442a-bea5-35732f922eeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196087542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.3196087542
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.128480459
Short name T398
Test name
Test status
Simulation time 426359346 ps
CPU time 2.66 seconds
Started Jun 21 06:11:30 PM PDT 24
Finished Jun 21 06:11:34 PM PDT 24
Peak memory 195864 kb
Host smart-2a0e54bd-003a-46d7-bf38-90ff3753025a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128480459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger.
128480459
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1523203298
Short name T657
Test name
Test status
Simulation time 32939856 ps
CPU time 1.3 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:31 PM PDT 24
Peak memory 195884 kb
Host smart-0d5e4893-6ad5-481e-9be2-72f47e0c60b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523203298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1523203298
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1144675110
Short name T436
Test name
Test status
Simulation time 201114262 ps
CPU time 1.18 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:30 PM PDT 24
Peak memory 196756 kb
Host smart-111172ba-c45a-4f25-a69f-c15d242fae91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144675110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1144675110
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1868090320
Short name T378
Test name
Test status
Simulation time 190338523 ps
CPU time 1.27 seconds
Started Jun 21 06:11:29 PM PDT 24
Finished Jun 21 06:11:32 PM PDT 24
Peak memory 197940 kb
Host smart-74308ec8-12a1-433f-a03a-f31eee1731ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868090320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1868090320
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.435687585
Short name T144
Test name
Test status
Simulation time 51654346 ps
CPU time 1.09 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:31 PM PDT 24
Peak memory 196564 kb
Host smart-386269b0-70aa-4059-b934-6d95acd66ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435687585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.435687585
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.878459702
Short name T164
Test name
Test status
Simulation time 188588034 ps
CPU time 0.74 seconds
Started Jun 21 06:11:27 PM PDT 24
Finished Jun 21 06:11:29 PM PDT 24
Peak memory 195936 kb
Host smart-e9a703e5-428c-49d8-a64a-ea2b21145039
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878459702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.878459702
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1074027877
Short name T689
Test name
Test status
Simulation time 2928372946 ps
CPU time 31.95 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:12:01 PM PDT 24
Peak memory 198192 kb
Host smart-a6625d75-f4d4-4c3a-a1ed-7eeb39633ccb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074027877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1074027877
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2474698450
Short name T65
Test name
Test status
Simulation time 174214593053 ps
CPU time 541.54 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:20:32 PM PDT 24
Peak memory 198316 kb
Host smart-5a31bf57-805e-4c7b-b6c5-2751ed6c8618
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2474698450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2474698450
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3476589836
Short name T519
Test name
Test status
Simulation time 15522261 ps
CPU time 0.58 seconds
Started Jun 21 06:11:27 PM PDT 24
Finished Jun 21 06:11:29 PM PDT 24
Peak memory 193828 kb
Host smart-45e8dc07-f96d-42b1-a1ff-db27f79c513b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476589836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3476589836
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.48747811
Short name T560
Test name
Test status
Simulation time 57390307 ps
CPU time 0.66 seconds
Started Jun 21 06:11:26 PM PDT 24
Finished Jun 21 06:11:28 PM PDT 24
Peak memory 194092 kb
Host smart-fa9b0de2-3810-40d6-aec5-b914e787ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48747811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.48747811
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3488204084
Short name T583
Test name
Test status
Simulation time 268137946 ps
CPU time 10.03 seconds
Started Jun 21 06:11:26 PM PDT 24
Finished Jun 21 06:11:36 PM PDT 24
Peak memory 196804 kb
Host smart-065a5d1d-bbb6-4c21-ab33-928529d14cab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488204084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3488204084
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.4129511175
Short name T8
Test name
Test status
Simulation time 72900216 ps
CPU time 0.95 seconds
Started Jun 21 06:11:27 PM PDT 24
Finished Jun 21 06:11:29 PM PDT 24
Peak memory 197036 kb
Host smart-5cdd4966-01e9-4f21-a86d-df2ddee21bcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129511175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.4129511175
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.4021345092
Short name T243
Test name
Test status
Simulation time 87781865 ps
CPU time 0.76 seconds
Started Jun 21 06:11:31 PM PDT 24
Finished Jun 21 06:11:33 PM PDT 24
Peak memory 196096 kb
Host smart-45ae93d1-922b-4ea4-bfb0-6bf8ae35c944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021345092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.4021345092
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3518479889
Short name T275
Test name
Test status
Simulation time 30636533 ps
CPU time 1.25 seconds
Started Jun 21 06:11:31 PM PDT 24
Finished Jun 21 06:11:33 PM PDT 24
Peak memory 197796 kb
Host smart-8c1fd542-3528-480d-a31d-c292b9e6d54f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518479889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3518479889
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2025720826
Short name T590
Test name
Test status
Simulation time 304053243 ps
CPU time 2.13 seconds
Started Jun 21 06:11:29 PM PDT 24
Finished Jun 21 06:11:32 PM PDT 24
Peak memory 196048 kb
Host smart-c57366fa-462c-4c40-bd13-4d1ac5699f4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025720826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2025720826
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.502756746
Short name T217
Test name
Test status
Simulation time 40964533 ps
CPU time 0.96 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:31 PM PDT 24
Peak memory 196556 kb
Host smart-be9d55bb-bded-4360-91d1-a19a4f69a857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502756746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.502756746
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.4088638899
Short name T305
Test name
Test status
Simulation time 30516040 ps
CPU time 0.83 seconds
Started Jun 21 06:11:27 PM PDT 24
Finished Jun 21 06:11:29 PM PDT 24
Peak memory 195500 kb
Host smart-906a9bbb-0ee1-4943-9f55-94e07393baba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088638899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.4088638899
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3272328465
Short name T646
Test name
Test status
Simulation time 301255168 ps
CPU time 5.18 seconds
Started Jun 21 06:11:26 PM PDT 24
Finished Jun 21 06:11:32 PM PDT 24
Peak memory 198052 kb
Host smart-ac9413df-4f67-448b-8e8b-e2b16e90fcab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272328465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3272328465
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1873574406
Short name T269
Test name
Test status
Simulation time 232857382 ps
CPU time 1.38 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:31 PM PDT 24
Peak memory 198028 kb
Host smart-9fcad487-fb51-417c-975c-fe8c1f700c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873574406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1873574406
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2107947019
Short name T499
Test name
Test status
Simulation time 214850032 ps
CPU time 0.91 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:11:31 PM PDT 24
Peak memory 195300 kb
Host smart-f9462946-d683-48d8-bac6-ecf9052b2d5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107947019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2107947019
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2278501291
Short name T458
Test name
Test status
Simulation time 48517671935 ps
CPU time 140.48 seconds
Started Jun 21 06:11:28 PM PDT 24
Finished Jun 21 06:13:50 PM PDT 24
Peak memory 198180 kb
Host smart-c2005660-0c7b-4658-92b5-370c2ff479d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278501291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2278501291
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1568841582
Short name T660
Test name
Test status
Simulation time 10198423 ps
CPU time 0.61 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:36 PM PDT 24
Peak memory 192708 kb
Host smart-00fb9d07-cdda-4394-9de0-b2750c59f2b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568841582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1568841582
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.930101718
Short name T480
Test name
Test status
Simulation time 74144363 ps
CPU time 0.89 seconds
Started Jun 21 06:11:34 PM PDT 24
Finished Jun 21 06:11:36 PM PDT 24
Peak memory 196500 kb
Host smart-5a343e35-1d93-49f0-ae4b-8820a91134da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930101718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.930101718
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3048449999
Short name T274
Test name
Test status
Simulation time 682231177 ps
CPU time 10.61 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:47 PM PDT 24
Peak memory 198032 kb
Host smart-f6f1f929-c0f5-414c-9d73-302c3d79af18
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048449999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3048449999
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3184700925
Short name T507
Test name
Test status
Simulation time 390557760 ps
CPU time 0.88 seconds
Started Jun 21 06:11:33 PM PDT 24
Finished Jun 21 06:11:34 PM PDT 24
Peak memory 196744 kb
Host smart-69d6c9da-9cf2-40d9-9a33-3f7b94e4d74f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184700925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3184700925
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3781926158
Short name T288
Test name
Test status
Simulation time 123875898 ps
CPU time 0.81 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:37 PM PDT 24
Peak memory 195364 kb
Host smart-423bdcca-a7a1-40a4-84a0-3342209409f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781926158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3781926158
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.447582291
Short name T207
Test name
Test status
Simulation time 58784274 ps
CPU time 1.32 seconds
Started Jun 21 06:11:33 PM PDT 24
Finished Jun 21 06:11:35 PM PDT 24
Peak memory 196416 kb
Host smart-6bc00392-0029-4ffb-9300-672b382bf10d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447582291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.447582291
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1174749750
Short name T495
Test name
Test status
Simulation time 75173592 ps
CPU time 2.37 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:38 PM PDT 24
Peak memory 195828 kb
Host smart-602bf75b-f1f8-4eec-af79-654eb230d134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174749750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1174749750
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1724662519
Short name T562
Test name
Test status
Simulation time 79418224 ps
CPU time 0.72 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:37 PM PDT 24
Peak memory 196104 kb
Host smart-f1698a5f-67fa-45a6-b4ae-e433093205a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724662519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1724662519
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3544784932
Short name T632
Test name
Test status
Simulation time 38547546 ps
CPU time 0.97 seconds
Started Jun 21 06:11:39 PM PDT 24
Finished Jun 21 06:11:40 PM PDT 24
Peak memory 196052 kb
Host smart-3d68c3c7-0b9d-48f0-b713-b2f68f89c3fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544784932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3544784932
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.4084588766
Short name T553
Test name
Test status
Simulation time 88056715 ps
CPU time 3.73 seconds
Started Jun 21 06:11:34 PM PDT 24
Finished Jun 21 06:11:38 PM PDT 24
Peak memory 197788 kb
Host smart-14e14924-75e7-4b80-8f5d-d6224e0effe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084588766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.4084588766
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2223098231
Short name T584
Test name
Test status
Simulation time 67139935 ps
CPU time 1.17 seconds
Started Jun 21 06:11:26 PM PDT 24
Finished Jun 21 06:11:28 PM PDT 24
Peak memory 195872 kb
Host smart-5a312586-3a7a-4655-9c2b-2c0e7bcb4f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223098231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2223098231
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1571127373
Short name T679
Test name
Test status
Simulation time 54873184 ps
CPU time 1.47 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:38 PM PDT 24
Peak memory 196728 kb
Host smart-122944aa-6694-45c0-886f-2c65e588ca5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571127373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1571127373
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.568554439
Short name T571
Test name
Test status
Simulation time 50136229817 ps
CPU time 117.45 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:13:34 PM PDT 24
Peak memory 198136 kb
Host smart-8d013804-bd43-4b18-8e47-6031baadc69c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568554439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.568554439
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2394213408
Short name T569
Test name
Test status
Simulation time 111600889202 ps
CPU time 544.69 seconds
Started Jun 21 06:11:34 PM PDT 24
Finished Jun 21 06:20:39 PM PDT 24
Peak memory 198264 kb
Host smart-d8a9d0fe-5d78-4adf-b61b-8ead3b0039db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2394213408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2394213408
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1408784792
Short name T385
Test name
Test status
Simulation time 13163182 ps
CPU time 0.59 seconds
Started Jun 21 06:09:33 PM PDT 24
Finished Jun 21 06:09:35 PM PDT 24
Peak memory 194024 kb
Host smart-88dd7057-2094-40d7-9140-98ef5fb41a37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408784792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1408784792
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.2851820678
Short name T474
Test name
Test status
Simulation time 15634294 ps
CPU time 0.64 seconds
Started Jun 21 06:09:33 PM PDT 24
Finished Jun 21 06:09:35 PM PDT 24
Peak memory 193848 kb
Host smart-93b9f1e9-2d28-4342-bd9a-606d964d5dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851820678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.2851820678
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3159789046
Short name T158
Test name
Test status
Simulation time 1707890040 ps
CPU time 12.89 seconds
Started Jun 21 06:09:32 PM PDT 24
Finished Jun 21 06:09:46 PM PDT 24
Peak memory 195556 kb
Host smart-87d2f71b-7d38-4a70-8b63-cdd8b9cbd8c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159789046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3159789046
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3705678400
Short name T491
Test name
Test status
Simulation time 86752115 ps
CPU time 1.15 seconds
Started Jun 21 06:09:35 PM PDT 24
Finished Jun 21 06:09:37 PM PDT 24
Peak memory 196588 kb
Host smart-ee05490a-df9d-447a-8437-b490053e8762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705678400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3705678400
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3310694821
Short name T540
Test name
Test status
Simulation time 231792302 ps
CPU time 1.19 seconds
Started Jun 21 06:09:32 PM PDT 24
Finished Jun 21 06:09:34 PM PDT 24
Peak memory 195956 kb
Host smart-b6ad0515-4857-4374-a622-852a10171e0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310694821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3310694821
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3547490799
Short name T711
Test name
Test status
Simulation time 38410605 ps
CPU time 0.93 seconds
Started Jun 21 06:09:35 PM PDT 24
Finished Jun 21 06:09:37 PM PDT 24
Peak memory 196024 kb
Host smart-6d4f738d-0263-435d-a9b7-8ba4b3505ccc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547490799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3547490799
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.38199410
Short name T692
Test name
Test status
Simulation time 189065264 ps
CPU time 1.15 seconds
Started Jun 21 06:09:32 PM PDT 24
Finished Jun 21 06:09:34 PM PDT 24
Peak memory 195580 kb
Host smart-938ccc2f-f745-4c76-aa36-3ee6e6458164
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38199410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.38199410
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.522840034
Short name T544
Test name
Test status
Simulation time 29010162 ps
CPU time 0.81 seconds
Started Jun 21 06:09:33 PM PDT 24
Finished Jun 21 06:09:35 PM PDT 24
Peak memory 196032 kb
Host smart-8c0c1e5f-cc9f-4821-9999-aed819dcc846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522840034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.522840034
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2137803564
Short name T263
Test name
Test status
Simulation time 48422876 ps
CPU time 1.14 seconds
Started Jun 21 06:09:34 PM PDT 24
Finished Jun 21 06:09:36 PM PDT 24
Peak memory 195848 kb
Host smart-134978e8-9442-406a-9e1e-a286ab2d6699
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137803564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2137803564
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3703976803
Short name T10
Test name
Test status
Simulation time 1205055569 ps
CPU time 3.8 seconds
Started Jun 21 06:09:35 PM PDT 24
Finished Jun 21 06:09:40 PM PDT 24
Peak memory 198052 kb
Host smart-f20eeb53-8e21-4b50-874c-ac0c32bb30f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703976803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3703976803
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2398949952
Short name T41
Test name
Test status
Simulation time 330752132 ps
CPU time 1 seconds
Started Jun 21 06:09:33 PM PDT 24
Finished Jun 21 06:09:35 PM PDT 24
Peak memory 214816 kb
Host smart-9ebe204b-e836-4335-adfa-7c8d524e23ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398949952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2398949952
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.4027588493
Short name T224
Test name
Test status
Simulation time 106361242 ps
CPU time 0.9 seconds
Started Jun 21 06:09:26 PM PDT 24
Finished Jun 21 06:09:28 PM PDT 24
Peak memory 196268 kb
Host smart-7ec83184-86c1-4e01-a821-801156e63afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027588493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.4027588493
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2185853250
Short name T215
Test name
Test status
Simulation time 45513444 ps
CPU time 1.17 seconds
Started Jun 21 06:09:33 PM PDT 24
Finished Jun 21 06:09:35 PM PDT 24
Peak memory 195792 kb
Host smart-a1167233-b2bd-4b16-bf7e-4633e3082057
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185853250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2185853250
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1170544500
Short name T510
Test name
Test status
Simulation time 148960818885 ps
CPU time 181.59 seconds
Started Jun 21 06:09:33 PM PDT 24
Finished Jun 21 06:12:35 PM PDT 24
Peak memory 198188 kb
Host smart-adce4360-5d94-4269-b58a-e1e8e1fd1d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170544500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1170544500
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.88885072
Short name T328
Test name
Test status
Simulation time 14687025 ps
CPU time 0.59 seconds
Started Jun 21 06:11:41 PM PDT 24
Finished Jun 21 06:11:42 PM PDT 24
Peak memory 193836 kb
Host smart-6ab44641-7e5b-4011-a0b5-a6638caff32c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88885072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.88885072
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.40251445
Short name T515
Test name
Test status
Simulation time 34561126 ps
CPU time 0.86 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:37 PM PDT 24
Peak memory 196132 kb
Host smart-dc651589-bdf4-4eaa-bca4-14d28d7ea977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40251445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.40251445
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.27469139
Short name T159
Test name
Test status
Simulation time 616336121 ps
CPU time 21.39 seconds
Started Jun 21 06:11:34 PM PDT 24
Finished Jun 21 06:11:56 PM PDT 24
Peak memory 198008 kb
Host smart-6a9d7d36-61f3-4df9-a04d-5446543715ee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27469139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stress
.27469139
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.1348846754
Short name T327
Test name
Test status
Simulation time 59061039 ps
CPU time 0.78 seconds
Started Jun 21 06:11:33 PM PDT 24
Finished Jun 21 06:11:35 PM PDT 24
Peak memory 195808 kb
Host smart-1dc22990-397d-4f00-8c31-b2225032c6a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348846754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.1348846754
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3837296340
Short name T705
Test name
Test status
Simulation time 62537916 ps
CPU time 1.01 seconds
Started Jun 21 06:11:38 PM PDT 24
Finished Jun 21 06:11:40 PM PDT 24
Peak memory 196060 kb
Host smart-9d2cdf1e-eb4d-4755-8dac-ffd7328edc67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837296340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3837296340
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3392934259
Short name T506
Test name
Test status
Simulation time 323057206 ps
CPU time 2.5 seconds
Started Jun 21 06:11:36 PM PDT 24
Finished Jun 21 06:11:40 PM PDT 24
Peak memory 196540 kb
Host smart-be0a30a2-ad63-4b9b-9cfb-26014f6fb9e8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392934259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3392934259
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3994129329
Short name T707
Test name
Test status
Simulation time 329687698 ps
CPU time 1.19 seconds
Started Jun 21 06:11:36 PM PDT 24
Finished Jun 21 06:11:38 PM PDT 24
Peak memory 196416 kb
Host smart-14895878-c76f-478f-9e35-a0f6dda52cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994129329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3994129329
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.1296860906
Short name T25
Test name
Test status
Simulation time 29377590 ps
CPU time 1.12 seconds
Started Jun 21 06:11:33 PM PDT 24
Finished Jun 21 06:11:35 PM PDT 24
Peak memory 196128 kb
Host smart-2faa1ded-594a-41b2-a1dd-32f09b2531cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296860906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.1296860906
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.969552055
Short name T681
Test name
Test status
Simulation time 63179768 ps
CPU time 1.18 seconds
Started Jun 21 06:11:38 PM PDT 24
Finished Jun 21 06:11:40 PM PDT 24
Peak memory 196060 kb
Host smart-f9c3f538-60a8-403e-b802-1e851e2c3e0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969552055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.969552055
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3614992904
Short name T530
Test name
Test status
Simulation time 70674620 ps
CPU time 3.27 seconds
Started Jun 21 06:11:39 PM PDT 24
Finished Jun 21 06:11:43 PM PDT 24
Peak memory 198052 kb
Host smart-c2fdedd3-fd8e-4a61-90fd-d87f8a5bc9f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614992904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3614992904
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1242343681
Short name T24
Test name
Test status
Simulation time 98932720 ps
CPU time 1.02 seconds
Started Jun 21 06:11:35 PM PDT 24
Finished Jun 21 06:11:37 PM PDT 24
Peak memory 195556 kb
Host smart-bc77aab1-1cd3-476c-af4f-bb830590d7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242343681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1242343681
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.433783078
Short name T670
Test name
Test status
Simulation time 161723319 ps
CPU time 0.94 seconds
Started Jun 21 06:11:38 PM PDT 24
Finished Jun 21 06:11:40 PM PDT 24
Peak memory 195120 kb
Host smart-a102fb24-85ba-4627-85af-3b190468e045
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433783078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.433783078
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.2253522911
Short name T322
Test name
Test status
Simulation time 19281177855 ps
CPU time 239.97 seconds
Started Jun 21 06:11:39 PM PDT 24
Finished Jun 21 06:15:40 PM PDT 24
Peak memory 198108 kb
Host smart-68b7ae1b-8f76-4352-8b27-3ca39fff498e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253522911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.2253522911
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3833496571
Short name T229
Test name
Test status
Simulation time 14049280 ps
CPU time 0.58 seconds
Started Jun 21 06:11:42 PM PDT 24
Finished Jun 21 06:11:43 PM PDT 24
Peak memory 193836 kb
Host smart-b0769771-6caa-444d-bcf2-30d67d42edd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833496571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3833496571
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1896553893
Short name T194
Test name
Test status
Simulation time 26298027 ps
CPU time 0.63 seconds
Started Jun 21 06:11:42 PM PDT 24
Finished Jun 21 06:11:43 PM PDT 24
Peak memory 193900 kb
Host smart-b26fca7b-774d-4dac-aebf-9a2008e1ab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896553893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1896553893
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1061886637
Short name T374
Test name
Test status
Simulation time 335349016 ps
CPU time 11.55 seconds
Started Jun 21 06:11:41 PM PDT 24
Finished Jun 21 06:11:53 PM PDT 24
Peak memory 196932 kb
Host smart-129ba6ea-63c3-44ce-af43-c0dfed958db8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061886637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1061886637
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3033127891
Short name T536
Test name
Test status
Simulation time 62865372 ps
CPU time 0.7 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:45 PM PDT 24
Peak memory 194760 kb
Host smart-f0a50cfc-c8db-47a8-8326-37cf390ccd08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033127891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3033127891
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2839873746
Short name T419
Test name
Test status
Simulation time 197530667 ps
CPU time 0.85 seconds
Started Jun 21 06:11:41 PM PDT 24
Finished Jun 21 06:11:43 PM PDT 24
Peak memory 196452 kb
Host smart-9abea3b3-1161-4702-b051-69be089a72c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839873746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2839873746
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3777122870
Short name T416
Test name
Test status
Simulation time 44516129 ps
CPU time 1.88 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:46 PM PDT 24
Peak memory 197384 kb
Host smart-b25efd3f-4867-4442-8a6a-5282bcb98cbd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777122870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3777122870
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2689322683
Short name T254
Test name
Test status
Simulation time 557472821 ps
CPU time 3.22 seconds
Started Jun 21 06:11:42 PM PDT 24
Finished Jun 21 06:11:46 PM PDT 24
Peak memory 197228 kb
Host smart-5bead52d-f34e-4793-a65b-3d44bbf85c71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689322683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2689322683
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1594482969
Short name T311
Test name
Test status
Simulation time 60130702 ps
CPU time 0.8 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:44 PM PDT 24
Peak memory 195480 kb
Host smart-11a7a4f7-55a3-4d31-a192-6e5ed1fe676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594482969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1594482969
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3554312487
Short name T642
Test name
Test status
Simulation time 27743470 ps
CPU time 0.75 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:45 PM PDT 24
Peak memory 194252 kb
Host smart-147665f9-2284-4003-83e8-af75037df10a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554312487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3554312487
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1284463766
Short name T661
Test name
Test status
Simulation time 3409055896 ps
CPU time 3.19 seconds
Started Jun 21 06:11:45 PM PDT 24
Finished Jun 21 06:11:49 PM PDT 24
Peak memory 198028 kb
Host smart-092f3686-87a2-443f-a520-741528769ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284463766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1284463766
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.12475033
Short name T118
Test name
Test status
Simulation time 199585922 ps
CPU time 1.01 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:45 PM PDT 24
Peak memory 195780 kb
Host smart-2176c9d0-44f3-4996-9a85-a5a8dcbb76ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12475033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.12475033
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.1889864644
Short name T14
Test name
Test status
Simulation time 44320511 ps
CPU time 0.97 seconds
Started Jun 21 06:11:42 PM PDT 24
Finished Jun 21 06:11:44 PM PDT 24
Peak memory 196032 kb
Host smart-fe9e9287-d2df-4204-89b1-8be63a297440
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889864644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.1889864644
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1303543501
Short name T395
Test name
Test status
Simulation time 18583596063 ps
CPU time 72.91 seconds
Started Jun 21 06:11:42 PM PDT 24
Finished Jun 21 06:12:55 PM PDT 24
Peak memory 198176 kb
Host smart-a10c3e22-46ac-41dc-89fd-0019c4a08daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303543501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1303543501
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1406612048
Short name T469
Test name
Test status
Simulation time 10537212 ps
CPU time 0.58 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:11:52 PM PDT 24
Peak memory 193828 kb
Host smart-5fcbeece-db4e-4b1b-b954-b431147fd27b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406612048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1406612048
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1955893038
Short name T588
Test name
Test status
Simulation time 56520366 ps
CPU time 0.74 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:45 PM PDT 24
Peak memory 195232 kb
Host smart-713f0203-e9f5-4965-9c44-7d6331ad73f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955893038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1955893038
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3066696983
Short name T492
Test name
Test status
Simulation time 3007832439 ps
CPU time 27.72 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:12:19 PM PDT 24
Peak memory 196924 kb
Host smart-90c50b07-a0ef-4c0b-aa9f-467d6fab9e45
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066696983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3066696983
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3188768177
Short name T470
Test name
Test status
Simulation time 133358383 ps
CPU time 0.76 seconds
Started Jun 21 06:11:48 PM PDT 24
Finished Jun 21 06:11:49 PM PDT 24
Peak memory 196480 kb
Host smart-9bc929bd-f1d1-46a2-89e0-7e5690e93993
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188768177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3188768177
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.103960392
Short name T422
Test name
Test status
Simulation time 33998655 ps
CPU time 0.84 seconds
Started Jun 21 06:11:42 PM PDT 24
Finished Jun 21 06:11:44 PM PDT 24
Peak memory 196092 kb
Host smart-2263e069-056c-4015-9466-b3e28228632e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103960392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.103960392
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3525624477
Short name T192
Test name
Test status
Simulation time 301878906 ps
CPU time 3.36 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:11:53 PM PDT 24
Peak memory 198092 kb
Host smart-6cd04840-b506-4a0d-a1fd-be9090b146e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525624477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3525624477
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1998737522
Short name T417
Test name
Test status
Simulation time 63810437 ps
CPU time 1.7 seconds
Started Jun 21 06:11:51 PM PDT 24
Finished Jun 21 06:11:54 PM PDT 24
Peak memory 196048 kb
Host smart-69a22c6a-0c4d-4544-984e-07246ce12170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998737522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1998737522
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3310264270
Short name T663
Test name
Test status
Simulation time 303444970 ps
CPU time 1.36 seconds
Started Jun 21 06:11:45 PM PDT 24
Finished Jun 21 06:11:47 PM PDT 24
Peak memory 195840 kb
Host smart-1bb45d41-7f66-4ac3-8ed6-7f5b438a202a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310264270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3310264270
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2155766471
Short name T257
Test name
Test status
Simulation time 511032492 ps
CPU time 1.53 seconds
Started Jun 21 06:11:40 PM PDT 24
Finished Jun 21 06:11:42 PM PDT 24
Peak memory 197048 kb
Host smart-c14fc3b4-69dd-420e-a57c-d038f33982e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155766471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2155766471
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3630299060
Short name T380
Test name
Test status
Simulation time 448711426 ps
CPU time 5 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:11:56 PM PDT 24
Peak memory 197992 kb
Host smart-2d00bc82-2518-4765-8993-efb99581e408
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630299060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3630299060
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1305236539
Short name T488
Test name
Test status
Simulation time 317170233 ps
CPU time 0.9 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:45 PM PDT 24
Peak memory 195352 kb
Host smart-41118db6-dca6-4089-b2bd-073e2811d635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305236539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1305236539
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.65186531
Short name T686
Test name
Test status
Simulation time 272526892 ps
CPU time 1.35 seconds
Started Jun 21 06:11:43 PM PDT 24
Finished Jun 21 06:11:45 PM PDT 24
Peak memory 195932 kb
Host smart-9d547a02-b6a8-44b0-bb29-30ef8aeddea4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65186531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.65186531
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.934638765
Short name T539
Test name
Test status
Simulation time 68254005283 ps
CPU time 214.39 seconds
Started Jun 21 06:11:49 PM PDT 24
Finished Jun 21 06:15:24 PM PDT 24
Peak memory 198252 kb
Host smart-339c45cc-263d-4951-b78a-309e6facac9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934638765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.934638765
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3829998128
Short name T300
Test name
Test status
Simulation time 47031468 ps
CPU time 0.58 seconds
Started Jun 21 06:11:58 PM PDT 24
Finished Jun 21 06:12:00 PM PDT 24
Peak memory 193820 kb
Host smart-685ec17f-74a1-402a-81ad-d1e200446029
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829998128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3829998128
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.65595953
Short name T332
Test name
Test status
Simulation time 19339821 ps
CPU time 0.73 seconds
Started Jun 21 06:11:47 PM PDT 24
Finished Jun 21 06:11:49 PM PDT 24
Peak memory 195088 kb
Host smart-305ff05b-46bd-4db2-a6bb-5574fbff0731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65595953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.65595953
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3283082499
Short name T589
Test name
Test status
Simulation time 2620741410 ps
CPU time 16.04 seconds
Started Jun 21 06:11:48 PM PDT 24
Finished Jun 21 06:12:05 PM PDT 24
Peak memory 198148 kb
Host smart-adb0b02a-a366-445d-806f-6a88a5d30875
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283082499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3283082499
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.833620076
Short name T489
Test name
Test status
Simulation time 56801777 ps
CPU time 0.81 seconds
Started Jun 21 06:12:00 PM PDT 24
Finished Jun 21 06:12:01 PM PDT 24
Peak memory 195736 kb
Host smart-bcd7a910-541a-4516-9fa5-cdac796c02ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833620076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.833620076
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.564062216
Short name T392
Test name
Test status
Simulation time 536774679 ps
CPU time 1.03 seconds
Started Jun 21 06:11:52 PM PDT 24
Finished Jun 21 06:11:53 PM PDT 24
Peak memory 195960 kb
Host smart-e3814eea-67de-41a4-8ab7-f09edec7c2c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564062216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.564062216
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1209066269
Short name T354
Test name
Test status
Simulation time 190388002 ps
CPU time 2.07 seconds
Started Jun 21 06:11:52 PM PDT 24
Finished Jun 21 06:11:54 PM PDT 24
Peak memory 198176 kb
Host smart-191f9957-9ca4-4e46-82fc-bbb2a81a6d86
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209066269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1209066269
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.368243288
Short name T542
Test name
Test status
Simulation time 180255731 ps
CPU time 2.62 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:11:54 PM PDT 24
Peak memory 198068 kb
Host smart-f80d16d6-be47-4479-815e-66ac15a539ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368243288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
368243288
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.296105673
Short name T465
Test name
Test status
Simulation time 27237650 ps
CPU time 0.63 seconds
Started Jun 21 06:11:49 PM PDT 24
Finished Jun 21 06:11:51 PM PDT 24
Peak memory 194176 kb
Host smart-2aa9a4fa-ad3e-4e9c-a6c4-1240ba347dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296105673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.296105673
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.716088803
Short name T457
Test name
Test status
Simulation time 40530624 ps
CPU time 0.77 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:11:51 PM PDT 24
Peak memory 195404 kb
Host smart-0b76eb2f-c44d-418e-b5e9-aae0da1fa6f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716088803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.716088803
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.14308052
Short name T518
Test name
Test status
Simulation time 405887064 ps
CPU time 5.06 seconds
Started Jun 21 06:11:56 PM PDT 24
Finished Jun 21 06:12:03 PM PDT 24
Peak memory 198052 kb
Host smart-454a6c66-816d-4f85-9881-b0c512fb6035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14308052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand
om_long_reg_writes_reg_reads.14308052
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.909681822
Short name T240
Test name
Test status
Simulation time 1072577827 ps
CPU time 1.44 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:11:53 PM PDT 24
Peak memory 196720 kb
Host smart-77bcd29b-fc5e-44ff-8c7a-983784ea864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909681822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.909681822
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3496715297
Short name T550
Test name
Test status
Simulation time 69604091 ps
CPU time 0.74 seconds
Started Jun 21 06:11:50 PM PDT 24
Finished Jun 21 06:11:51 PM PDT 24
Peak memory 194752 kb
Host smart-856ab06e-2f40-4063-9376-f24a9b4845de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496715297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3496715297
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.229770596
Short name T513
Test name
Test status
Simulation time 3676502267 ps
CPU time 89.79 seconds
Started Jun 21 06:11:57 PM PDT 24
Finished Jun 21 06:13:29 PM PDT 24
Peak memory 198188 kb
Host smart-3e3b9623-1c61-4d98-8742-8f71d8dd1eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229770596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.229770596
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.2518863900
Short name T337
Test name
Test status
Simulation time 21395547 ps
CPU time 0.57 seconds
Started Jun 21 06:11:56 PM PDT 24
Finished Jun 21 06:11:59 PM PDT 24
Peak memory 193836 kb
Host smart-7f225414-ee01-43f3-8ab9-ae89abed3f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518863900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.2518863900
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2752730523
Short name T361
Test name
Test status
Simulation time 28559722 ps
CPU time 0.77 seconds
Started Jun 21 06:11:55 PM PDT 24
Finished Jun 21 06:11:57 PM PDT 24
Peak memory 195340 kb
Host smart-a376950a-90f4-4cf3-abb9-80decd94cf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752730523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2752730523
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1214725938
Short name T468
Test name
Test status
Simulation time 220748796 ps
CPU time 7.3 seconds
Started Jun 21 06:11:58 PM PDT 24
Finished Jun 21 06:12:07 PM PDT 24
Peak memory 197008 kb
Host smart-c116a487-01f8-401b-9c23-ab28c8f69b41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214725938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1214725938
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.4048424630
Short name T429
Test name
Test status
Simulation time 172994881 ps
CPU time 0.72 seconds
Started Jun 21 06:11:56 PM PDT 24
Finished Jun 21 06:11:58 PM PDT 24
Peak memory 194708 kb
Host smart-6514aac4-fbd0-4f7a-a2e0-1079c2192819
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048424630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.4048424630
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1782084417
Short name T125
Test name
Test status
Simulation time 48574725 ps
CPU time 0.93 seconds
Started Jun 21 06:11:57 PM PDT 24
Finished Jun 21 06:11:59 PM PDT 24
Peak memory 196816 kb
Host smart-1519ef8c-906e-45b4-9418-ac767a7471f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782084417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1782084417
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3239168375
Short name T315
Test name
Test status
Simulation time 186550538 ps
CPU time 3.7 seconds
Started Jun 21 06:11:58 PM PDT 24
Finished Jun 21 06:12:03 PM PDT 24
Peak memory 198012 kb
Host smart-adb7015b-91c7-4216-b402-f8cc8c464ad2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239168375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3239168375
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.432439819
Short name T391
Test name
Test status
Simulation time 444118678 ps
CPU time 3.37 seconds
Started Jun 21 06:11:56 PM PDT 24
Finished Jun 21 06:12:01 PM PDT 24
Peak memory 197300 kb
Host smart-03fda88e-dc94-4fd2-9755-5f08e0450db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432439819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
432439819
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4259677131
Short name T413
Test name
Test status
Simulation time 55123720 ps
CPU time 1.25 seconds
Started Jun 21 06:11:56 PM PDT 24
Finished Jun 21 06:11:59 PM PDT 24
Peak memory 196604 kb
Host smart-fe2394f3-a856-4595-a5d7-81a56de087b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259677131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4259677131
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1362435704
Short name T479
Test name
Test status
Simulation time 34550342 ps
CPU time 0.99 seconds
Started Jun 21 06:11:55 PM PDT 24
Finished Jun 21 06:11:56 PM PDT 24
Peak memory 196052 kb
Host smart-dc2b8d6a-9fee-4734-91a0-3b677695d139
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362435704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1362435704
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.450987876
Short name T120
Test name
Test status
Simulation time 25724228 ps
CPU time 1.32 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:05 PM PDT 24
Peak memory 198000 kb
Host smart-54de8eae-0bed-4c5b-a6b1-ffd4ed2290bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450987876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ran
dom_long_reg_writes_reg_reads.450987876
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.91407497
Short name T714
Test name
Test status
Simulation time 52751825 ps
CPU time 0.88 seconds
Started Jun 21 06:11:57 PM PDT 24
Finished Jun 21 06:11:59 PM PDT 24
Peak memory 196116 kb
Host smart-11e7d8e6-1adc-4c6b-9fb0-5a439312fbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91407497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.91407497
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3432614338
Short name T333
Test name
Test status
Simulation time 307405129 ps
CPU time 1.06 seconds
Started Jun 21 06:11:56 PM PDT 24
Finished Jun 21 06:11:58 PM PDT 24
Peak memory 195584 kb
Host smart-06e88b13-0901-4f4f-aee0-cbe9f0f454cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432614338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3432614338
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2636261928
Short name T541
Test name
Test status
Simulation time 18450350284 ps
CPU time 36.89 seconds
Started Jun 21 06:11:57 PM PDT 24
Finished Jun 21 06:12:36 PM PDT 24
Peak memory 198160 kb
Host smart-dbf77945-9a03-4433-93d7-b22d9a2de045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636261928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2636261928
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2966633466
Short name T202
Test name
Test status
Simulation time 12453022 ps
CPU time 0.59 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:08 PM PDT 24
Peak memory 194528 kb
Host smart-c57e3329-e2c3-4a03-8b2e-991547cf5f8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966633466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2966633466
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1048543074
Short name T251
Test name
Test status
Simulation time 37191792 ps
CPU time 0.93 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:05 PM PDT 24
Peak memory 196180 kb
Host smart-efeb2edf-de62-454b-b708-834bff61f350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048543074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1048543074
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1981933707
Short name T381
Test name
Test status
Simulation time 135371159 ps
CPU time 4.7 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:12 PM PDT 24
Peak memory 196044 kb
Host smart-d7655c7a-5018-4700-9b42-f30d1b2eda6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981933707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1981933707
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.492745138
Short name T292
Test name
Test status
Simulation time 51650462 ps
CPU time 0.86 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:07 PM PDT 24
Peak memory 196608 kb
Host smart-2e170eb0-6f8d-46bd-b77a-34506c1b705d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492745138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.492745138
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1440163875
Short name T534
Test name
Test status
Simulation time 56583971 ps
CPU time 1.36 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:09 PM PDT 24
Peak memory 195916 kb
Host smart-0a20ab12-3906-45c1-9c17-f9365a23c2e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440163875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1440163875
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3076043311
Short name T283
Test name
Test status
Simulation time 92313614 ps
CPU time 3.34 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:11 PM PDT 24
Peak memory 198164 kb
Host smart-547a31e5-ed67-4904-9834-bdcfe498e046
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076043311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3076043311
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3974409125
Short name T317
Test name
Test status
Simulation time 33117705 ps
CPU time 0.97 seconds
Started Jun 21 06:12:07 PM PDT 24
Finished Jun 21 06:12:10 PM PDT 24
Peak memory 194476 kb
Host smart-d51202a0-d5c1-4080-a41b-29b104161147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974409125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3974409125
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2117586893
Short name T15
Test name
Test status
Simulation time 61766841 ps
CPU time 1.32 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:05 PM PDT 24
Peak memory 198068 kb
Host smart-c07705e8-dd74-486f-ad9a-f5180ddd8d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117586893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2117586893
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.952107208
Short name T171
Test name
Test status
Simulation time 28062561 ps
CPU time 1.1 seconds
Started Jun 21 06:11:58 PM PDT 24
Finished Jun 21 06:12:00 PM PDT 24
Peak memory 196024 kb
Host smart-fd6a2d04-3c96-4940-8fb3-7a80b4480b11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952107208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.952107208
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.887993320
Short name T132
Test name
Test status
Simulation time 185666663 ps
CPU time 3.37 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:09 PM PDT 24
Peak memory 198004 kb
Host smart-158c5900-cb89-4bbd-8a07-544d0a2049ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887993320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.887993320
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2020565343
Short name T699
Test name
Test status
Simulation time 139070417 ps
CPU time 1.38 seconds
Started Jun 21 06:11:56 PM PDT 24
Finished Jun 21 06:11:59 PM PDT 24
Peak memory 196932 kb
Host smart-52458f94-7a63-43a8-8d4d-470e13f0b70e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020565343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2020565343
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2610996710
Short name T384
Test name
Test status
Simulation time 42181399 ps
CPU time 1.38 seconds
Started Jun 21 06:11:58 PM PDT 24
Finished Jun 21 06:12:00 PM PDT 24
Peak memory 196780 kb
Host smart-e14df46e-b9f2-402f-97ad-eeca904d6e43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610996710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2610996710
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3337304043
Short name T667
Test name
Test status
Simulation time 55291643825 ps
CPU time 157.22 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:14:44 PM PDT 24
Peak memory 198156 kb
Host smart-8223e442-94c6-4a60-afd9-94e861dd019d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337304043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3337304043
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.3801674730
Short name T683
Test name
Test status
Simulation time 303022776260 ps
CPU time 1663.74 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:39:48 PM PDT 24
Peak memory 206456 kb
Host smart-322eeb12-567a-49bb-a791-de40842546c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3801674730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.3801674730
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4003695599
Short name T59
Test name
Test status
Simulation time 64510910 ps
CPU time 0.6 seconds
Started Jun 21 06:12:07 PM PDT 24
Finished Jun 21 06:12:09 PM PDT 24
Peak memory 194744 kb
Host smart-988f9920-20f6-49df-953c-f4e5739abfd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003695599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4003695599
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1448735335
Short name T593
Test name
Test status
Simulation time 49634748 ps
CPU time 0.98 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:07 PM PDT 24
Peak memory 196464 kb
Host smart-106d8722-0964-4abd-959f-c3f9ae36334b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448735335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1448735335
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2399553766
Short name T592
Test name
Test status
Simulation time 359047402 ps
CPU time 6.52 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:11 PM PDT 24
Peak memory 196756 kb
Host smart-01f7d740-047a-4961-89fa-997905e4af0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399553766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2399553766
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2149824512
Short name T151
Test name
Test status
Simulation time 1475904911 ps
CPU time 1.13 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:06 PM PDT 24
Peak memory 197832 kb
Host smart-9f7dbdee-1335-4fbc-a39f-812d85a98064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149824512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2149824512
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3091388056
Short name T451
Test name
Test status
Simulation time 38918181 ps
CPU time 0.87 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:05 PM PDT 24
Peak memory 195600 kb
Host smart-41c5645f-48c0-41c5-aacf-a4e567d8c50a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091388056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3091388056
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.438050036
Short name T706
Test name
Test status
Simulation time 38198684 ps
CPU time 1.64 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:07 PM PDT 24
Peak memory 196512 kb
Host smart-00ff954a-21f3-405d-90a9-bd4cdedec00b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438050036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.438050036
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.347736054
Short name T344
Test name
Test status
Simulation time 116448405 ps
CPU time 2.46 seconds
Started Jun 21 06:12:06 PM PDT 24
Finished Jun 21 06:12:10 PM PDT 24
Peak memory 196548 kb
Host smart-02e0a2c8-fdb8-4708-91a5-bac425542b76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347736054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
347736054
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.819403270
Short name T655
Test name
Test status
Simulation time 59722685 ps
CPU time 0.98 seconds
Started Jun 21 06:12:11 PM PDT 24
Finished Jun 21 06:12:14 PM PDT 24
Peak memory 196620 kb
Host smart-b5fffeab-e4d4-4550-988b-bdaa5858ad6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819403270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.819403270
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1071244822
Short name T613
Test name
Test status
Simulation time 112159417 ps
CPU time 0.88 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:07 PM PDT 24
Peak memory 196600 kb
Host smart-4861de38-e9a8-4bc3-bb3b-14d721fe1eb6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071244822 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1071244822
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3962755389
Short name T443
Test name
Test status
Simulation time 237895036 ps
CPU time 5.34 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:13 PM PDT 24
Peak memory 197836 kb
Host smart-5e34121e-94fd-45b4-9d99-da406242e08f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962755389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3962755389
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.4135485059
Short name T399
Test name
Test status
Simulation time 170365714 ps
CPU time 1.33 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:08 PM PDT 24
Peak memory 195584 kb
Host smart-cba4217e-930d-408a-9899-a3bfcb636c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135485059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.4135485059
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3864936986
Short name T365
Test name
Test status
Simulation time 196512526 ps
CPU time 1.32 seconds
Started Jun 21 06:12:06 PM PDT 24
Finished Jun 21 06:12:09 PM PDT 24
Peak memory 195552 kb
Host smart-5aae8f21-6085-4fd8-ac5b-33b930a77a78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864936986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3864936986
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1544496254
Short name T564
Test name
Test status
Simulation time 1244234124 ps
CPU time 32.58 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:37 PM PDT 24
Peak memory 198140 kb
Host smart-a41e1dde-92cb-450c-9af2-25d3fbf5baae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544496254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1544496254
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3599210856
Short name T100
Test name
Test status
Simulation time 12269838 ps
CPU time 0.59 seconds
Started Jun 21 06:12:06 PM PDT 24
Finished Jun 21 06:12:09 PM PDT 24
Peak memory 193728 kb
Host smart-0898a92e-b424-4920-b25b-ac6cee10f765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599210856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3599210856
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2439279869
Short name T425
Test name
Test status
Simulation time 18907637 ps
CPU time 0.66 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:05 PM PDT 24
Peak memory 194068 kb
Host smart-b675241c-c7ea-4ec9-8815-47ceae700af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439279869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2439279869
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.1296381200
Short name T546
Test name
Test status
Simulation time 709983451 ps
CPU time 9.81 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:15 PM PDT 24
Peak memory 198032 kb
Host smart-8a0af23c-b4cb-4072-a26e-ee77db2a1214
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296381200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.1296381200
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.45623164
Short name T423
Test name
Test status
Simulation time 40867310 ps
CPU time 0.7 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:08 PM PDT 24
Peak memory 195740 kb
Host smart-5a928554-1d0d-4c1d-b048-f47e908cec2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45623164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.45623164
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1738288846
Short name T367
Test name
Test status
Simulation time 168215902 ps
CPU time 1.08 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:12:08 PM PDT 24
Peak memory 195740 kb
Host smart-40b8c216-77d3-4e1f-9a7d-05531cb538b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738288846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1738288846
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.412940442
Short name T347
Test name
Test status
Simulation time 127653093 ps
CPU time 1.37 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:06 PM PDT 24
Peak memory 196360 kb
Host smart-1cc5c134-9f89-4f67-8b02-3b97c82c4a4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412940442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.412940442
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.49021345
Short name T463
Test name
Test status
Simulation time 81650496 ps
CPU time 2.37 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:10 PM PDT 24
Peak memory 196560 kb
Host smart-5c666ed7-9838-4880-a8ce-10d120009e13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49021345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.49021345
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.2445031146
Short name T234
Test name
Test status
Simulation time 36231981 ps
CPU time 1.33 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:06 PM PDT 24
Peak memory 196960 kb
Host smart-8a66c0f0-61db-4735-8d83-37dbb0e07992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445031146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.2445031146
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1428109267
Short name T596
Test name
Test status
Simulation time 211637522 ps
CPU time 1.3 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:08 PM PDT 24
Peak memory 197000 kb
Host smart-36581034-13e2-40ca-91cc-41e8a9efa299
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428109267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1428109267
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2838407677
Short name T372
Test name
Test status
Simulation time 97959915 ps
CPU time 2.44 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:10 PM PDT 24
Peak memory 197956 kb
Host smart-a4c542c7-46f6-449d-bdeb-550748673330
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838407677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2838407677
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2527242787
Short name T362
Test name
Test status
Simulation time 78644132 ps
CPU time 1.46 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:08 PM PDT 24
Peak memory 196844 kb
Host smart-8cf8ade2-a62e-4ae3-8922-1f69c83b045a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527242787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2527242787
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3553101938
Short name T227
Test name
Test status
Simulation time 268071396 ps
CPU time 0.84 seconds
Started Jun 21 06:12:05 PM PDT 24
Finished Jun 21 06:12:08 PM PDT 24
Peak memory 195092 kb
Host smart-713c52cc-551b-43da-99b2-24e59c38719a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553101938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3553101938
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3061221726
Short name T313
Test name
Test status
Simulation time 12822706963 ps
CPU time 143.3 seconds
Started Jun 21 06:12:04 PM PDT 24
Finished Jun 21 06:14:30 PM PDT 24
Peak memory 198152 kb
Host smart-dd2e5a8a-835f-443b-9fd6-a8a5c965febf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061221726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3061221726
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.422915320
Short name T691
Test name
Test status
Simulation time 13668898 ps
CPU time 0.59 seconds
Started Jun 21 06:12:14 PM PDT 24
Finished Jun 21 06:12:16 PM PDT 24
Peak memory 193800 kb
Host smart-37b6cad6-1357-425d-8afb-d112d8886d9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422915320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.422915320
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4031121423
Short name T204
Test name
Test status
Simulation time 91685891 ps
CPU time 0.85 seconds
Started Jun 21 06:12:14 PM PDT 24
Finished Jun 21 06:12:18 PM PDT 24
Peak memory 195388 kb
Host smart-8980c4f1-7067-438a-964b-c5fc2cf9110b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031121423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4031121423
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3293329100
Short name T324
Test name
Test status
Simulation time 1220191264 ps
CPU time 18.67 seconds
Started Jun 21 06:12:11 PM PDT 24
Finished Jun 21 06:12:32 PM PDT 24
Peak memory 197208 kb
Host smart-1723dff4-9856-4d99-8a01-224a07bd3ecf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293329100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3293329100
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3772021252
Short name T621
Test name
Test status
Simulation time 138120129 ps
CPU time 0.74 seconds
Started Jun 21 06:12:13 PM PDT 24
Finished Jun 21 06:12:16 PM PDT 24
Peak memory 194620 kb
Host smart-cd4227de-aacc-4c6a-be0a-cac9df6b4010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772021252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3772021252
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1453659328
Short name T364
Test name
Test status
Simulation time 134939776 ps
CPU time 1.19 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:12:15 PM PDT 24
Peak memory 196144 kb
Host smart-503ce490-0c4f-4bc5-8579-883618f21fe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453659328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1453659328
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.902283851
Short name T216
Test name
Test status
Simulation time 51497735 ps
CPU time 2.17 seconds
Started Jun 21 06:12:13 PM PDT 24
Finished Jun 21 06:12:17 PM PDT 24
Peak memory 198148 kb
Host smart-17e6824a-2b48-48a2-a81a-50143a3031b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902283851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.902283851
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3405116484
Short name T617
Test name
Test status
Simulation time 126754167 ps
CPU time 2.84 seconds
Started Jun 21 06:12:13 PM PDT 24
Finished Jun 21 06:12:19 PM PDT 24
Peak memory 196600 kb
Host smart-c1bc864f-e94a-4dec-bbdb-efa0a1c8ed5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405116484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3405116484
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3229155753
Short name T336
Test name
Test status
Simulation time 24141073 ps
CPU time 0.92 seconds
Started Jun 21 06:12:03 PM PDT 24
Finished Jun 21 06:12:05 PM PDT 24
Peak memory 196564 kb
Host smart-123f2c59-24db-45d1-8789-57edcaa72bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229155753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3229155753
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2915594083
Short name T548
Test name
Test status
Simulation time 72134107 ps
CPU time 0.99 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:12:15 PM PDT 24
Peak memory 196068 kb
Host smart-db7cacf4-d3d9-49c3-9840-4146a3fedc7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915594083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2915594083
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2391545046
Short name T56
Test name
Test status
Simulation time 375868609 ps
CPU time 5.94 seconds
Started Jun 21 06:12:11 PM PDT 24
Finished Jun 21 06:12:19 PM PDT 24
Peak memory 197988 kb
Host smart-b835ff36-e717-419d-b32d-55c61a72a3d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391545046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2391545046
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2693241820
Short name T63
Test name
Test status
Simulation time 195433311 ps
CPU time 1.01 seconds
Started Jun 21 06:12:06 PM PDT 24
Finished Jun 21 06:12:09 PM PDT 24
Peak memory 195580 kb
Host smart-90232028-3175-4e2b-97fe-7fe13979c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693241820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2693241820
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1563111096
Short name T526
Test name
Test status
Simulation time 64551809 ps
CPU time 1.13 seconds
Started Jun 21 06:12:06 PM PDT 24
Finished Jun 21 06:12:10 PM PDT 24
Peak memory 195664 kb
Host smart-fe872309-d776-4152-95f9-a2f0056632d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563111096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1563111096
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3320098327
Short name T387
Test name
Test status
Simulation time 13811268553 ps
CPU time 187.36 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:15:21 PM PDT 24
Peak memory 191928 kb
Host smart-5750ec01-1686-4183-bd33-7a9f8d5f4b8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320098327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3320098327
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1053815552
Short name T424
Test name
Test status
Simulation time 22571617 ps
CPU time 0.57 seconds
Started Jun 21 06:12:15 PM PDT 24
Finished Jun 21 06:12:18 PM PDT 24
Peak memory 193828 kb
Host smart-0f7b620d-6a44-4b70-9499-4d0ae666d576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053815552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1053815552
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.386331367
Short name T685
Test name
Test status
Simulation time 23853196 ps
CPU time 0.74 seconds
Started Jun 21 06:12:15 PM PDT 24
Finished Jun 21 06:12:18 PM PDT 24
Peak memory 194028 kb
Host smart-90c5368e-3774-4225-8a80-3e0d7dac4182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386331367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.386331367
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1844699701
Short name T179
Test name
Test status
Simulation time 418812540 ps
CPU time 4.35 seconds
Started Jun 21 06:12:13 PM PDT 24
Finished Jun 21 06:12:20 PM PDT 24
Peak memory 196020 kb
Host smart-14a9c59c-2c2d-4ad4-9bd6-bf7f21c0e2fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844699701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1844699701
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2907894601
Short name T680
Test name
Test status
Simulation time 32908524 ps
CPU time 0.74 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:12:15 PM PDT 24
Peak memory 195464 kb
Host smart-7dcf64b1-8c1e-49b9-8d7d-8f358fb3254a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907894601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2907894601
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1976653513
Short name T268
Test name
Test status
Simulation time 31890016 ps
CPU time 0.77 seconds
Started Jun 21 06:12:13 PM PDT 24
Finished Jun 21 06:12:16 PM PDT 24
Peak memory 195304 kb
Host smart-5b096f2f-940d-4ff6-8d62-78c21705d8a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976653513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1976653513
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.1850758574
Short name T355
Test name
Test status
Simulation time 72939063 ps
CPU time 3.23 seconds
Started Jun 21 06:12:10 PM PDT 24
Finished Jun 21 06:12:14 PM PDT 24
Peak memory 196380 kb
Host smart-c7a76524-84f1-4a90-8a15-ac67adcbf7ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850758574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.1850758574
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3711666989
Short name T405
Test name
Test status
Simulation time 1191381737 ps
CPU time 2.4 seconds
Started Jun 21 06:12:14 PM PDT 24
Finished Jun 21 06:12:18 PM PDT 24
Peak memory 197036 kb
Host smart-423072ef-2cba-4ea4-be81-a9a7932bff16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711666989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3711666989
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2859727285
Short name T335
Test name
Test status
Simulation time 456478836 ps
CPU time 1.21 seconds
Started Jun 21 06:12:13 PM PDT 24
Finished Jun 21 06:12:17 PM PDT 24
Peak memory 197072 kb
Host smart-f007daf7-9867-495c-94f1-bd4d1d7e56ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859727285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2859727285
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1050389218
Short name T116
Test name
Test status
Simulation time 168888773 ps
CPU time 1.07 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:12:15 PM PDT 24
Peak memory 195872 kb
Host smart-cfa5f0b2-a604-494a-a3b6-83a93170eabe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050389218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1050389218
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4228234574
Short name T155
Test name
Test status
Simulation time 297469262 ps
CPU time 5.03 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:12:19 PM PDT 24
Peak memory 198008 kb
Host smart-469eafa4-e591-4ed2-9ce2-7cfd22da19e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228234574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4228234574
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2697101896
Short name T18
Test name
Test status
Simulation time 52039157 ps
CPU time 1.08 seconds
Started Jun 21 06:12:15 PM PDT 24
Finished Jun 21 06:12:19 PM PDT 24
Peak memory 196480 kb
Host smart-50feffb9-c8df-407b-9f1d-86f53797fc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697101896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2697101896
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3585207241
Short name T630
Test name
Test status
Simulation time 123206397 ps
CPU time 1.05 seconds
Started Jun 21 06:12:13 PM PDT 24
Finished Jun 21 06:12:16 PM PDT 24
Peak memory 195872 kb
Host smart-d051ebc3-22ef-4026-ab15-53c57a064005
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585207241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3585207241
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.3247204120
Short name T17
Test name
Test status
Simulation time 159369691948 ps
CPU time 226.43 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:16:00 PM PDT 24
Peak memory 198144 kb
Host smart-d162050b-ddd0-4966-9903-aa1d2bac43b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247204120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.3247204120
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.818257767
Short name T605
Test name
Test status
Simulation time 100893725453 ps
CPU time 1070.84 seconds
Started Jun 21 06:12:14 PM PDT 24
Finished Jun 21 06:30:08 PM PDT 24
Peak memory 198216 kb
Host smart-9797e512-5394-468f-aaa5-b63f91798927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=818257767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.818257767
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2236394411
Short name T437
Test name
Test status
Simulation time 31708193 ps
CPU time 0.58 seconds
Started Jun 21 06:09:43 PM PDT 24
Finished Jun 21 06:09:45 PM PDT 24
Peak memory 194540 kb
Host smart-ff81b6bc-0ddd-4748-a1c1-9fb08839231f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236394411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2236394411
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3164405488
Short name T273
Test name
Test status
Simulation time 27477095 ps
CPU time 0.85 seconds
Started Jun 21 06:09:43 PM PDT 24
Finished Jun 21 06:09:45 PM PDT 24
Peak memory 197156 kb
Host smart-83b6cad2-89dc-4756-833a-6a15b72b5e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164405488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3164405488
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.416463419
Short name T709
Test name
Test status
Simulation time 6765741212 ps
CPU time 18.7 seconds
Started Jun 21 06:09:41 PM PDT 24
Finished Jun 21 06:10:01 PM PDT 24
Peak memory 196848 kb
Host smart-8ac34fe6-b264-4b3d-a338-1a5500c0e48a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416463419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.416463419
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.4090936279
Short name T509
Test name
Test status
Simulation time 69608882 ps
CPU time 1.04 seconds
Started Jun 21 06:09:43 PM PDT 24
Finished Jun 21 06:09:45 PM PDT 24
Peak memory 196540 kb
Host smart-e8e9cb15-80f1-4b72-bbb2-221224f320fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090936279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.4090936279
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4000131328
Short name T450
Test name
Test status
Simulation time 33095333 ps
CPU time 0.8 seconds
Started Jun 21 06:09:43 PM PDT 24
Finished Jun 21 06:09:45 PM PDT 24
Peak memory 195336 kb
Host smart-235df72e-dfea-4fcc-b628-2548602322c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000131328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4000131328
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.435989873
Short name T55
Test name
Test status
Simulation time 70278310 ps
CPU time 2.8 seconds
Started Jun 21 06:09:40 PM PDT 24
Finished Jun 21 06:09:43 PM PDT 24
Peak memory 198092 kb
Host smart-8089a2c7-0684-4e72-8dda-5cdd7e15448a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435989873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.435989873
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.845663879
Short name T278
Test name
Test status
Simulation time 2211630912 ps
CPU time 2.62 seconds
Started Jun 21 06:09:40 PM PDT 24
Finished Jun 21 06:09:43 PM PDT 24
Peak memory 197348 kb
Host smart-30d90fd4-89fa-4f6f-812d-9d6131e19b3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845663879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.845663879
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3398656313
Short name T249
Test name
Test status
Simulation time 89356675 ps
CPU time 1.1 seconds
Started Jun 21 06:09:33 PM PDT 24
Finished Jun 21 06:09:35 PM PDT 24
Peak memory 196800 kb
Host smart-8429cafd-de47-4d1a-8337-89c2731841bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398656313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3398656313
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.67662868
Short name T106
Test name
Test status
Simulation time 125264138 ps
CPU time 1.24 seconds
Started Jun 21 06:09:41 PM PDT 24
Finished Jun 21 06:09:43 PM PDT 24
Peak memory 198104 kb
Host smart-59b1ba17-9eac-4d35-b23f-8500bd2eb4c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67662868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_p
ulldown.67662868
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1011761342
Short name T244
Test name
Test status
Simulation time 129074040 ps
CPU time 3.4 seconds
Started Jun 21 06:09:40 PM PDT 24
Finished Jun 21 06:09:44 PM PDT 24
Peak memory 198000 kb
Host smart-5169976d-b564-421e-adc8-45137369f770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011761342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1011761342
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3488500825
Short name T53
Test name
Test status
Simulation time 535146041 ps
CPU time 0.95 seconds
Started Jun 21 06:09:39 PM PDT 24
Finished Jun 21 06:09:41 PM PDT 24
Peak memory 214796 kb
Host smart-fe524528-5128-4ca1-a107-aa9c7fcb1225
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488500825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3488500825
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1141987338
Short name T289
Test name
Test status
Simulation time 384299210 ps
CPU time 0.87 seconds
Started Jun 21 06:09:32 PM PDT 24
Finished Jun 21 06:09:33 PM PDT 24
Peak memory 197024 kb
Host smart-61f1446a-f37b-46a7-9aae-85b637685ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141987338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1141987338
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3109896389
Short name T612
Test name
Test status
Simulation time 44876764 ps
CPU time 1.17 seconds
Started Jun 21 06:09:35 PM PDT 24
Finished Jun 21 06:09:37 PM PDT 24
Peak memory 195556 kb
Host smart-206e2d0f-3c2f-40b8-b521-caf0435cc70d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109896389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3109896389
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1395700797
Short name T239
Test name
Test status
Simulation time 8293782617 ps
CPU time 108.91 seconds
Started Jun 21 06:09:43 PM PDT 24
Finished Jun 21 06:11:33 PM PDT 24
Peak memory 198156 kb
Host smart-b91b5eea-2bad-4842-a188-dce17de321be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395700797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1395700797
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.669818872
Short name T615
Test name
Test status
Simulation time 116219269873 ps
CPU time 811.21 seconds
Started Jun 21 06:09:41 PM PDT 24
Finished Jun 21 06:23:13 PM PDT 24
Peak memory 198200 kb
Host smart-841841e4-b8b7-4f9e-9129-b51dfa39faef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=669818872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.669818872
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2589829929
Short name T60
Test name
Test status
Simulation time 18814106 ps
CPU time 0.58 seconds
Started Jun 21 06:12:20 PM PDT 24
Finished Jun 21 06:12:22 PM PDT 24
Peak memory 193820 kb
Host smart-0ba98790-7f54-4987-bfc7-f71d35fd6c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589829929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2589829929
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3208931526
Short name T514
Test name
Test status
Simulation time 20173757 ps
CPU time 0.62 seconds
Started Jun 21 06:12:19 PM PDT 24
Finished Jun 21 06:12:21 PM PDT 24
Peak memory 193960 kb
Host smart-e7f2f72f-a4ab-4310-8b98-52e2636e35d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208931526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3208931526
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2411661186
Short name T205
Test name
Test status
Simulation time 2775793213 ps
CPU time 21.99 seconds
Started Jun 21 06:12:18 PM PDT 24
Finished Jun 21 06:12:42 PM PDT 24
Peak memory 198152 kb
Host smart-eb0a6a4e-c8f3-4472-ab62-de6c27b34ce9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411661186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2411661186
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4011511735
Short name T357
Test name
Test status
Simulation time 95104604 ps
CPU time 0.74 seconds
Started Jun 21 06:12:20 PM PDT 24
Finished Jun 21 06:12:22 PM PDT 24
Peak memory 195852 kb
Host smart-2f590761-1cb7-4fed-be18-f154750a667f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011511735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4011511735
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1956851975
Short name T701
Test name
Test status
Simulation time 33160634 ps
CPU time 0.72 seconds
Started Jun 21 06:12:19 PM PDT 24
Finished Jun 21 06:12:21 PM PDT 24
Peak memory 194236 kb
Host smart-1cba167c-ac45-4704-9388-10e044c16231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956851975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1956851975
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3493147218
Short name T625
Test name
Test status
Simulation time 82787590 ps
CPU time 3.48 seconds
Started Jun 21 06:12:21 PM PDT 24
Finished Jun 21 06:12:25 PM PDT 24
Peak memory 198056 kb
Host smart-8893a2df-829d-4c80-80c8-d56764536311
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493147218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3493147218
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2632774423
Short name T345
Test name
Test status
Simulation time 307289315 ps
CPU time 3.05 seconds
Started Jun 21 06:12:20 PM PDT 24
Finished Jun 21 06:12:25 PM PDT 24
Peak memory 197316 kb
Host smart-b95249a9-afa9-4bbe-80b8-fd87a6d34038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632774423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2632774423
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2031571490
Short name T678
Test name
Test status
Simulation time 44987916 ps
CPU time 0.68 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:12:15 PM PDT 24
Peak memory 194984 kb
Host smart-3c6f2d17-5a07-425b-a87f-18f27d021da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031571490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2031571490
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2223488714
Short name T703
Test name
Test status
Simulation time 118205635 ps
CPU time 0.88 seconds
Started Jun 21 06:12:14 PM PDT 24
Finished Jun 21 06:12:17 PM PDT 24
Peak memory 195956 kb
Host smart-aad4445a-202d-4c6e-b107-0fcb70bea909
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223488714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2223488714
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.4158123585
Short name T627
Test name
Test status
Simulation time 641160835 ps
CPU time 3.52 seconds
Started Jun 21 06:12:21 PM PDT 24
Finished Jun 21 06:12:25 PM PDT 24
Peak memory 197984 kb
Host smart-0408360a-5c4e-45ff-be06-3ab64f4bb894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158123585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.4158123585
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1886472417
Short name T258
Test name
Test status
Simulation time 86585384 ps
CPU time 0.95 seconds
Started Jun 21 06:12:12 PM PDT 24
Finished Jun 21 06:12:15 PM PDT 24
Peak memory 195548 kb
Host smart-57524e07-7ac4-45c7-8036-e4f548ca79f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886472417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1886472417
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.1800122136
Short name T123
Test name
Test status
Simulation time 203752662 ps
CPU time 1.14 seconds
Started Jun 21 06:12:14 PM PDT 24
Finished Jun 21 06:12:18 PM PDT 24
Peak memory 195736 kb
Host smart-10e31c23-265a-4fd6-8838-2e22bd9a9070
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800122136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.1800122136
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3210551684
Short name T147
Test name
Test status
Simulation time 56157049279 ps
CPU time 201.15 seconds
Started Jun 21 06:12:19 PM PDT 24
Finished Jun 21 06:15:41 PM PDT 24
Peak memory 198104 kb
Host smart-cd175b54-1983-4da9-84f8-b18662ef9316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210551684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3210551684
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.742563825
Short name T70
Test name
Test status
Simulation time 23288559921 ps
CPU time 313.2 seconds
Started Jun 21 06:12:18 PM PDT 24
Finished Jun 21 06:17:33 PM PDT 24
Peak memory 198108 kb
Host smart-ad101d94-78cd-4251-81c8-d6cae7db2bdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=742563825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.742563825
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3775376205
Short name T406
Test name
Test status
Simulation time 37610616 ps
CPU time 0.58 seconds
Started Jun 21 06:12:19 PM PDT 24
Finished Jun 21 06:12:21 PM PDT 24
Peak memory 193936 kb
Host smart-6235d944-f1aa-4f41-85f7-ef08e8d28c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775376205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3775376205
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.3978779966
Short name T651
Test name
Test status
Simulation time 83737415 ps
CPU time 0.95 seconds
Started Jun 21 06:12:21 PM PDT 24
Finished Jun 21 06:12:23 PM PDT 24
Peak memory 196988 kb
Host smart-cf722a9e-2fd4-4dc0-9ae9-aff7cf4a9fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978779966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.3978779966
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3234168893
Short name T119
Test name
Test status
Simulation time 602236812 ps
CPU time 17.54 seconds
Started Jun 21 06:12:19 PM PDT 24
Finished Jun 21 06:12:38 PM PDT 24
Peak memory 196940 kb
Host smart-b308c9c5-ece8-4ef2-b5eb-18c235d292da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234168893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3234168893
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1661113392
Short name T533
Test name
Test status
Simulation time 740591080 ps
CPU time 0.94 seconds
Started Jun 21 06:12:21 PM PDT 24
Finished Jun 21 06:12:23 PM PDT 24
Peak memory 196728 kb
Host smart-17a1fc63-8acf-4ae6-ab9c-019f2131a0dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661113392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1661113392
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.2272524116
Short name T130
Test name
Test status
Simulation time 409887112 ps
CPU time 1.53 seconds
Started Jun 21 06:12:21 PM PDT 24
Finished Jun 21 06:12:24 PM PDT 24
Peak memory 197272 kb
Host smart-d8bda0d2-a183-47d3-8588-e9107dfd22c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272524116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.2272524116
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.93440173
Short name T113
Test name
Test status
Simulation time 174059234 ps
CPU time 3.42 seconds
Started Jun 21 06:12:20 PM PDT 24
Finished Jun 21 06:12:25 PM PDT 24
Peak memory 198060 kb
Host smart-dff2cb59-d772-4870-91e2-2e7f81feb883
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93440173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 41.gpio_intr_with_filter_rand_intr_event.93440173
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.2500436154
Short name T146
Test name
Test status
Simulation time 37266155 ps
CPU time 0.95 seconds
Started Jun 21 06:12:19 PM PDT 24
Finished Jun 21 06:12:21 PM PDT 24
Peak memory 195956 kb
Host smart-03f3f392-9eb6-4ffc-b1da-35accda29d78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500436154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.2500436154
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2833599325
Short name T306
Test name
Test status
Simulation time 135250948 ps
CPU time 0.96 seconds
Started Jun 21 06:12:21 PM PDT 24
Finished Jun 21 06:12:23 PM PDT 24
Peak memory 195836 kb
Host smart-84f0b403-52c9-4e10-9d1c-663d3009ab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833599325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2833599325
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3711769035
Short name T314
Test name
Test status
Simulation time 223958367 ps
CPU time 1.29 seconds
Started Jun 21 06:12:18 PM PDT 24
Finished Jun 21 06:12:21 PM PDT 24
Peak memory 198064 kb
Host smart-501ccd3f-ece7-4699-a428-88633da1787e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711769035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3711769035
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.213526208
Short name T693
Test name
Test status
Simulation time 262791041 ps
CPU time 1.5 seconds
Started Jun 21 06:12:18 PM PDT 24
Finished Jun 21 06:12:20 PM PDT 24
Peak memory 197996 kb
Host smart-f8eb42cc-0235-4dac-bfe7-d73f73effe58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213526208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.213526208
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.277557931
Short name T54
Test name
Test status
Simulation time 552722659 ps
CPU time 1.31 seconds
Started Jun 21 06:12:20 PM PDT 24
Finished Jun 21 06:12:23 PM PDT 24
Peak memory 196760 kb
Host smart-a7b3182d-7ede-46f6-a7cf-6439c4b7cd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277557931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.277557931
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3620461861
Short name T708
Test name
Test status
Simulation time 30895371 ps
CPU time 0.9 seconds
Started Jun 21 06:12:23 PM PDT 24
Finished Jun 21 06:12:25 PM PDT 24
Peak memory 196168 kb
Host smart-dedc26f5-0310-4581-8605-40cb41f11326
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620461861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3620461861
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.483690300
Short name T582
Test name
Test status
Simulation time 70048331136 ps
CPU time 193.08 seconds
Started Jun 21 06:12:18 PM PDT 24
Finished Jun 21 06:15:32 PM PDT 24
Peak memory 198212 kb
Host smart-95a66fe4-3ecd-4e83-b448-12486713436c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483690300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.483690300
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3152788630
Short name T61
Test name
Test status
Simulation time 15081548 ps
CPU time 0.6 seconds
Started Jun 21 06:12:40 PM PDT 24
Finished Jun 21 06:12:41 PM PDT 24
Peak memory 193808 kb
Host smart-fc419048-ac3e-4be8-a8b1-221edc648dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152788630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3152788630
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.1468045667
Short name T117
Test name
Test status
Simulation time 18788339 ps
CPU time 0.7 seconds
Started Jun 21 06:12:27 PM PDT 24
Finished Jun 21 06:12:28 PM PDT 24
Peak memory 194120 kb
Host smart-07cde956-0757-426a-b7e6-227a4fa2210d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468045667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.1468045667
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2356574921
Short name T438
Test name
Test status
Simulation time 1004377678 ps
CPU time 20.38 seconds
Started Jun 21 06:12:29 PM PDT 24
Finished Jun 21 06:12:50 PM PDT 24
Peak memory 196644 kb
Host smart-b7c895f5-bd56-4e5b-ba51-e9ec137d30df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356574921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2356574921
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3009755596
Short name T4
Test name
Test status
Simulation time 80886128 ps
CPU time 0.99 seconds
Started Jun 21 06:12:29 PM PDT 24
Finished Jun 21 06:12:31 PM PDT 24
Peak memory 197848 kb
Host smart-c2d602fc-479e-4934-80a9-63338e43c9d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009755596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3009755596
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3630827060
Short name T360
Test name
Test status
Simulation time 694984903 ps
CPU time 1.21 seconds
Started Jun 21 06:12:30 PM PDT 24
Finished Jun 21 06:12:32 PM PDT 24
Peak memory 195752 kb
Host smart-2ba4bed4-2cbb-4068-8aa3-764e6d2cd86b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630827060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3630827060
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3170355362
Short name T475
Test name
Test status
Simulation time 1232356437 ps
CPU time 3.65 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:12:33 PM PDT 24
Peak memory 198088 kb
Host smart-fa908752-5f06-41ca-9353-64a982dd14ed
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170355362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3170355362
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2992334217
Short name T124
Test name
Test status
Simulation time 670979713 ps
CPU time 3.29 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:12:32 PM PDT 24
Peak memory 197124 kb
Host smart-83dafb6f-79ae-4b6a-b710-a543ded92332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992334217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2992334217
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2756406409
Short name T653
Test name
Test status
Simulation time 192323861 ps
CPU time 0.75 seconds
Started Jun 21 06:12:29 PM PDT 24
Finished Jun 21 06:12:31 PM PDT 24
Peak memory 195392 kb
Host smart-a06b115e-603b-49a2-8428-58e15897ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756406409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2756406409
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3703796507
Short name T359
Test name
Test status
Simulation time 54397446 ps
CPU time 0.84 seconds
Started Jun 21 06:12:32 PM PDT 24
Finished Jun 21 06:12:34 PM PDT 24
Peak memory 196588 kb
Host smart-2ca7f877-b93a-4cd5-8d91-80ef528893b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703796507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3703796507
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2661306275
Short name T493
Test name
Test status
Simulation time 372289513 ps
CPU time 4.18 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:12:33 PM PDT 24
Peak memory 197968 kb
Host smart-eb351e4f-cbb9-4a43-bb98-ebd676e192fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661306275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2661306275
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3148625649
Short name T433
Test name
Test status
Simulation time 116009134 ps
CPU time 1.17 seconds
Started Jun 21 06:12:19 PM PDT 24
Finished Jun 21 06:12:22 PM PDT 24
Peak memory 195832 kb
Host smart-66e2a5b6-2731-4d36-af3f-7315f3582182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148625649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3148625649
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1187360254
Short name T600
Test name
Test status
Simulation time 148400948 ps
CPU time 0.97 seconds
Started Jun 21 06:12:30 PM PDT 24
Finished Jun 21 06:12:32 PM PDT 24
Peak memory 196240 kb
Host smart-ef5f3630-64ba-4eb9-8262-8c506db07811
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187360254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1187360254
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3416582591
Short name T352
Test name
Test status
Simulation time 7100252326 ps
CPU time 14.28 seconds
Started Jun 21 06:12:30 PM PDT 24
Finished Jun 21 06:12:45 PM PDT 24
Peak memory 198072 kb
Host smart-17eef705-edec-4743-8a68-f66c7549c80c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416582591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3416582591
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1593730949
Short name T66
Test name
Test status
Simulation time 86490705108 ps
CPU time 252.58 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:16:41 PM PDT 24
Peak memory 206356 kb
Host smart-30a23a9e-3fda-4c7c-835a-594afce7a48a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1593730949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1593730949
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.4024098248
Short name T99
Test name
Test status
Simulation time 69472069 ps
CPU time 0.66 seconds
Started Jun 21 06:12:39 PM PDT 24
Finished Jun 21 06:12:41 PM PDT 24
Peak memory 193856 kb
Host smart-2223bf2e-408b-4405-96ae-d322c6176096
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024098248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.4024098248
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.388739068
Short name T484
Test name
Test status
Simulation time 216187560 ps
CPU time 0.89 seconds
Started Jun 21 06:12:27 PM PDT 24
Finished Jun 21 06:12:28 PM PDT 24
Peak memory 195484 kb
Host smart-2f6d4388-6a53-4439-b08f-babbc324d9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388739068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.388739068
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1489990864
Short name T178
Test name
Test status
Simulation time 1138082937 ps
CPU time 15.15 seconds
Started Jun 21 06:12:32 PM PDT 24
Finished Jun 21 06:12:48 PM PDT 24
Peak memory 198040 kb
Host smart-94c8eb9c-6797-4ce2-8a99-5a0e3ad80fab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489990864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1489990864
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3902620740
Short name T299
Test name
Test status
Simulation time 1194893043 ps
CPU time 1 seconds
Started Jun 21 06:12:30 PM PDT 24
Finished Jun 21 06:12:32 PM PDT 24
Peak memory 196624 kb
Host smart-b7db9c44-9408-4edc-9aa8-703f4ee192fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902620740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3902620740
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.670992442
Short name T281
Test name
Test status
Simulation time 106013424 ps
CPU time 1.38 seconds
Started Jun 21 06:12:27 PM PDT 24
Finished Jun 21 06:12:29 PM PDT 24
Peak memory 198120 kb
Host smart-d2edb066-41d2-4f03-b26a-84472f0d9396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670992442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.670992442
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2482016406
Short name T370
Test name
Test status
Simulation time 28599163 ps
CPU time 1.22 seconds
Started Jun 21 06:12:30 PM PDT 24
Finished Jun 21 06:12:32 PM PDT 24
Peak memory 196376 kb
Host smart-ce52196d-d819-4d12-8d95-4a3de4599ab9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482016406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2482016406
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.4226390314
Short name T434
Test name
Test status
Simulation time 145343566 ps
CPU time 2.4 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:12:32 PM PDT 24
Peak memory 198112 kb
Host smart-c2f4c7cc-0474-4e3b-8bb3-1a5f8ef8201c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226390314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.4226390314
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3265282812
Short name T150
Test name
Test status
Simulation time 171066739 ps
CPU time 1.01 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:12:30 PM PDT 24
Peak memory 196016 kb
Host smart-6cf0f773-7c98-4510-a629-469e2fa390aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265282812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3265282812
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1911120841
Short name T308
Test name
Test status
Simulation time 70230094 ps
CPU time 1.33 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:12:31 PM PDT 24
Peak memory 197268 kb
Host smart-13b328ee-a3e9-4f33-b662-339b43af1a31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911120841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1911120841
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3068785178
Short name T511
Test name
Test status
Simulation time 272668964 ps
CPU time 4.7 seconds
Started Jun 21 06:12:29 PM PDT 24
Finished Jun 21 06:12:35 PM PDT 24
Peak memory 198004 kb
Host smart-0e7f0a02-15c8-44c0-8bed-c8911ba39e3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068785178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3068785178
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.3463151128
Short name T137
Test name
Test status
Simulation time 37751883 ps
CPU time 0.91 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:12:30 PM PDT 24
Peak memory 196240 kb
Host smart-68994956-0a40-4591-b755-05092360f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463151128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.3463151128
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.354691583
Short name T439
Test name
Test status
Simulation time 138102416 ps
CPU time 1.18 seconds
Started Jun 21 06:12:29 PM PDT 24
Finished Jun 21 06:12:31 PM PDT 24
Peak memory 196828 kb
Host smart-257bb35f-9d18-4a43-a370-cb655ac7b826
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354691583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.354691583
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.4148503060
Short name T659
Test name
Test status
Simulation time 45428256038 ps
CPU time 86.47 seconds
Started Jun 21 06:12:28 PM PDT 24
Finished Jun 21 06:13:56 PM PDT 24
Peak memory 198212 kb
Host smart-2a19d148-b54d-4540-b609-4fb7404872df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148503060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.4148503060
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.1892269086
Short name T684
Test name
Test status
Simulation time 331520468087 ps
CPU time 1755.51 seconds
Started Jun 21 06:12:36 PM PDT 24
Finished Jun 21 06:41:53 PM PDT 24
Peak memory 198204 kb
Host smart-6315a380-bd4e-40b3-ace8-a2e8822d429f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1892269086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.1892269086
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.334355233
Short name T386
Test name
Test status
Simulation time 49274765 ps
CPU time 0.62 seconds
Started Jun 21 06:12:34 PM PDT 24
Finished Jun 21 06:12:35 PM PDT 24
Peak memory 194092 kb
Host smart-71a1f428-a278-45c4-829a-045160f032c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334355233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.334355233
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.4116739284
Short name T195
Test name
Test status
Simulation time 40279846 ps
CPU time 0.82 seconds
Started Jun 21 06:12:37 PM PDT 24
Finished Jun 21 06:12:39 PM PDT 24
Peak memory 196028 kb
Host smart-71903f92-934a-45c7-8567-6cb4479da204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116739284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.4116739284
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3577197433
Short name T172
Test name
Test status
Simulation time 659725868 ps
CPU time 5.99 seconds
Started Jun 21 06:12:34 PM PDT 24
Finished Jun 21 06:12:41 PM PDT 24
Peak memory 196964 kb
Host smart-8be6a15e-f63a-4f8e-a564-d85368454284
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577197433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3577197433
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1789363732
Short name T121
Test name
Test status
Simulation time 661696152 ps
CPU time 1.1 seconds
Started Jun 21 06:12:38 PM PDT 24
Finished Jun 21 06:12:41 PM PDT 24
Peak memory 196984 kb
Host smart-e1d6aecb-fbd6-4354-bb62-91c456d038e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789363732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1789363732
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3066137172
Short name T688
Test name
Test status
Simulation time 129698348 ps
CPU time 1.18 seconds
Started Jun 21 06:12:37 PM PDT 24
Finished Jun 21 06:12:40 PM PDT 24
Peak memory 195824 kb
Host smart-8b22a9b1-64e2-4250-b41b-07c345e36fa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066137172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3066137172
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2486503482
Short name T591
Test name
Test status
Simulation time 260975531 ps
CPU time 3.32 seconds
Started Jun 21 06:12:37 PM PDT 24
Finished Jun 21 06:12:41 PM PDT 24
Peak memory 198092 kb
Host smart-5225deeb-8f85-49a0-9a24-4a5b494bc868
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486503482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2486503482
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4028324014
Short name T637
Test name
Test status
Simulation time 192249697 ps
CPU time 3.05 seconds
Started Jun 21 06:12:34 PM PDT 24
Finished Jun 21 06:12:38 PM PDT 24
Peak memory 198108 kb
Host smart-9db093f5-e652-4cd1-b2a5-920364688677
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028324014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4028324014
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.980305927
Short name T261
Test name
Test status
Simulation time 120943770 ps
CPU time 0.97 seconds
Started Jun 21 06:12:39 PM PDT 24
Finished Jun 21 06:12:41 PM PDT 24
Peak memory 195852 kb
Host smart-6fe5963e-d4f8-4cc7-ba27-13232066565c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980305927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.980305927
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3028664263
Short name T713
Test name
Test status
Simulation time 45976266 ps
CPU time 1.07 seconds
Started Jun 21 06:12:37 PM PDT 24
Finished Jun 21 06:12:39 PM PDT 24
Peak memory 195832 kb
Host smart-3afedb56-e19b-4161-9d11-1a2f20b35218
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028664263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3028664263
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_smoke.2061778206
Short name T421
Test name
Test status
Simulation time 118330887 ps
CPU time 1.08 seconds
Started Jun 21 06:12:34 PM PDT 24
Finished Jun 21 06:12:37 PM PDT 24
Peak memory 196456 kb
Host smart-f846a9e5-c1d3-4e37-8eef-119c1136abe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061778206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2061778206
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2264968
Short name T629
Test name
Test status
Simulation time 44540291 ps
CPU time 0.9 seconds
Started Jun 21 06:12:35 PM PDT 24
Finished Jun 21 06:12:37 PM PDT 24
Peak memory 195292 kb
Host smart-02f6f7da-2410-44db-9f83-c111af3258c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2264968
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1842628901
Short name T528
Test name
Test status
Simulation time 54432073743 ps
CPU time 219.55 seconds
Started Jun 21 06:12:35 PM PDT 24
Finished Jun 21 06:16:16 PM PDT 24
Peak memory 198296 kb
Host smart-368a81ea-d727-4d96-8d1b-438490addd5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842628901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1842628901
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.704812896
Short name T184
Test name
Test status
Simulation time 14987377 ps
CPU time 0.58 seconds
Started Jun 21 06:12:45 PM PDT 24
Finished Jun 21 06:12:47 PM PDT 24
Peak memory 193832 kb
Host smart-99745ec9-0f1d-42d5-94b0-2c178f9d06e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704812896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.704812896
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.3071566245
Short name T446
Test name
Test status
Simulation time 91385097 ps
CPU time 0.93 seconds
Started Jun 21 06:12:37 PM PDT 24
Finished Jun 21 06:12:39 PM PDT 24
Peak memory 196488 kb
Host smart-2c589572-c720-4c9f-885e-0e4fa1f11571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071566245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.3071566245
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1930711681
Short name T191
Test name
Test status
Simulation time 4884579781 ps
CPU time 16.4 seconds
Started Jun 21 06:12:35 PM PDT 24
Finished Jun 21 06:12:52 PM PDT 24
Peak memory 198156 kb
Host smart-b014229d-c426-4c1b-8214-c2098857d6d2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930711681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1930711681
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3177594864
Short name T402
Test name
Test status
Simulation time 133004444 ps
CPU time 1.08 seconds
Started Jun 21 06:12:42 PM PDT 24
Finished Jun 21 06:12:44 PM PDT 24
Peak memory 197804 kb
Host smart-cfd7cd0c-5cbb-4ea4-a21d-0b6e70b25636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177594864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3177594864
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.79686200
Short name T102
Test name
Test status
Simulation time 72103049 ps
CPU time 1.24 seconds
Started Jun 21 06:12:35 PM PDT 24
Finished Jun 21 06:12:37 PM PDT 24
Peak memory 196716 kb
Host smart-7e6e8a1d-b82e-4bac-9e9d-3f0f08866b4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79686200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.79686200
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3833180893
Short name T573
Test name
Test status
Simulation time 58686009 ps
CPU time 1.46 seconds
Started Jun 21 06:12:35 PM PDT 24
Finished Jun 21 06:12:38 PM PDT 24
Peak memory 196560 kb
Host smart-1471984a-b303-4b20-b626-c995c1020f70
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833180893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3833180893
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1565044146
Short name T312
Test name
Test status
Simulation time 598916889 ps
CPU time 2.22 seconds
Started Jun 21 06:12:34 PM PDT 24
Finished Jun 21 06:12:37 PM PDT 24
Peak memory 196604 kb
Host smart-7511dded-3651-47c8-8f29-13d5fb6b6d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565044146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1565044146
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1968715957
Short name T331
Test name
Test status
Simulation time 30612421 ps
CPU time 0.8 seconds
Started Jun 21 06:12:36 PM PDT 24
Finished Jun 21 06:12:38 PM PDT 24
Peak memory 195320 kb
Host smart-bb647d1e-b387-47be-9dcb-71e4ae4c5e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968715957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1968715957
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1801590197
Short name T521
Test name
Test status
Simulation time 167630756 ps
CPU time 0.94 seconds
Started Jun 21 06:12:37 PM PDT 24
Finished Jun 21 06:12:39 PM PDT 24
Peak memory 195956 kb
Host smart-708e6f15-3d42-49d6-8a8e-71d0b455a2e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801590197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1801590197
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3017648567
Short name T246
Test name
Test status
Simulation time 1203513476 ps
CPU time 5.04 seconds
Started Jun 21 06:12:44 PM PDT 24
Finished Jun 21 06:12:50 PM PDT 24
Peak memory 198000 kb
Host smart-8886c2ef-25bb-4b76-bd98-c81925fdcc11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017648567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3017648567
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2412639192
Short name T383
Test name
Test status
Simulation time 201294109 ps
CPU time 1.16 seconds
Started Jun 21 06:12:37 PM PDT 24
Finished Jun 21 06:12:39 PM PDT 24
Peak memory 196368 kb
Host smart-23e6adf0-b13f-460c-93a0-6d8bbec1c6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412639192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2412639192
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2691156255
Short name T658
Test name
Test status
Simulation time 50991265 ps
CPU time 1.34 seconds
Started Jun 21 06:12:34 PM PDT 24
Finished Jun 21 06:12:36 PM PDT 24
Peak memory 197992 kb
Host smart-edb7abb5-2351-4534-b65f-47deaa5d05fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691156255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2691156255
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.732850150
Short name T3
Test name
Test status
Simulation time 10969776192 ps
CPU time 65.34 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:13:50 PM PDT 24
Peak memory 198084 kb
Host smart-9549fe24-c5ae-4045-9e33-c203b8269d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732850150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.732850150
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2596597333
Short name T687
Test name
Test status
Simulation time 40874625 ps
CPU time 0.62 seconds
Started Jun 21 06:12:41 PM PDT 24
Finished Jun 21 06:12:42 PM PDT 24
Peak memory 194152 kb
Host smart-37607d60-002f-450b-887c-e2cdeb6e5859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596597333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2596597333
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.199595893
Short name T232
Test name
Test status
Simulation time 155804654 ps
CPU time 0.86 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:12:45 PM PDT 24
Peak memory 195416 kb
Host smart-c0d080ed-2d25-4668-8fb3-25e6046a3e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199595893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.199595893
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.1408724962
Short name T62
Test name
Test status
Simulation time 7370108738 ps
CPU time 12.34 seconds
Started Jun 21 06:12:44 PM PDT 24
Finished Jun 21 06:12:57 PM PDT 24
Peak memory 198080 kb
Host smart-20908d2a-1495-48e2-8f34-12f1e453b82e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408724962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.1408724962
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.576638697
Short name T644
Test name
Test status
Simulation time 62451184 ps
CPU time 0.91 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:12:46 PM PDT 24
Peak memory 196564 kb
Host smart-c0db014e-0009-4675-87b9-58935fac9f2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576638697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.576638697
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.4067490916
Short name T631
Test name
Test status
Simulation time 56744143 ps
CPU time 1.11 seconds
Started Jun 21 06:12:42 PM PDT 24
Finished Jun 21 06:12:44 PM PDT 24
Peak memory 195880 kb
Host smart-af096b13-da72-4034-998b-9852a11962ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067490916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.4067490916
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3609145185
Short name T338
Test name
Test status
Simulation time 69487983 ps
CPU time 2.82 seconds
Started Jun 21 06:12:42 PM PDT 24
Finished Jun 21 06:12:45 PM PDT 24
Peak memory 198164 kb
Host smart-07c814dd-60eb-47dc-915f-6f36b49d7d53
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609145185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3609145185
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1169980556
Short name T579
Test name
Test status
Simulation time 1863713996 ps
CPU time 2.79 seconds
Started Jun 21 06:12:41 PM PDT 24
Finished Jun 21 06:12:45 PM PDT 24
Peak memory 198096 kb
Host smart-5a6b4a15-53ad-44da-aa94-cc7e93d09474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169980556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1169980556
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.533496649
Short name T303
Test name
Test status
Simulation time 39638758 ps
CPU time 0.75 seconds
Started Jun 21 06:12:42 PM PDT 24
Finished Jun 21 06:12:44 PM PDT 24
Peak memory 196096 kb
Host smart-4e521c5e-6354-4a06-93e0-e81b5f7686b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533496649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.533496649
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3145312350
Short name T250
Test name
Test status
Simulation time 282552689 ps
CPU time 1.17 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:12:46 PM PDT 24
Peak memory 196832 kb
Host smart-b0bb3994-32b7-4105-b3b9-fda96f563142
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145312350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3145312350
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3233545585
Short name T173
Test name
Test status
Simulation time 384610166 ps
CPU time 6.27 seconds
Started Jun 21 06:12:45 PM PDT 24
Finished Jun 21 06:12:52 PM PDT 24
Peak memory 197896 kb
Host smart-f7ac17cb-fd33-42b1-8c97-f9ff8913515e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233545585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3233545585
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.4030536228
Short name T676
Test name
Test status
Simulation time 276920281 ps
CPU time 1.14 seconds
Started Jun 21 06:12:44 PM PDT 24
Finished Jun 21 06:12:47 PM PDT 24
Peak memory 195544 kb
Host smart-653e594c-304e-41a5-a033-516c66f51e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030536228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.4030536228
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.4115509605
Short name T654
Test name
Test status
Simulation time 85278127 ps
CPU time 0.81 seconds
Started Jun 21 06:12:41 PM PDT 24
Finished Jun 21 06:12:43 PM PDT 24
Peak memory 195356 kb
Host smart-8fabedf6-0993-461c-998f-c751178d1921
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115509605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.4115509605
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1302007445
Short name T500
Test name
Test status
Simulation time 64907489596 ps
CPU time 129.14 seconds
Started Jun 21 06:12:44 PM PDT 24
Finished Jun 21 06:14:54 PM PDT 24
Peak memory 198160 kb
Host smart-84f2d572-f672-4da3-b932-cb0a053b7ef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302007445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1302007445
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2266045500
Short name T307
Test name
Test status
Simulation time 27508917 ps
CPU time 0.62 seconds
Started Jun 21 06:12:49 PM PDT 24
Finished Jun 21 06:12:51 PM PDT 24
Peak memory 194736 kb
Host smart-ed5e7db9-905f-4d3d-abc1-26c283952699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266045500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2266045500
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.577265116
Short name T12
Test name
Test status
Simulation time 82778127 ps
CPU time 0.73 seconds
Started Jun 21 06:12:44 PM PDT 24
Finished Jun 21 06:12:46 PM PDT 24
Peak memory 194180 kb
Host smart-f5fe22ec-a7a8-4baf-96b5-7150eec65bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577265116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.577265116
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3638924510
Short name T634
Test name
Test status
Simulation time 7493055218 ps
CPU time 26.35 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:13:19 PM PDT 24
Peak memory 197096 kb
Host smart-109953ba-9f26-4ebc-a903-d3dd463df646
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638924510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3638924510
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.264245486
Short name T298
Test name
Test status
Simulation time 35351039 ps
CPU time 0.71 seconds
Started Jun 21 06:12:54 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 195204 kb
Host smart-b53c19a0-7bca-4412-b88e-881387c029c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264245486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.264245486
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1497067233
Short name T567
Test name
Test status
Simulation time 41592090 ps
CPU time 0.86 seconds
Started Jun 21 06:12:45 PM PDT 24
Finished Jun 21 06:12:47 PM PDT 24
Peak memory 196324 kb
Host smart-ebf12a97-a049-49e3-a924-56e4bc9c4d59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497067233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1497067233
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1303259199
Short name T285
Test name
Test status
Simulation time 51397648 ps
CPU time 2.07 seconds
Started Jun 21 06:12:42 PM PDT 24
Finished Jun 21 06:12:45 PM PDT 24
Peak memory 196504 kb
Host smart-6b2333b2-1426-4c98-843e-3db324958ca8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303259199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1303259199
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2742667407
Short name T201
Test name
Test status
Simulation time 286790118 ps
CPU time 2.86 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:12:47 PM PDT 24
Peak memory 198096 kb
Host smart-107184e2-2de8-418b-866b-87c0ab75b53e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742667407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2742667407
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.414806095
Short name T418
Test name
Test status
Simulation time 81110901 ps
CPU time 1.09 seconds
Started Jun 21 06:12:47 PM PDT 24
Finished Jun 21 06:12:49 PM PDT 24
Peak memory 196600 kb
Host smart-b10c71d0-d72e-4b97-badd-3bf30414af50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414806095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.414806095
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.874938285
Short name T71
Test name
Test status
Simulation time 68437503 ps
CPU time 1.39 seconds
Started Jun 21 06:12:42 PM PDT 24
Finished Jun 21 06:12:45 PM PDT 24
Peak memory 197096 kb
Host smart-535cfc22-d0c6-4bde-9e4e-0a0269a9f04d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874938285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.874938285
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2560175516
Short name T211
Test name
Test status
Simulation time 264941252 ps
CPU time 4.56 seconds
Started Jun 21 06:12:50 PM PDT 24
Finished Jun 21 06:12:55 PM PDT 24
Peak memory 198060 kb
Host smart-839b243f-7f16-49ba-b3d0-e2814bb21aed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560175516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2560175516
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.1396524856
Short name T431
Test name
Test status
Simulation time 70637125 ps
CPU time 1.4 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:12:46 PM PDT 24
Peak memory 196832 kb
Host smart-b0c5838d-930b-4fb9-8bfc-42fdfcc442e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396524856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.1396524856
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1675958435
Short name T453
Test name
Test status
Simulation time 31446064 ps
CPU time 0.92 seconds
Started Jun 21 06:12:43 PM PDT 24
Finished Jun 21 06:12:45 PM PDT 24
Peak memory 195180 kb
Host smart-a9156915-9dbe-4948-8af9-f60a84422b34
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675958435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1675958435
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.909986610
Short name T358
Test name
Test status
Simulation time 6049481165 ps
CPU time 186.36 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:15:59 PM PDT 24
Peak memory 198160 kb
Host smart-16143c25-df84-4f95-807c-813fc55344c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909986610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.909986610
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.822458502
Short name T694
Test name
Test status
Simulation time 34455928099 ps
CPU time 1077.03 seconds
Started Jun 21 06:12:53 PM PDT 24
Finished Jun 21 06:30:52 PM PDT 24
Peak memory 198092 kb
Host smart-6a6a1d00-e044-4563-b8e6-293497841247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=822458502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.822458502
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.838689519
Short name T610
Test name
Test status
Simulation time 29157245 ps
CPU time 0.59 seconds
Started Jun 21 06:12:53 PM PDT 24
Finished Jun 21 06:12:55 PM PDT 24
Peak memory 194532 kb
Host smart-a7c45e62-d17f-4aaf-abe3-c8372983d5b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838689519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.838689519
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.791150131
Short name T415
Test name
Test status
Simulation time 84099527 ps
CPU time 0.84 seconds
Started Jun 21 06:12:52 PM PDT 24
Finished Jun 21 06:12:55 PM PDT 24
Peak memory 195360 kb
Host smart-bc0e9a2a-9b22-4702-9a7f-d2273d103e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791150131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.791150131
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2894784418
Short name T428
Test name
Test status
Simulation time 1463108145 ps
CPU time 15.19 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:13:07 PM PDT 24
Peak memory 197032 kb
Host smart-a8449fa3-f1cd-4d26-a3e9-51369bc22398
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894784418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2894784418
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.205640682
Short name T532
Test name
Test status
Simulation time 87103582 ps
CPU time 1.1 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:12:55 PM PDT 24
Peak memory 196444 kb
Host smart-c6e2f6eb-b588-4e85-9153-bf2bba1262f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205640682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.205640682
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3348293845
Short name T643
Test name
Test status
Simulation time 42605323 ps
CPU time 1.24 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:12:54 PM PDT 24
Peak memory 196192 kb
Host smart-6d4bf045-123b-44c7-8297-195e54b5b966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348293845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3348293845
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1304659716
Short name T503
Test name
Test status
Simulation time 96938634 ps
CPU time 2.09 seconds
Started Jun 21 06:12:50 PM PDT 24
Finished Jun 21 06:12:53 PM PDT 24
Peak memory 198040 kb
Host smart-ab37c493-c32d-41a0-ba01-b3e071f1fee5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304659716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1304659716
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3397527518
Short name T639
Test name
Test status
Simulation time 559411656 ps
CPU time 2.86 seconds
Started Jun 21 06:12:52 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 197188 kb
Host smart-eed778c2-6993-411a-8a06-4f5ff7eb90b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397527518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3397527518
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2923907063
Short name T167
Test name
Test status
Simulation time 1028194825 ps
CPU time 1.34 seconds
Started Jun 21 06:12:54 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 197964 kb
Host smart-66b236e6-f3c2-4d18-9558-1610550ca0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923907063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2923907063
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.384300859
Short name T188
Test name
Test status
Simulation time 46417987 ps
CPU time 0.86 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:12:53 PM PDT 24
Peak memory 196040 kb
Host smart-a962f0ba-4178-482a-bb91-5e02f647dfc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384300859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.384300859
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3199222012
Short name T6
Test name
Test status
Simulation time 337156577 ps
CPU time 4.81 seconds
Started Jun 21 06:12:52 PM PDT 24
Finished Jun 21 06:12:59 PM PDT 24
Peak memory 197964 kb
Host smart-739c3d58-8ace-4c09-9d0f-8efd962ee0a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199222012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3199222012
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3584223582
Short name T608
Test name
Test status
Simulation time 73144166 ps
CPU time 1.33 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:12:54 PM PDT 24
Peak memory 195576 kb
Host smart-aeb945d8-6c2f-4739-a226-aef374735e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584223582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3584223582
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2316159886
Short name T547
Test name
Test status
Simulation time 246269582 ps
CPU time 1.24 seconds
Started Jun 21 06:12:50 PM PDT 24
Finished Jun 21 06:12:52 PM PDT 24
Peak memory 195752 kb
Host smart-60530aae-51f2-4f5b-b5d1-3ca6fe6361cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316159886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2316159886
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1278333327
Short name T196
Test name
Test status
Simulation time 16758605991 ps
CPU time 68.05 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:14:00 PM PDT 24
Peak memory 198140 kb
Host smart-e238c950-bd85-4b15-a062-5db9b6151d1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278333327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1278333327
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.4256272248
Short name T594
Test name
Test status
Simulation time 14641024 ps
CPU time 0.62 seconds
Started Jun 21 06:13:02 PM PDT 24
Finished Jun 21 06:13:03 PM PDT 24
Peak memory 193776 kb
Host smart-684dee06-6be4-4057-8da0-34b2b85868a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256272248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.4256272248
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.3484379985
Short name T143
Test name
Test status
Simulation time 41914826 ps
CPU time 0.84 seconds
Started Jun 21 06:12:54 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 195440 kb
Host smart-f7fa5646-b4e4-4d32-9a65-c0f72e9222f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484379985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.3484379985
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.740540627
Short name T412
Test name
Test status
Simulation time 1269042422 ps
CPU time 29.5 seconds
Started Jun 21 06:13:00 PM PDT 24
Finished Jun 21 06:13:30 PM PDT 24
Peak memory 198060 kb
Host smart-eb12198f-909c-4831-aafe-6bb84b01f4b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740540627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.740540627
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1744716202
Short name T9
Test name
Test status
Simulation time 327467465 ps
CPU time 0.98 seconds
Started Jun 21 06:12:58 PM PDT 24
Finished Jun 21 06:13:00 PM PDT 24
Peak memory 197184 kb
Host smart-ca2c370e-c766-434c-81a9-2645a1d038e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744716202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1744716202
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.2366859049
Short name T296
Test name
Test status
Simulation time 63348634 ps
CPU time 1.08 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:12:54 PM PDT 24
Peak memory 196712 kb
Host smart-b68155d2-2092-4b85-afef-a3c0f43eb10f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366859049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.2366859049
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1299749039
Short name T502
Test name
Test status
Simulation time 48408106 ps
CPU time 1.23 seconds
Started Jun 21 06:12:50 PM PDT 24
Finished Jun 21 06:12:52 PM PDT 24
Peak memory 197216 kb
Host smart-c5a5ca82-4518-4a44-ad5a-3ee5f9f87261
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299749039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1299749039
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.436002660
Short name T570
Test name
Test status
Simulation time 255707047 ps
CPU time 1.53 seconds
Started Jun 21 06:12:52 PM PDT 24
Finished Jun 21 06:12:55 PM PDT 24
Peak memory 195828 kb
Host smart-f088603d-9c88-45bf-8a8a-8bf7f1b32bd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436002660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
436002660
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3056778814
Short name T225
Test name
Test status
Simulation time 127776672 ps
CPU time 1.07 seconds
Started Jun 21 06:12:53 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 196056 kb
Host smart-7d4b2d9d-0184-47b5-ac40-73e993927361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056778814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3056778814
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3610436043
Short name T279
Test name
Test status
Simulation time 66974755 ps
CPU time 0.78 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:12:53 PM PDT 24
Peak memory 195368 kb
Host smart-1308ea0c-cb78-4d31-afb3-3b0f2e7860f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610436043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3610436043
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1729538427
Short name T640
Test name
Test status
Simulation time 369675824 ps
CPU time 4.73 seconds
Started Jun 21 06:12:59 PM PDT 24
Finished Jun 21 06:13:04 PM PDT 24
Peak memory 198124 kb
Host smart-77832a85-dae8-4206-b4d1-10f50233023c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729538427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1729538427
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1687952333
Short name T606
Test name
Test status
Simulation time 58578615 ps
CPU time 1.11 seconds
Started Jun 21 06:12:54 PM PDT 24
Finished Jun 21 06:12:56 PM PDT 24
Peak memory 195736 kb
Host smart-68470ba5-27b2-4da5-ba16-12ee8f549704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687952333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1687952333
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3989969409
Short name T141
Test name
Test status
Simulation time 122363699 ps
CPU time 0.98 seconds
Started Jun 21 06:12:51 PM PDT 24
Finished Jun 21 06:12:53 PM PDT 24
Peak memory 195520 kb
Host smart-edf68b87-a173-49d8-a1ff-c4cc2b9898d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989969409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3989969409
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2970478012
Short name T189
Test name
Test status
Simulation time 33142244127 ps
CPU time 94.51 seconds
Started Jun 21 06:13:01 PM PDT 24
Finished Jun 21 06:14:36 PM PDT 24
Peak memory 198076 kb
Host smart-ba2ac09b-b1de-4295-ae56-7c2037f4b777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970478012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2970478012
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2581503617
Short name T29
Test name
Test status
Simulation time 14214762 ps
CPU time 0.57 seconds
Started Jun 21 06:09:49 PM PDT 24
Finished Jun 21 06:09:50 PM PDT 24
Peak memory 193844 kb
Host smart-02c07990-83e6-4369-8c3a-9c451e6e2acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581503617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2581503617
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2545168798
Short name T477
Test name
Test status
Simulation time 25009238 ps
CPU time 0.91 seconds
Started Jun 21 06:09:44 PM PDT 24
Finished Jun 21 06:09:46 PM PDT 24
Peak memory 195460 kb
Host smart-288b5290-7cb2-4550-a150-63a339e07c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545168798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2545168798
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.466811661
Short name T341
Test name
Test status
Simulation time 1397045301 ps
CPU time 18.3 seconds
Started Jun 21 06:09:50 PM PDT 24
Finished Jun 21 06:10:09 PM PDT 24
Peak memory 196996 kb
Host smart-23e149d4-36bc-492e-9c9c-06f3ae00cce3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466811661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress
.466811661
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1282067390
Short name T21
Test name
Test status
Simulation time 92425091 ps
CPU time 0.78 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:09:49 PM PDT 24
Peak memory 195896 kb
Host smart-3e610dd2-1353-4c0f-98d2-70f671d186d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282067390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1282067390
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.550401674
Short name T551
Test name
Test status
Simulation time 23231765 ps
CPU time 0.8 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:09:49 PM PDT 24
Peak memory 195580 kb
Host smart-4503423a-dd76-40b3-b692-9cde307383f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550401674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.550401674
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.974536176
Short name T603
Test name
Test status
Simulation time 361652786 ps
CPU time 3.43 seconds
Started Jun 21 06:09:48 PM PDT 24
Finished Jun 21 06:09:52 PM PDT 24
Peak memory 198160 kb
Host smart-bfd564f3-65fc-489f-8f29-7099999ff973
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974536176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.974536176
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.301194724
Short name T248
Test name
Test status
Simulation time 83501889 ps
CPU time 2.5 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:09:50 PM PDT 24
Peak memory 197268 kb
Host smart-a8c290db-519a-4a27-acfd-1d174bd3385d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301194724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.301194724
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3329252080
Short name T343
Test name
Test status
Simulation time 61822087 ps
CPU time 0.86 seconds
Started Jun 21 06:09:40 PM PDT 24
Finished Jun 21 06:09:41 PM PDT 24
Peak memory 195368 kb
Host smart-ea343741-dc8a-408f-900a-ab71d271a26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329252080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3329252080
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3737692976
Short name T607
Test name
Test status
Simulation time 583763144 ps
CPU time 1.28 seconds
Started Jun 21 06:09:39 PM PDT 24
Finished Jun 21 06:09:41 PM PDT 24
Peak memory 198008 kb
Host smart-e211bab0-868f-477b-a3b3-e4f14cb36c1a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737692976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3737692976
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3655234428
Short name T235
Test name
Test status
Simulation time 152197123 ps
CPU time 2.07 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:09:51 PM PDT 24
Peak memory 198020 kb
Host smart-9aa7f916-8c74-48d4-94b9-647b1a43e680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655234428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3655234428
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1745994969
Short name T134
Test name
Test status
Simulation time 187445307 ps
CPU time 1.24 seconds
Started Jun 21 06:09:40 PM PDT 24
Finished Jun 21 06:09:42 PM PDT 24
Peak memory 197000 kb
Host smart-1bcae2ee-a028-41da-8aae-54a2e4a09c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745994969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1745994969
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3631300550
Short name T348
Test name
Test status
Simulation time 39565486 ps
CPU time 1.13 seconds
Started Jun 21 06:09:42 PM PDT 24
Finished Jun 21 06:09:43 PM PDT 24
Peak memory 195820 kb
Host smart-b70a80f2-32bd-49a2-bd5b-3e4f0bf75f19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631300550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3631300550
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2451178657
Short name T2
Test name
Test status
Simulation time 26288438570 ps
CPU time 67.81 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:10:56 PM PDT 24
Peak memory 198140 kb
Host smart-cf254f1c-4cde-427f-aa8c-fd52a03201d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451178657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2451178657
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.3911978847
Short name T577
Test name
Test status
Simulation time 22059604 ps
CPU time 0.56 seconds
Started Jun 21 06:09:56 PM PDT 24
Finished Jun 21 06:09:57 PM PDT 24
Peak memory 194528 kb
Host smart-c5331155-3fe5-4fb7-94de-2b5087f825b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911978847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.3911978847
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2326323796
Short name T242
Test name
Test status
Simulation time 32494824 ps
CPU time 0.62 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:09:49 PM PDT 24
Peak memory 193800 kb
Host smart-c45aae04-a9dc-4e9a-be90-fed9c40403d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326323796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2326323796
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3485623671
Short name T218
Test name
Test status
Simulation time 672522750 ps
CPU time 8.72 seconds
Started Jun 21 06:09:49 PM PDT 24
Finished Jun 21 06:09:59 PM PDT 24
Peak memory 196888 kb
Host smart-4ae4c4ee-61b1-40a5-9399-5e9450b76c8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485623671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3485623671
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1188480293
Short name T525
Test name
Test status
Simulation time 61810428 ps
CPU time 0.85 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:09:57 PM PDT 24
Peak memory 195860 kb
Host smart-91f68d00-353a-4508-a2a0-4fa666d71441
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188480293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1188480293
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3498981391
Short name T284
Test name
Test status
Simulation time 195324036 ps
CPU time 1.31 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:09:50 PM PDT 24
Peak memory 195884 kb
Host smart-91a10da6-7afc-4435-905a-04c7055e152b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498981391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3498981391
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.772534970
Short name T697
Test name
Test status
Simulation time 77929223 ps
CPU time 3.1 seconds
Started Jun 21 06:09:51 PM PDT 24
Finished Jun 21 06:09:54 PM PDT 24
Peak memory 198140 kb
Host smart-0c9c4a81-4a31-4188-9203-a6605c953c87
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772534970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.772534970
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2307633363
Short name T505
Test name
Test status
Simulation time 86096867 ps
CPU time 2.67 seconds
Started Jun 21 06:09:51 PM PDT 24
Finished Jun 21 06:09:54 PM PDT 24
Peak memory 197252 kb
Host smart-aa9a9f70-1f5a-4728-9a22-44a10153352e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307633363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2307633363
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3635400396
Short name T616
Test name
Test status
Simulation time 45558574 ps
CPU time 1.17 seconds
Started Jun 21 06:09:53 PM PDT 24
Finished Jun 21 06:09:54 PM PDT 24
Peak memory 196896 kb
Host smart-009f874b-04e1-4a96-84dd-e4a92689c8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635400396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3635400396
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3059369914
Short name T403
Test name
Test status
Simulation time 61822317 ps
CPU time 1.28 seconds
Started Jun 21 06:09:47 PM PDT 24
Finished Jun 21 06:09:50 PM PDT 24
Peak memory 197124 kb
Host smart-4ba14625-e638-4d0c-a329-f26c1663a6c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059369914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3059369914
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.672448020
Short name T23
Test name
Test status
Simulation time 1313353775 ps
CPU time 4.01 seconds
Started Jun 21 06:09:48 PM PDT 24
Finished Jun 21 06:09:53 PM PDT 24
Peak memory 198096 kb
Host smart-ba690579-4305-4677-a118-87845161e42e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672448020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.672448020
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3210116940
Short name T473
Test name
Test status
Simulation time 51068645 ps
CPU time 1.37 seconds
Started Jun 21 06:09:49 PM PDT 24
Finished Jun 21 06:09:52 PM PDT 24
Peak memory 196780 kb
Host smart-a6996b1c-9707-43eb-aa08-2863a4dbea7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210116940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3210116940
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1761386263
Short name T127
Test name
Test status
Simulation time 160612454 ps
CPU time 1.25 seconds
Started Jun 21 06:09:49 PM PDT 24
Finished Jun 21 06:09:51 PM PDT 24
Peak memory 196732 kb
Host smart-4833c2a9-55b7-4ae2-b133-579f097af551
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761386263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1761386263
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.4203219459
Short name T200
Test name
Test status
Simulation time 3005134204 ps
CPU time 77.82 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:11:13 PM PDT 24
Peak memory 198124 kb
Host smart-4c0d32d5-8f38-488f-a2b4-be9bf0610c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203219459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.4203219459
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2575584465
Short name T496
Test name
Test status
Simulation time 115436274914 ps
CPU time 2641.68 seconds
Started Jun 21 06:09:56 PM PDT 24
Finished Jun 21 06:53:59 PM PDT 24
Peak memory 198252 kb
Host smart-b2357023-ca8a-422a-90bb-ae469f2ecdf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2575584465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2575584465
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3923565222
Short name T181
Test name
Test status
Simulation time 12170830 ps
CPU time 0.56 seconds
Started Jun 21 06:09:59 PM PDT 24
Finished Jun 21 06:10:00 PM PDT 24
Peak memory 193780 kb
Host smart-cfabcd35-b4e6-4478-b301-9b60e58d40a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923565222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3923565222
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.530727306
Short name T531
Test name
Test status
Simulation time 157829275 ps
CPU time 0.98 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:09:58 PM PDT 24
Peak memory 197224 kb
Host smart-cdce3fde-7b12-4f95-b97d-db0bfc658231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530727306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.530727306
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1915404628
Short name T444
Test name
Test status
Simulation time 930110426 ps
CPU time 22.03 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:10:17 PM PDT 24
Peak memory 196512 kb
Host smart-a4147585-479c-47fe-9c3f-e90c59e7a686
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915404628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1915404628
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.1880060594
Short name T586
Test name
Test status
Simulation time 60608216 ps
CPU time 0.61 seconds
Started Jun 21 06:09:57 PM PDT 24
Finished Jun 21 06:09:58 PM PDT 24
Peak memory 194252 kb
Host smart-aa8fe1e1-b99f-40ec-8770-f613afe77d4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880060594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.1880060594
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.248526428
Short name T461
Test name
Test status
Simulation time 167233413 ps
CPU time 1.08 seconds
Started Jun 21 06:09:56 PM PDT 24
Finished Jun 21 06:09:58 PM PDT 24
Peak memory 196004 kb
Host smart-a9385745-1b13-4dac-a424-d21bf33201ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248526428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.248526428
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1715680796
Short name T302
Test name
Test status
Simulation time 78937393 ps
CPU time 3.17 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:09:59 PM PDT 24
Peak memory 198188 kb
Host smart-1f905c27-a416-409e-97b1-20b38035b350
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715680796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1715680796
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3687744959
Short name T568
Test name
Test status
Simulation time 91921663 ps
CPU time 2.22 seconds
Started Jun 21 06:09:59 PM PDT 24
Finished Jun 21 06:10:02 PM PDT 24
Peak memory 197220 kb
Host smart-a1b7586d-bf3b-41c1-bb38-be18a49f0f9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687744959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3687744959
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3202864466
Short name T587
Test name
Test status
Simulation time 386628184 ps
CPU time 1.26 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:09:58 PM PDT 24
Peak memory 195872 kb
Host smart-b0a1a6cc-3328-4a65-a933-039b3b317ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202864466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3202864466
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1597850827
Short name T170
Test name
Test status
Simulation time 21400656 ps
CPU time 0.86 seconds
Started Jun 21 06:09:56 PM PDT 24
Finished Jun 21 06:09:58 PM PDT 24
Peak memory 195832 kb
Host smart-13f90749-af5d-4c97-bcc1-279f4662b2ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597850827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1597850827
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1222214317
Short name T320
Test name
Test status
Simulation time 330733934 ps
CPU time 4.17 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:10:00 PM PDT 24
Peak memory 198052 kb
Host smart-6efd9a39-f150-48c0-8c26-c9072a7d3444
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222214317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1222214317
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.354889476
Short name T135
Test name
Test status
Simulation time 86682904 ps
CPU time 1.45 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:09:57 PM PDT 24
Peak memory 196768 kb
Host smart-a4f617a7-68c3-48a0-be18-4c4d3a980069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354889476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.354889476
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1483525241
Short name T133
Test name
Test status
Simulation time 28356799 ps
CPU time 0.89 seconds
Started Jun 21 06:09:54 PM PDT 24
Finished Jun 21 06:09:56 PM PDT 24
Peak memory 195404 kb
Host smart-3a6cf78e-fb83-4879-b590-460c0ada1e97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483525241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1483525241
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.932291174
Short name T32
Test name
Test status
Simulation time 15034962662 ps
CPU time 226.46 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:13:42 PM PDT 24
Peak memory 198312 kb
Host smart-6a743a28-36a3-4025-8a3a-d602925cb36c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932291174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.932291174
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.2259634104
Short name T67
Test name
Test status
Simulation time 30128182092 ps
CPU time 928.66 seconds
Started Jun 21 06:09:58 PM PDT 24
Finished Jun 21 06:25:27 PM PDT 24
Peak memory 198220 kb
Host smart-21b6b2fe-b4e0-4f3b-b66f-35f883749b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2259634104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.2259634104
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.356532317
Short name T329
Test name
Test status
Simulation time 28380824 ps
CPU time 0.61 seconds
Started Jun 21 06:10:02 PM PDT 24
Finished Jun 21 06:10:04 PM PDT 24
Peak memory 194048 kb
Host smart-3df723f1-5f98-4300-b1f9-8c8169818167
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356532317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.356532317
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.381337099
Short name T350
Test name
Test status
Simulation time 186471277 ps
CPU time 0.89 seconds
Started Jun 21 06:09:56 PM PDT 24
Finished Jun 21 06:09:58 PM PDT 24
Peak memory 197092 kb
Host smart-04e6ffc4-05f5-4f38-9d51-3886c3101038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381337099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.381337099
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3612353002
Short name T26
Test name
Test status
Simulation time 2193940151 ps
CPU time 28.87 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:10:25 PM PDT 24
Peak memory 198020 kb
Host smart-0318275f-3060-4465-a733-bce5fe76f432
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612353002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3612353002
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1963072489
Short name T388
Test name
Test status
Simulation time 230099313 ps
CPU time 1.08 seconds
Started Jun 21 06:09:58 PM PDT 24
Finished Jun 21 06:10:00 PM PDT 24
Peak memory 197848 kb
Host smart-a6c069d6-8758-4ec5-817e-b8446cad759f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963072489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1963072489
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2570320091
Short name T459
Test name
Test status
Simulation time 44812635 ps
CPU time 1.04 seconds
Started Jun 21 06:09:59 PM PDT 24
Finished Jun 21 06:10:00 PM PDT 24
Peak memory 196840 kb
Host smart-d91b006f-8567-4131-8cf4-4078d878e036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570320091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2570320091
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.66876549
Short name T404
Test name
Test status
Simulation time 311921622 ps
CPU time 3.75 seconds
Started Jun 21 06:09:55 PM PDT 24
Finished Jun 21 06:10:00 PM PDT 24
Peak memory 198176 kb
Host smart-370d5211-01f1-49ca-b09e-e0cc658c54bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66876549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.gpio_intr_with_filter_rand_intr_event.66876549
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.2808563437
Short name T206
Test name
Test status
Simulation time 107731063 ps
CPU time 1.04 seconds
Started Jun 21 06:09:59 PM PDT 24
Finished Jun 21 06:10:01 PM PDT 24
Peak memory 195560 kb
Host smart-e371b6cd-e121-41ba-b8db-be7a73ad24af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808563437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
2808563437
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.3086563103
Short name T501
Test name
Test status
Simulation time 50480593 ps
CPU time 1.23 seconds
Started Jun 21 06:09:56 PM PDT 24
Finished Jun 21 06:09:59 PM PDT 24
Peak memory 195888 kb
Host smart-874db744-0d31-4334-9135-4b4da39abd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086563103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.3086563103
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.247175249
Short name T286
Test name
Test status
Simulation time 111458919 ps
CPU time 1.32 seconds
Started Jun 21 06:09:56 PM PDT 24
Finished Jun 21 06:09:59 PM PDT 24
Peak memory 195872 kb
Host smart-de5728e8-df36-42c7-a970-387eb4536709
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247175249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.247175249
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2670414684
Short name T390
Test name
Test status
Simulation time 236287911 ps
CPU time 2.93 seconds
Started Jun 21 06:09:54 PM PDT 24
Finished Jun 21 06:09:58 PM PDT 24
Peak memory 198004 kb
Host smart-364fdf21-e70c-45c5-8f33-e596f1130316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670414684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2670414684
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.4100198183
Short name T219
Test name
Test status
Simulation time 312137882 ps
CPU time 1.53 seconds
Started Jun 21 06:09:59 PM PDT 24
Finished Jun 21 06:10:01 PM PDT 24
Peak memory 196740 kb
Host smart-7524b369-57b2-4569-b312-8d85bd669857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100198183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.4100198183
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2835261825
Short name T259
Test name
Test status
Simulation time 45246644 ps
CPU time 0.87 seconds
Started Jun 21 06:09:54 PM PDT 24
Finished Jun 21 06:09:56 PM PDT 24
Peak memory 196228 kb
Host smart-66ca76a0-2fc8-438e-a0fb-3e59ef344965
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835261825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2835261825
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2091750310
Short name T122
Test name
Test status
Simulation time 14356306098 ps
CPU time 49.57 seconds
Started Jun 21 06:10:05 PM PDT 24
Finished Jun 21 06:10:55 PM PDT 24
Peak memory 198144 kb
Host smart-15958ea6-4064-4f5f-8b0b-d26e11349cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091750310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2091750310
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2887530763
Short name T545
Test name
Test status
Simulation time 48902090939 ps
CPU time 584.94 seconds
Started Jun 21 06:10:06 PM PDT 24
Finished Jun 21 06:19:51 PM PDT 24
Peak memory 198188 kb
Host smart-a404486c-7d5e-4a57-8eb3-7432919fa537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2887530763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2887530763
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3877282730
Short name T552
Test name
Test status
Simulation time 28536508 ps
CPU time 0.6 seconds
Started Jun 21 06:10:14 PM PDT 24
Finished Jun 21 06:10:16 PM PDT 24
Peak memory 194080 kb
Host smart-219d2cbd-5229-4306-9086-c99e383508e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877282730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3877282730
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2625880836
Short name T199
Test name
Test status
Simulation time 30898803 ps
CPU time 1.05 seconds
Started Jun 21 06:10:01 PM PDT 24
Finished Jun 21 06:10:03 PM PDT 24
Peak memory 196476 kb
Host smart-f47fcc9e-ccdb-4b41-84ce-46b7ddccc7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625880836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2625880836
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1463389693
Short name T323
Test name
Test status
Simulation time 3582102303 ps
CPU time 25.31 seconds
Started Jun 21 06:10:03 PM PDT 24
Finished Jun 21 06:10:29 PM PDT 24
Peak memory 196896 kb
Host smart-30edae13-d49f-4761-8c25-458d72c8433a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463389693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1463389693
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3597357116
Short name T252
Test name
Test status
Simulation time 110391267 ps
CPU time 0.73 seconds
Started Jun 21 06:10:02 PM PDT 24
Finished Jun 21 06:10:03 PM PDT 24
Peak memory 195332 kb
Host smart-7b4877c0-a1bf-4853-8894-c098f0cafa50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597357116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3597357116
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1163819126
Short name T214
Test name
Test status
Simulation time 74568567 ps
CPU time 0.83 seconds
Started Jun 21 06:10:03 PM PDT 24
Finished Jun 21 06:10:04 PM PDT 24
Peak memory 196072 kb
Host smart-75ebe46f-708e-4952-8696-de0e4ed45b64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163819126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1163819126
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.4003849394
Short name T193
Test name
Test status
Simulation time 83683554 ps
CPU time 3.26 seconds
Started Jun 21 06:10:04 PM PDT 24
Finished Jun 21 06:10:08 PM PDT 24
Peak memory 198168 kb
Host smart-719db923-c870-4820-88a5-5df74c616f2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003849394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.4003849394
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2229112430
Short name T638
Test name
Test status
Simulation time 36084067 ps
CPU time 1.29 seconds
Started Jun 21 06:10:03 PM PDT 24
Finished Jun 21 06:10:06 PM PDT 24
Peak memory 196816 kb
Host smart-4a669363-f5ef-4f8e-b30a-243417d037dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229112430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2229112430
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.249196096
Short name T601
Test name
Test status
Simulation time 96367773 ps
CPU time 1.08 seconds
Started Jun 21 06:10:05 PM PDT 24
Finished Jun 21 06:10:07 PM PDT 24
Peak memory 196744 kb
Host smart-fe16cfbc-9072-43c9-b103-6864ac4ae3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249196096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.249196096
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1616151791
Short name T635
Test name
Test status
Simulation time 105570204 ps
CPU time 1.37 seconds
Started Jun 21 06:10:02 PM PDT 24
Finished Jun 21 06:10:04 PM PDT 24
Peak memory 197148 kb
Host smart-cd4f6f8f-33a6-4d73-bc63-c87270a198a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616151791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1616151791
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.892482844
Short name T267
Test name
Test status
Simulation time 1206596823 ps
CPU time 5.11 seconds
Started Jun 21 06:10:05 PM PDT 24
Finished Jun 21 06:10:11 PM PDT 24
Peak memory 197920 kb
Host smart-7749d82c-2a17-4f99-917e-8abb2ea06216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892482844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.892482844
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1858752568
Short name T675
Test name
Test status
Simulation time 40168341 ps
CPU time 0.79 seconds
Started Jun 21 06:10:03 PM PDT 24
Finished Jun 21 06:10:05 PM PDT 24
Peak memory 195944 kb
Host smart-5ef9c3b7-6f66-4378-90c7-64ee15e2fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858752568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1858752568
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.493098354
Short name T210
Test name
Test status
Simulation time 77385466 ps
CPU time 1.14 seconds
Started Jun 21 06:10:03 PM PDT 24
Finished Jun 21 06:10:05 PM PDT 24
Peak memory 195568 kb
Host smart-717591bf-3e31-4f96-9f47-08fc1d67075d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493098354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.493098354
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.122942715
Short name T485
Test name
Test status
Simulation time 23293502924 ps
CPU time 134.16 seconds
Started Jun 21 06:10:10 PM PDT 24
Finished Jun 21 06:12:25 PM PDT 24
Peak memory 198156 kb
Host smart-621abd64-1d1b-48b4-9b68-288d43e39ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122942715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.122942715
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2990109285
Short name T931
Test name
Test status
Simulation time 39618685 ps
CPU time 1.03 seconds
Started Jun 21 06:57:02 PM PDT 24
Finished Jun 21 06:57:09 PM PDT 24
Peak memory 196440 kb
Host smart-b8c92657-b70e-4b0f-9f46-df62e01e3b9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2990109285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2990109285
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2109323942
Short name T914
Test name
Test status
Simulation time 47841137 ps
CPU time 1.3 seconds
Started Jun 21 06:57:04 PM PDT 24
Finished Jun 21 06:57:11 PM PDT 24
Peak memory 196700 kb
Host smart-291cec89-acd6-48e8-8b54-1c514254495a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109323942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2109323942
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.378461225
Short name T900
Test name
Test status
Simulation time 57271200 ps
CPU time 1.03 seconds
Started Jun 21 06:57:06 PM PDT 24
Finished Jun 21 06:57:15 PM PDT 24
Peak memory 196296 kb
Host smart-45aa8729-2503-491d-9e7c-eb416f3f2f10
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=378461225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.378461225
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1410341191
Short name T877
Test name
Test status
Simulation time 65404981 ps
CPU time 1.07 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:13 PM PDT 24
Peak memory 196224 kb
Host smart-a1c6b1b4-e885-4c50-973c-2c361aca3e8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410341191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1410341191
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.277837903
Short name T935
Test name
Test status
Simulation time 540277341 ps
CPU time 1.34 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:13 PM PDT 24
Peak memory 197912 kb
Host smart-044c18e4-9537-44a2-81ec-e459a0a0afa4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=277837903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.277837903
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2847681155
Short name T930
Test name
Test status
Simulation time 108874530 ps
CPU time 1.12 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:13 PM PDT 24
Peak memory 196608 kb
Host smart-cb4c7cd2-520f-48eb-b40a-5c0fdcc9ac10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847681155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2847681155
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1174080523
Short name T890
Test name
Test status
Simulation time 95919264 ps
CPU time 1.54 seconds
Started Jun 21 06:57:21 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 196824 kb
Host smart-d6291b97-8bec-4091-b81e-0d9450399049
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1174080523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1174080523
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3526038463
Short name T886
Test name
Test status
Simulation time 117775906 ps
CPU time 1.14 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 195748 kb
Host smart-6aac69fb-3a17-495b-9cce-0066dfebf7ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526038463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3526038463
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1294701641
Short name T854
Test name
Test status
Simulation time 55882052 ps
CPU time 0.97 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:12 PM PDT 24
Peak memory 196624 kb
Host smart-da374ca5-ec3a-4cd2-a2f0-52e98b187d71
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1294701641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1294701641
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1185142573
Short name T936
Test name
Test status
Simulation time 356653473 ps
CPU time 0.98 seconds
Started Jun 21 06:57:06 PM PDT 24
Finished Jun 21 06:57:14 PM PDT 24
Peak memory 196320 kb
Host smart-c77349b7-93c2-4b50-80eb-754ef560bb69
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185142573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1185142573
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2646028369
Short name T864
Test name
Test status
Simulation time 187469945 ps
CPU time 1.01 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:13 PM PDT 24
Peak memory 195524 kb
Host smart-2e77e439-6d05-4338-b9b8-9c81840521c0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2646028369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2646028369
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.574567427
Short name T847
Test name
Test status
Simulation time 66094652 ps
CPU time 0.86 seconds
Started Jun 21 06:57:04 PM PDT 24
Finished Jun 21 06:57:11 PM PDT 24
Peak memory 195328 kb
Host smart-57ddabe2-62c8-4bc8-a2ec-9b2236c5e61a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574567427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.574567427
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2726097065
Short name T903
Test name
Test status
Simulation time 171013607 ps
CPU time 1.13 seconds
Started Jun 21 06:57:06 PM PDT 24
Finished Jun 21 06:57:15 PM PDT 24
Peak memory 195536 kb
Host smart-284375a4-9c6d-4ba7-8043-5390601af6a6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2726097065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2726097065
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3460615282
Short name T894
Test name
Test status
Simulation time 312856969 ps
CPU time 1 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:13 PM PDT 24
Peak memory 196420 kb
Host smart-482cf2f4-dde7-4fec-8809-aa1d1e371d27
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460615282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3460615282
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2035528995
Short name T882
Test name
Test status
Simulation time 63349140 ps
CPU time 1.21 seconds
Started Jun 21 06:57:04 PM PDT 24
Finished Jun 21 06:57:11 PM PDT 24
Peak memory 196480 kb
Host smart-227bea7e-c3c9-4f56-92ff-65022604c64a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2035528995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2035528995
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.910266768
Short name T919
Test name
Test status
Simulation time 102629625 ps
CPU time 1.51 seconds
Started Jun 21 06:57:06 PM PDT 24
Finished Jun 21 06:57:14 PM PDT 24
Peak memory 197872 kb
Host smart-91c6f4e9-d10c-466e-a353-d58800712b7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910266768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.910266768
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3464030936
Short name T843
Test name
Test status
Simulation time 168753836 ps
CPU time 1.21 seconds
Started Jun 21 06:57:11 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 196456 kb
Host smart-d3eb3b67-707a-47ab-8135-0970b613f97d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3464030936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3464030936
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3505322292
Short name T904
Test name
Test status
Simulation time 131068335 ps
CPU time 0.97 seconds
Started Jun 21 06:57:13 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 196448 kb
Host smart-886e5c9f-ddd6-4925-bfd7-907344fb4351
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505322292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3505322292
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.1360996264
Short name T902
Test name
Test status
Simulation time 96858261 ps
CPU time 1.02 seconds
Started Jun 21 06:57:11 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 195756 kb
Host smart-d99e72a2-1395-4dde-a7c5-ef5d979e476e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1360996264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.1360996264
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2651879947
Short name T870
Test name
Test status
Simulation time 24746777 ps
CPU time 0.84 seconds
Started Jun 21 06:57:14 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 195460 kb
Host smart-24ef5b8d-f0ed-40c2-b7d8-a7bb72c90c44
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651879947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2651879947
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.928011552
Short name T892
Test name
Test status
Simulation time 267156052 ps
CPU time 1.44 seconds
Started Jun 21 06:57:12 PM PDT 24
Finished Jun 21 06:57:20 PM PDT 24
Peak memory 196704 kb
Host smart-07a47a38-0a70-44e5-953b-0c20ff014043
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=928011552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.928011552
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.478679926
Short name T910
Test name
Test status
Simulation time 55851640 ps
CPU time 0.88 seconds
Started Jun 21 06:57:09 PM PDT 24
Finished Jun 21 06:57:17 PM PDT 24
Peak memory 195224 kb
Host smart-b3824299-04ec-4766-9b6f-79a77d02f75f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478679926 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.478679926
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2196902771
Short name T932
Test name
Test status
Simulation time 313470232 ps
CPU time 1.02 seconds
Started Jun 21 06:57:14 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 196712 kb
Host smart-12bc75f1-6e80-4c5b-abb1-ba9c42fd87cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2196902771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2196902771
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3648234418
Short name T883
Test name
Test status
Simulation time 61319266 ps
CPU time 0.93 seconds
Started Jun 21 06:57:14 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 197784 kb
Host smart-9cde8f90-aeed-4419-9189-7fb2c0c51494
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648234418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3648234418
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1675267890
Short name T893
Test name
Test status
Simulation time 26453915 ps
CPU time 0.82 seconds
Started Jun 21 06:57:06 PM PDT 24
Finished Jun 21 06:57:13 PM PDT 24
Peak memory 195136 kb
Host smart-cf6182d5-00a1-4cad-b7ca-3c567ad5c6c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1675267890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1675267890
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3906853553
Short name T851
Test name
Test status
Simulation time 497259115 ps
CPU time 1.1 seconds
Started Jun 21 06:57:06 PM PDT 24
Finished Jun 21 06:57:14 PM PDT 24
Peak memory 196404 kb
Host smart-aee2485f-9c92-43cd-9c05-6e3547fe2327
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906853553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3906853553
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3279816058
Short name T899
Test name
Test status
Simulation time 73607536 ps
CPU time 1.26 seconds
Started Jun 21 06:57:09 PM PDT 24
Finished Jun 21 06:57:18 PM PDT 24
Peak memory 197892 kb
Host smart-7208fe95-6e29-4741-8031-932877cd82b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3279816058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3279816058
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2278681396
Short name T940
Test name
Test status
Simulation time 194664029 ps
CPU time 1.57 seconds
Started Jun 21 06:57:13 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 196620 kb
Host smart-44396e7c-fd84-4e68-afb3-46fd8e947766
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278681396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2278681396
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2863670626
Short name T911
Test name
Test status
Simulation time 24860131 ps
CPU time 0.76 seconds
Started Jun 21 06:57:10 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 195992 kb
Host smart-d48c9ede-0435-4686-a0d1-074bddd3c449
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2863670626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2863670626
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1572317374
Short name T901
Test name
Test status
Simulation time 103531620 ps
CPU time 0.78 seconds
Started Jun 21 06:57:15 PM PDT 24
Finished Jun 21 06:57:22 PM PDT 24
Peak memory 195476 kb
Host smart-680c0a67-ad1e-4a1f-9d66-d33848caf2dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572317374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1572317374
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.3369958221
Short name T933
Test name
Test status
Simulation time 49387642 ps
CPU time 0.98 seconds
Started Jun 21 06:57:09 PM PDT 24
Finished Jun 21 06:57:18 PM PDT 24
Peak memory 197956 kb
Host smart-9e67f265-caae-454c-9376-db4aa4fe71ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3369958221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.3369958221
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.226073084
Short name T938
Test name
Test status
Simulation time 202657086 ps
CPU time 1.05 seconds
Started Jun 21 06:57:11 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 195684 kb
Host smart-3e57a10d-3c01-47d6-b695-7f4ba2347e48
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226073084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.226073084
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.4043238323
Short name T891
Test name
Test status
Simulation time 80234682 ps
CPU time 0.96 seconds
Started Jun 21 06:57:11 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 195456 kb
Host smart-dc1ca97a-af0c-4aaf-a481-5f0fc0d0e3ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4043238323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.4043238323
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2954415404
Short name T921
Test name
Test status
Simulation time 63860397 ps
CPU time 1.15 seconds
Started Jun 21 06:57:10 PM PDT 24
Finished Jun 21 06:57:18 PM PDT 24
Peak memory 196248 kb
Host smart-3db41584-a2fd-438c-95f5-0a889004bc11
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954415404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2954415404
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3422207394
Short name T888
Test name
Test status
Simulation time 214601604 ps
CPU time 1.15 seconds
Started Jun 21 06:57:13 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 196352 kb
Host smart-fa1528ed-7ea3-45a5-a4de-fefb0a83b45e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3422207394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3422207394
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.809176473
Short name T879
Test name
Test status
Simulation time 41768723 ps
CPU time 0.68 seconds
Started Jun 21 06:57:13 PM PDT 24
Finished Jun 21 06:57:20 PM PDT 24
Peak memory 195040 kb
Host smart-3bbefa43-5091-47e8-994b-59c1ea67f971
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809176473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.809176473
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.835859584
Short name T842
Test name
Test status
Simulation time 74333131 ps
CPU time 0.72 seconds
Started Jun 21 06:57:14 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 195404 kb
Host smart-97833286-116a-4125-a43f-e1dc0b475407
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=835859584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.835859584
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4197875467
Short name T896
Test name
Test status
Simulation time 266560565 ps
CPU time 1.23 seconds
Started Jun 21 06:57:13 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 195832 kb
Host smart-78df53d2-086b-4cfc-b10a-23cf9098e6ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197875467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4197875467
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.911478977
Short name T868
Test name
Test status
Simulation time 42505619 ps
CPU time 0.88 seconds
Started Jun 21 06:57:10 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 196456 kb
Host smart-68c144c6-3d35-44ec-b4a4-17837c03a747
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=911478977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.911478977
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164840988
Short name T897
Test name
Test status
Simulation time 29479670 ps
CPU time 0.95 seconds
Started Jun 21 06:57:11 PM PDT 24
Finished Jun 21 06:57:19 PM PDT 24
Peak memory 196388 kb
Host smart-32c72a5a-1fea-4d34-862f-2518c83f2e06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164840988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1164840988
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1528662648
Short name T849
Test name
Test status
Simulation time 50484682 ps
CPU time 1.05 seconds
Started Jun 21 06:57:13 PM PDT 24
Finished Jun 21 06:57:21 PM PDT 24
Peak memory 195804 kb
Host smart-14555bbb-b2ea-4339-8d96-6e36c75dc3da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1528662648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1528662648
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436602634
Short name T866
Test name
Test status
Simulation time 41637823 ps
CPU time 1.12 seconds
Started Jun 21 06:57:12 PM PDT 24
Finished Jun 21 06:57:20 PM PDT 24
Peak memory 196392 kb
Host smart-3aaedf9d-d167-4365-87d2-f30285e28557
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436602634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1436602634
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.1092582333
Short name T874
Test name
Test status
Simulation time 305594505 ps
CPU time 0.77 seconds
Started Jun 21 06:57:12 PM PDT 24
Finished Jun 21 06:57:20 PM PDT 24
Peak memory 195420 kb
Host smart-b20f65b3-f4ba-4bd7-971e-41c233ad286a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1092582333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.1092582333
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520970645
Short name T929
Test name
Test status
Simulation time 156033086 ps
CPU time 1.17 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 197424 kb
Host smart-d4556af0-1f29-4d0e-9ae8-6280cf267a22
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520970645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3520970645
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1947173505
Short name T857
Test name
Test status
Simulation time 22869337 ps
CPU time 0.76 seconds
Started Jun 21 06:57:20 PM PDT 24
Finished Jun 21 06:57:26 PM PDT 24
Peak memory 194356 kb
Host smart-a08e82d6-556a-43ac-8cee-d71a35f1feeb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1947173505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1947173505
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4197165987
Short name T884
Test name
Test status
Simulation time 88524272 ps
CPU time 1.28 seconds
Started Jun 21 06:57:21 PM PDT 24
Finished Jun 21 06:57:27 PM PDT 24
Peak memory 196768 kb
Host smart-363651de-b821-4274-937b-0997924583e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197165987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4197165987
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1321576712
Short name T906
Test name
Test status
Simulation time 37330230 ps
CPU time 0.84 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 195388 kb
Host smart-7dc487c1-3e99-4fdc-8e2f-dc085bb4a616
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1321576712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1321576712
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.565568743
Short name T915
Test name
Test status
Simulation time 38340988 ps
CPU time 0.88 seconds
Started Jun 21 06:57:02 PM PDT 24
Finished Jun 21 06:57:09 PM PDT 24
Peak memory 196616 kb
Host smart-e73faa77-f9cf-4af0-a73b-c85669c1ba67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565568743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.565568743
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2179799336
Short name T916
Test name
Test status
Simulation time 36547449 ps
CPU time 1.02 seconds
Started Jun 21 06:57:19 PM PDT 24
Finished Jun 21 06:57:25 PM PDT 24
Peak memory 195508 kb
Host smart-c61cabe0-ab59-491d-9a8c-1c6aff8ec782
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2179799336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2179799336
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.623010939
Short name T907
Test name
Test status
Simulation time 94960952 ps
CPU time 1.42 seconds
Started Jun 21 06:57:21 PM PDT 24
Finished Jun 21 06:57:27 PM PDT 24
Peak memory 195548 kb
Host smart-cf6cf1ca-97d2-4379-a470-b59ad18f3ae6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623010939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.623010939
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.774783545
Short name T872
Test name
Test status
Simulation time 246462646 ps
CPU time 1.2 seconds
Started Jun 21 06:57:18 PM PDT 24
Finished Jun 21 06:57:25 PM PDT 24
Peak memory 197868 kb
Host smart-af1d46d6-ff10-4924-a1f6-e6c05a647101
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=774783545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.774783545
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2698810504
Short name T937
Test name
Test status
Simulation time 64533037 ps
CPU time 1.2 seconds
Started Jun 21 06:57:19 PM PDT 24
Finished Jun 21 06:57:26 PM PDT 24
Peak memory 197876 kb
Host smart-c19b1333-aa38-4cb2-8de7-a0ca35d60d2c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698810504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2698810504
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2672929247
Short name T885
Test name
Test status
Simulation time 101365325 ps
CPU time 0.94 seconds
Started Jun 21 06:57:20 PM PDT 24
Finished Jun 21 06:57:26 PM PDT 24
Peak memory 196640 kb
Host smart-9bd02ce0-d3fd-486d-9ffb-280549de9b6a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2672929247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2672929247
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.983327068
Short name T862
Test name
Test status
Simulation time 57056897 ps
CPU time 1.23 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:29 PM PDT 24
Peak memory 197896 kb
Host smart-a862f303-4c09-402a-a1f5-1917592190f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983327068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.983327068
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4269006206
Short name T878
Test name
Test status
Simulation time 87029671 ps
CPU time 0.88 seconds
Started Jun 21 06:57:19 PM PDT 24
Finished Jun 21 06:57:25 PM PDT 24
Peak memory 195604 kb
Host smart-3c7d2196-ee81-46ef-8869-258bd2d41cf0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4269006206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.4269006206
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.388731557
Short name T858
Test name
Test status
Simulation time 119567308 ps
CPU time 0.95 seconds
Started Jun 21 06:57:21 PM PDT 24
Finished Jun 21 06:57:26 PM PDT 24
Peak memory 197772 kb
Host smart-88073538-bf65-43c8-b17c-49fc051fba30
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388731557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.388731557
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.349843939
Short name T898
Test name
Test status
Simulation time 49750598 ps
CPU time 1.08 seconds
Started Jun 21 06:57:23 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 197892 kb
Host smart-520d44ee-1523-45b2-9294-6cc8903f0422
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=349843939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.349843939
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1436134760
Short name T918
Test name
Test status
Simulation time 56209481 ps
CPU time 1.14 seconds
Started Jun 21 06:57:19 PM PDT 24
Finished Jun 21 06:57:26 PM PDT 24
Peak memory 196520 kb
Host smart-90abf40c-a078-49e3-98b6-f7577b46ddaf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436134760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1436134760
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3082453118
Short name T928
Test name
Test status
Simulation time 34727351 ps
CPU time 0.98 seconds
Started Jun 21 06:57:23 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 195716 kb
Host smart-7bbc6de9-84fa-412e-9632-9afdf5d2cf64
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3082453118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3082453118
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3236498694
Short name T909
Test name
Test status
Simulation time 245513531 ps
CPU time 1.13 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 197828 kb
Host smart-f393a5ee-2f4c-4e65-8c43-65bb3e230848
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236498694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3236498694
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1145866024
Short name T853
Test name
Test status
Simulation time 221427668 ps
CPU time 1.08 seconds
Started Jun 21 06:57:23 PM PDT 24
Finished Jun 21 06:57:29 PM PDT 24
Peak memory 196472 kb
Host smart-57593d0e-bb36-4b4e-bd98-856cb36a2b38
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1145866024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1145866024
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3253234304
Short name T920
Test name
Test status
Simulation time 357817231 ps
CPU time 1.29 seconds
Started Jun 21 06:57:19 PM PDT 24
Finished Jun 21 06:57:26 PM PDT 24
Peak memory 197916 kb
Host smart-528dde25-2e7b-4865-b592-639eea32e919
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253234304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3253234304
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3626260798
Short name T917
Test name
Test status
Simulation time 46769609 ps
CPU time 0.87 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 195264 kb
Host smart-baf6f708-52c5-40c3-9077-a62b497e5a57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3626260798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3626260798
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.209283022
Short name T905
Test name
Test status
Simulation time 54476558 ps
CPU time 1.01 seconds
Started Jun 21 06:57:18 PM PDT 24
Finished Jun 21 06:57:25 PM PDT 24
Peak memory 196424 kb
Host smart-ab555e94-9ac5-47cf-bba3-bf2a3df680f7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209283022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.209283022
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2320925923
Short name T927
Test name
Test status
Simulation time 83762461 ps
CPU time 1.2 seconds
Started Jun 21 06:57:31 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 196344 kb
Host smart-e136bcaf-316f-47b5-88c1-c69f7d1fcf09
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2320925923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2320925923
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2209861580
Short name T912
Test name
Test status
Simulation time 38136774 ps
CPU time 0.87 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 195212 kb
Host smart-4faea2f5-0cf1-49d0-be54-4142cb16e5e3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209861580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2209861580
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.770828379
Short name T887
Test name
Test status
Simulation time 43927298 ps
CPU time 1.03 seconds
Started Jun 21 06:57:31 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 195736 kb
Host smart-eed081ce-ed8a-48da-9f24-c02a212f1b65
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=770828379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.770828379
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2727634004
Short name T845
Test name
Test status
Simulation time 26556352 ps
CPU time 0.74 seconds
Started Jun 21 06:57:28 PM PDT 24
Finished Jun 21 06:57:31 PM PDT 24
Peak memory 194332 kb
Host smart-f319577a-f835-496d-9dfd-d29a1bde1e3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727634004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2727634004
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4144643223
Short name T869
Test name
Test status
Simulation time 50853729 ps
CPU time 0.94 seconds
Started Jun 21 06:57:04 PM PDT 24
Finished Jun 21 06:57:10 PM PDT 24
Peak memory 196504 kb
Host smart-f42f878a-9392-468a-9c87-a1fb56041601
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4144643223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4144643223
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1400146906
Short name T859
Test name
Test status
Simulation time 127700019 ps
CPU time 1.17 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 195496 kb
Host smart-481380f0-2331-40d1-8b91-2f12bd214c41
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400146906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1400146906
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2620007198
Short name T939
Test name
Test status
Simulation time 40134731 ps
CPU time 0.82 seconds
Started Jun 21 06:57:31 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 195168 kb
Host smart-2fba13fd-0f32-43fd-a109-91e9e71ac551
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2620007198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2620007198
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3238388094
Short name T846
Test name
Test status
Simulation time 31533093 ps
CPU time 0.93 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 195712 kb
Host smart-41026f9d-191e-4ed4-ad58-b61f04f595d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238388094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3238388094
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3725118367
Short name T850
Test name
Test status
Simulation time 247502015 ps
CPU time 1.18 seconds
Started Jun 21 06:57:29 PM PDT 24
Finished Jun 21 06:57:32 PM PDT 24
Peak memory 196452 kb
Host smart-7229acc3-eb09-4c5c-9305-5191642ea151
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3725118367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3725118367
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1450297200
Short name T863
Test name
Test status
Simulation time 258781486 ps
CPU time 1.08 seconds
Started Jun 21 06:57:29 PM PDT 24
Finished Jun 21 06:57:33 PM PDT 24
Peak memory 195724 kb
Host smart-37a222d8-f315-4127-87d7-fcf3febbf275
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450297200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1450297200
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2677262410
Short name T856
Test name
Test status
Simulation time 163596272 ps
CPU time 1.21 seconds
Started Jun 21 06:57:28 PM PDT 24
Finished Jun 21 06:57:32 PM PDT 24
Peak memory 197012 kb
Host smart-a70667f2-3b52-47cf-b057-824de2559f5b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2677262410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2677262410
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3853672702
Short name T873
Test name
Test status
Simulation time 29581997 ps
CPU time 0.98 seconds
Started Jun 21 06:57:27 PM PDT 24
Finished Jun 21 06:57:31 PM PDT 24
Peak memory 196380 kb
Host smart-a95efe84-89f1-446a-a71b-74375a8f4bcf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853672702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3853672702
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1963159753
Short name T908
Test name
Test status
Simulation time 86086211 ps
CPU time 0.75 seconds
Started Jun 21 06:57:31 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 195372 kb
Host smart-26342685-e21f-48e8-a6af-cb798c720056
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1963159753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1963159753
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1713902144
Short name T876
Test name
Test status
Simulation time 50076486 ps
CPU time 1.15 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 196400 kb
Host smart-d12264a3-1108-48df-adb6-4ea5bb5dd6ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713902144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1713902144
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1631731847
Short name T855
Test name
Test status
Simulation time 48998277 ps
CPU time 0.7 seconds
Started Jun 21 06:57:28 PM PDT 24
Finished Jun 21 06:57:31 PM PDT 24
Peak memory 194316 kb
Host smart-1dfc2185-f80d-46b9-a8c1-e77835327111
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1631731847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1631731847
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1461026089
Short name T923
Test name
Test status
Simulation time 97253814 ps
CPU time 1.41 seconds
Started Jun 21 06:57:28 PM PDT 24
Finished Jun 21 06:57:32 PM PDT 24
Peak memory 196492 kb
Host smart-872d9b90-8e5b-4387-b847-c290650ac294
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461026089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1461026089
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3621758696
Short name T922
Test name
Test status
Simulation time 30489659 ps
CPU time 0.88 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 196488 kb
Host smart-1e9b6fa1-67d3-4dc6-9572-16640b685835
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3621758696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3621758696
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3169351446
Short name T871
Test name
Test status
Simulation time 665861712 ps
CPU time 0.93 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:33 PM PDT 24
Peak memory 196368 kb
Host smart-511293d8-b681-400d-b581-28188a6b072c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169351446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3169351446
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4190674771
Short name T880
Test name
Test status
Simulation time 67482990 ps
CPU time 1.21 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 196420 kb
Host smart-b189e0fe-9a6f-4808-9a35-bf02412656ee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4190674771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4190674771
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.205609810
Short name T926
Test name
Test status
Simulation time 183398387 ps
CPU time 1.12 seconds
Started Jun 21 06:57:28 PM PDT 24
Finished Jun 21 06:57:32 PM PDT 24
Peak memory 196404 kb
Host smart-9c22c4c0-b6bc-4546-a95d-0300735a2ba9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205609810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.205609810
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2745289270
Short name T848
Test name
Test status
Simulation time 75501294 ps
CPU time 0.81 seconds
Started Jun 21 06:57:28 PM PDT 24
Finished Jun 21 06:57:31 PM PDT 24
Peak memory 196140 kb
Host smart-9f74ce3e-e02c-4245-a116-4beb82ea120d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2745289270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2745289270
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2079782728
Short name T889
Test name
Test status
Simulation time 36063640 ps
CPU time 0.85 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 196072 kb
Host smart-c5aa99f8-dfbf-42a1-a0a1-b146330ac964
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079782728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2079782728
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.2385389007
Short name T881
Test name
Test status
Simulation time 68420713 ps
CPU time 1.26 seconds
Started Jun 21 06:57:29 PM PDT 24
Finished Jun 21 06:57:32 PM PDT 24
Peak memory 197172 kb
Host smart-2e3880f1-eb9c-40cb-893a-caa1cdc0645d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2385389007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.2385389007
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1911438083
Short name T852
Test name
Test status
Simulation time 54734180 ps
CPU time 1.09 seconds
Started Jun 21 06:57:37 PM PDT 24
Finished Jun 21 06:57:41 PM PDT 24
Peak memory 196624 kb
Host smart-723460a4-9e99-4f29-9004-bf5d5788b75f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911438083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1911438083
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3241282446
Short name T860
Test name
Test status
Simulation time 94980555 ps
CPU time 0.69 seconds
Started Jun 21 06:57:28 PM PDT 24
Finished Jun 21 06:57:31 PM PDT 24
Peak memory 194856 kb
Host smart-5b6a84b2-1b2d-454f-a25e-dc57ecc03f9f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3241282446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3241282446
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3896738563
Short name T895
Test name
Test status
Simulation time 331748643 ps
CPU time 1.03 seconds
Started Jun 21 06:57:30 PM PDT 24
Finished Jun 21 06:57:34 PM PDT 24
Peak memory 196364 kb
Host smart-5a77baac-c742-4652-bdaf-7e78b056722d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896738563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3896738563
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.483742823
Short name T925
Test name
Test status
Simulation time 64315450 ps
CPU time 1.15 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 197192 kb
Host smart-98c45a11-6c30-40c3-9264-2ff57a60ceb7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=483742823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.483742823
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2730682258
Short name T934
Test name
Test status
Simulation time 637557475 ps
CPU time 1.23 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 196412 kb
Host smart-428fa396-d938-4ce7-9238-b16463d17f58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730682258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2730682258
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2835484650
Short name T924
Test name
Test status
Simulation time 247968402 ps
CPU time 1.07 seconds
Started Jun 21 06:57:07 PM PDT 24
Finished Jun 21 06:57:16 PM PDT 24
Peak memory 196644 kb
Host smart-1631659a-f9a4-4276-8571-8d7240f8bc8b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2835484650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2835484650
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2795129787
Short name T875
Test name
Test status
Simulation time 46590077 ps
CPU time 1.02 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:13 PM PDT 24
Peak memory 196344 kb
Host smart-fdd263e6-34e9-49e0-b5de-09f6af98e4ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795129787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2795129787
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3931701169
Short name T865
Test name
Test status
Simulation time 71292777 ps
CPU time 1.27 seconds
Started Jun 21 06:57:22 PM PDT 24
Finished Jun 21 06:57:28 PM PDT 24
Peak memory 195400 kb
Host smart-92605c05-b076-4448-b5c1-7a16e3c4f899
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3931701169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3931701169
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1194454640
Short name T861
Test name
Test status
Simulation time 231919726 ps
CPU time 1.15 seconds
Started Jun 21 06:57:03 PM PDT 24
Finished Jun 21 06:57:10 PM PDT 24
Peak memory 196556 kb
Host smart-d5b36cb9-e753-47a0-b150-bae0fcc76581
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194454640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1194454640
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3825018748
Short name T913
Test name
Test status
Simulation time 28684393 ps
CPU time 0.73 seconds
Started Jun 21 06:57:05 PM PDT 24
Finished Jun 21 06:57:11 PM PDT 24
Peak memory 195356 kb
Host smart-bfe28e60-f5ac-4c4d-9864-c8065ccb092f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3825018748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3825018748
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1341024696
Short name T867
Test name
Test status
Simulation time 188262838 ps
CPU time 1.22 seconds
Started Jun 21 06:57:04 PM PDT 24
Finished Jun 21 06:57:11 PM PDT 24
Peak memory 195516 kb
Host smart-76b83156-a1ca-4e12-afd6-77891e9f8196
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341024696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1341024696
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2884547544
Short name T841
Test name
Test status
Simulation time 186084416 ps
CPU time 1.03 seconds
Started Jun 21 06:57:02 PM PDT 24
Finished Jun 21 06:57:09 PM PDT 24
Peak memory 196420 kb
Host smart-42648ed9-bdb5-4cd8-b423-1db6767ee449
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2884547544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2884547544
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1209769872
Short name T844
Test name
Test status
Simulation time 138647523 ps
CPU time 1.18 seconds
Started Jun 21 06:57:03 PM PDT 24
Finished Jun 21 06:57:10 PM PDT 24
Peak memory 195700 kb
Host smart-14b3ec68-c290-45b5-9988-08c9e44442ee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209769872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1209769872
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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