Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5153753	1			T20	131608		T21	1		T22	1
all_pins[1]	5153753	1			T20	131608		T21	1		T22	1
all_pins[2]	5153753	1			T20	131608		T21	1		T22	1
all_pins[3]	5153753	1			T20	131608		T21	1		T22	1
all_pins[4]	5153753	1			T20	131608		T21	1		T22	1
all_pins[5]	5153753	1			T20	131608		T21	1		T22	1
all_pins[6]	5153753	1			T20	131608		T21	1		T22	1
all_pins[7]	5153753	1			T20	131608		T21	1		T22	1
all_pins[8]	5153753	1			T20	131608		T21	1		T22	1
all_pins[9]	5153753	1			T20	131608		T21	1		T22	1
all_pins[10]	5153753	1			T20	131608		T21	1		T22	1
all_pins[11]	5153753	1			T20	131608		T21	1		T22	1
all_pins[12]	5153753	1			T20	131608		T21	1		T22	1
all_pins[13]	5153753	1			T20	131608		T21	1		T22	1
all_pins[14]	5153753	1			T20	131608		T21	1		T22	1
all_pins[15]	5153753	1			T20	131608		T21	1		T22	1
all_pins[16]	5153753	1			T20	131608		T21	1		T22	1
all_pins[17]	5153753	1			T20	131608		T21	1		T22	1
all_pins[18]	5153753	1			T20	131608		T21	1		T22	1
all_pins[19]	5153753	1			T20	131608		T21	1		T22	1
all_pins[20]	5153753	1			T20	131608		T21	1		T22	1
all_pins[21]	5153753	1			T20	131608		T21	1		T22	1
all_pins[22]	5153753	1			T20	131608		T21	1		T22	1
all_pins[23]	5153753	1			T20	131608		T21	1		T22	1
all_pins[24]	5153753	1			T20	131608		T21	1		T22	1
all_pins[25]	5153753	1			T20	131608		T21	1		T22	1
all_pins[26]	5153753	1			T20	131608		T21	1		T22	1
all_pins[27]	5153753	1			T20	131608		T21	1		T22	1
all_pins[28]	5153753	1			T20	131608		T21	1		T22	1
all_pins[29]	5153753	1			T20	131608		T21	1		T22	1
all_pins[30]	5153753	1			T20	131608		T21	1		T22	1
all_pins[31]	5153753	1			T20	131608		T21	1		T22	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	102479221	1			T20	261246		T21	32		T22	32
values[0x1]	62440875	1			T20	159899		T23	1457		T1	2977
transitions[0x0=>0x1]	37416885	1			T20	957400		T23	762		T1	1801
transitions[0x1=>0x0]	37416731	1			T20	957400		T23	762		T1	1801

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3202288	1			T20	81994		T21	1		T22	1
all_pins[0]	values[0x1]	1951465	1			T20	49614		T23	38		T1	72
all_pins[0]	transitions[0x0=>0x1]	1209565	1			T20	30785		T23	20		T1	51
all_pins[0]	transitions[0x1=>0x0]	1205106	1			T20	30237		T23	23		T1	68
all_pins[1]	values[0x0]	3195413	1			T20	80639		T21	1		T22	1
all_pins[1]	values[0x1]	1958340	1			T20	50969		T23	43		T1	110
all_pins[1]	transitions[0x0=>0x1]	1172441	1			T20	30637		T23	28		T1	91
all_pins[1]	transitions[0x1=>0x0]	1165566	1			T20	29282		T23	23		T1	53
all_pins[2]	values[0x0]	3199496	1			T20	81401		T21	1		T22	1
all_pins[2]	values[0x1]	1954257	1			T20	50207		T23	47		T1	71
all_pins[2]	transitions[0x0=>0x1]	1168976	1			T20	29678		T23	28		T1	39
all_pins[2]	transitions[0x1=>0x0]	1173059	1			T20	30440		T23	24		T1	78
all_pins[3]	values[0x0]	3200157	1			T20	81564		T21	1		T22	1
all_pins[3]	values[0x1]	1953596	1			T20	50044		T23	41		T1	90
all_pins[3]	transitions[0x0=>0x1]	1168620	1			T20	29793		T23	24		T1	65
all_pins[3]	transitions[0x1=>0x0]	1169281	1			T20	29956		T23	30		T1	46
all_pins[4]	values[0x0]	3203385	1			T20	81543		T21	1		T22	1
all_pins[4]	values[0x1]	1950368	1			T20	50065		T23	48		T1	31
all_pins[4]	transitions[0x0=>0x1]	1165398	1			T20	30156		T23	27		T1	15
all_pins[4]	transitions[0x1=>0x0]	1168626	1			T20	30135		T23	20		T1	74
all_pins[5]	values[0x0]	3207108	1			T20	82406		T21	1		T22	1
all_pins[5]	values[0x1]	1946645	1			T20	49202		T23	39		T1	79
all_pins[5]	transitions[0x0=>0x1]	1164808	1			T20	29217		T23	17		T1	69
all_pins[5]	transitions[0x1=>0x0]	1168531	1			T20	30080		T23	26		T1	21
all_pins[6]	values[0x0]	3204644	1			T20	81425		T21	1		T22	1
all_pins[6]	values[0x1]	1949109	1			T20	50183		T23	42		T1	71
all_pins[6]	transitions[0x0=>0x1]	1167659	1			T20	30516		T23	22		T1	50
all_pins[6]	transitions[0x1=>0x0]	1165195	1			T20	29535		T23	19		T1	58
all_pins[7]	values[0x0]	3202194	1			T20	81664		T21	1		T22	1
all_pins[7]	values[0x1]	1951559	1			T20	49944		T23	46		T1	103
all_pins[7]	transitions[0x0=>0x1]	1168018	1			T20	29204		T23	34		T1	82
all_pins[7]	transitions[0x1=>0x0]	1165568	1			T20	29443		T23	30		T1	50
all_pins[8]	values[0x0]	3200806	1			T20	82114		T21	1		T22	1
all_pins[8]	values[0x1]	1952947	1			T20	49494		T23	42		T1	119
all_pins[8]	transitions[0x0=>0x1]	1170540	1			T20	29727		T23	23		T1	64
all_pins[8]	transitions[0x1=>0x0]	1169152	1			T20	30177		T23	27		T1	48
all_pins[9]	values[0x0]	3202207	1			T20	81496		T21	1		T22	1
all_pins[9]	values[0x1]	1951546	1			T20	50112		T23	44		T1	111
all_pins[9]	transitions[0x0=>0x1]	1169683	1			T20	30352		T23	23		T1	62
all_pins[9]	transitions[0x1=>0x0]	1171084	1			T20	29734		T23	21		T1	70
all_pins[10]	values[0x0]	3197164	1			T20	80819		T21	1		T22	1
all_pins[10]	values[0x1]	1956589	1			T20	50789		T23	45		T1	97
all_pins[10]	transitions[0x0=>0x1]	1169668	1			T20	30138		T23	22		T1	53
all_pins[10]	transitions[0x1=>0x0]	1164625	1			T20	29461		T23	21		T1	67
all_pins[11]	values[0x0]	3202026	1			T20	81471		T21	1		T22	1
all_pins[11]	values[0x1]	1951727	1			T20	50137		T23	46		T1	88
all_pins[11]	transitions[0x0=>0x1]	1167393	1			T20	29657		T23	20		T1	51
all_pins[11]	transitions[0x1=>0x0]	1172255	1			T20	30309		T23	19		T1	60
all_pins[12]	values[0x0]	3206154	1			T20	80700		T21	1		T22	1
all_pins[12]	values[0x1]	1947599	1			T20	50908		T23	45		T1	74
all_pins[12]	transitions[0x0=>0x1]	1166424	1			T20	29935		T23	22		T1	43
all_pins[12]	transitions[0x1=>0x0]	1170552	1			T20	29164		T23	23		T1	57
all_pins[13]	values[0x0]	3198114	1			T20	82518		T21	1		T22	1
all_pins[13]	values[0x1]	1955639	1			T20	49090		T23	49		T1	98
all_pins[13]	transitions[0x0=>0x1]	1172211	1			T20	29350		T23	25		T1	62
all_pins[13]	transitions[0x1=>0x0]	1164171	1			T20	31168		T23	21		T1	38
all_pins[14]	values[0x0]	3205588	1			T20	81512		T21	1		T22	1
all_pins[14]	values[0x1]	1948165	1			T20	50096		T23	48		T1	112
all_pins[14]	transitions[0x0=>0x1]	1162927	1			T20	30525		T23	22		T1	60
all_pins[14]	transitions[0x1=>0x0]	1170401	1			T20	29519		T23	23		T1	46
all_pins[15]	values[0x0]	3203557	1			T20	81149		T21	1		T22	1
all_pins[15]	values[0x1]	1950196	1			T20	50459		T23	51		T1	102
all_pins[15]	transitions[0x0=>0x1]	1170212	1			T20	30371		T23	28		T1	38
all_pins[15]	transitions[0x1=>0x0]	1168181	1			T20	30008		T23	25		T1	48
all_pins[16]	values[0x0]	3205738	1			T20	81867		T21	1		T22	1
all_pins[16]	values[0x1]	1948015	1			T20	49741		T23	47		T1	89
all_pins[16]	transitions[0x0=>0x1]	1165379	1			T20	29761		T23	22		T1	41
all_pins[16]	transitions[0x1=>0x0]	1167560	1			T20	30479		T23	26		T1	54
all_pins[17]	values[0x0]	3199930	1			T20	81858		T21	1		T22	1
all_pins[17]	values[0x1]	1953823	1			T20	49750		T23	41		T1	74
all_pins[17]	transitions[0x0=>0x1]	1172454	1			T20	29674		T23	18		T1	45
all_pins[17]	transitions[0x1=>0x0]	1166646	1			T20	29665		T23	24		T1	60
all_pins[18]	values[0x0]	3205401	1			T20	82372		T21	1		T22	1
all_pins[18]	values[0x1]	1948352	1			T20	49236		T23	51		T1	80
all_pins[18]	transitions[0x0=>0x1]	1164930	1			T20	29621		T23	31		T1	64
all_pins[18]	transitions[0x1=>0x0]	1170401	1			T20	30135		T23	21		T1	58
all_pins[19]	values[0x0]	3205847	1			T20	81857		T21	1		T22	1
all_pins[19]	values[0x1]	1947906	1			T20	49751		T23	54		T1	89
all_pins[19]	transitions[0x0=>0x1]	1166481	1			T20	30380		T23	26		T1	56
all_pins[19]	transitions[0x1=>0x0]	1166927	1			T20	29865		T23	23		T1	47
all_pins[20]	values[0x0]	3198740	1			T20	81682		T21	1		T22	1
all_pins[20]	values[0x1]	1955013	1			T20	49926		T23	37		T1	128
all_pins[20]	transitions[0x0=>0x1]	1170865	1			T20	29630		T23	12		T1	97
all_pins[20]	transitions[0x1=>0x0]	1163758	1			T20	29455		T23	29		T1	58
all_pins[21]	values[0x0]	3204343	1			T20	82671		T21	1		T22	1
all_pins[21]	values[0x1]	1949410	1			T20	48937		T23	47		T1	81
all_pins[21]	transitions[0x0=>0x1]	1164123	1			T20	29098		T23	30		T1	32
all_pins[21]	transitions[0x1=>0x0]	1169726	1			T20	30087		T23	20		T1	79
all_pins[22]	values[0x0]	3200722	1			T20	81970		T21	1		T22	1
all_pins[22]	values[0x1]	1953031	1			T20	49638		T23	45		T1	96
all_pins[22]	transitions[0x0=>0x1]	1171787	1			T20	30083		T23	26		T1	63
all_pins[22]	transitions[0x1=>0x0]	1168166	1			T20	29382		T23	28		T1	48
all_pins[23]	values[0x0]	3197734	1			T20	80327		T21	1		T22	1
all_pins[23]	values[0x1]	1956019	1			T20	51281		T23	52		T1	121
all_pins[23]	transitions[0x0=>0x1]	1170883	1			T20	30960		T23	31		T1	62
all_pins[23]	transitions[0x1=>0x0]	1167895	1			T20	29317		T23	24		T1	37
all_pins[24]	values[0x0]	3204095	1			T20	81524		T21	1		T22	1
all_pins[24]	values[0x1]	1949658	1			T20	50084		T23	47		T1	102
all_pins[24]	transitions[0x0=>0x1]	1165716	1			T20	29128		T23	19		T1	59
all_pins[24]	transitions[0x1=>0x0]	1172077	1			T20	30325		T23	24		T1	78
all_pins[25]	values[0x0]	3200833	1			T20	80658		T21	1		T22	1
all_pins[25]	values[0x1]	1952920	1			T20	50950		T23	51		T1	122
all_pins[25]	transitions[0x0=>0x1]	1168701	1			T20	30797		T23	27		T1	65
all_pins[25]	transitions[0x1=>0x0]	1165439	1			T20	29931		T23	23		T1	45
all_pins[26]	values[0x0]	3205526	1			T20	81530		T21	1		T22	1
all_pins[26]	values[0x1]	1948227	1			T20	50078		T23	39		T1	137
all_pins[26]	transitions[0x0=>0x1]	1163339	1			T20	29427		T23	21		T1	75
all_pins[26]	transitions[0x1=>0x0]	1168032	1			T20	30299		T23	33		T1	60
all_pins[27]	values[0x0]	3203723	1			T20	81967		T21	1		T22	1
all_pins[27]	values[0x1]	1950030	1			T20	49641		T23	47		T1	79
all_pins[27]	transitions[0x0=>0x1]	1169930	1			T20	29647		T23	27		T1	41
all_pins[27]	transitions[0x1=>0x0]	1168127	1			T20	30084		T23	19		T1	99
all_pins[28]	values[0x0]	3203056	1			T20	80646		T21	1		T22	1
all_pins[28]	values[0x1]	1950697	1			T20	50962		T23	45		T1	112
all_pins[28]	transitions[0x0=>0x1]	1167495	1			T20	30288		T23	19		T1	71
all_pins[28]	transitions[0x1=>0x0]	1166828	1			T20	28967		T23	21		T1	38
all_pins[29]	values[0x0]	3203702	1			T20	82374		T21	1		T22	1
all_pins[29]	values[0x1]	1950051	1			T20	49234		T23	53		T1	88
all_pins[29]	transitions[0x0=>0x1]	1167928	1			T20	29177		T23	28		T1	32
all_pins[29]	transitions[0x1=>0x0]	1168574	1			T20	30905		T23	20		T1	56
all_pins[30]	values[0x0]	3202937	1			T20	82205		T21	1		T22	1
all_pins[30]	values[0x1]	1950816	1			T20	49403		T23	46		T1	62
all_pins[30]	transitions[0x0=>0x1]	1167020	1			T20	29809		T23	16		T1	37
all_pins[30]	transitions[0x1=>0x0]	1166255	1			T20	29640		T23	23		T1	63
all_pins[31]	values[0x0]	3206593	1			T20	82542		T21	1		T22	1
all_pins[31]	values[0x1]	1947160	1			T20	49066		T23	41		T1	89
all_pins[31]	transitions[0x0=>0x1]	1165311	1			T20	29879		T23	24		T1	66
all_pins[31]	transitions[0x1=>0x0]	1168967	1			T20	30216		T23	29		T1	39