Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[1]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[2]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[3]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[4]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[5]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[6]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[7]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[8]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[9]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[10]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[11]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[12]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[13]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[14]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[15]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[16]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[17]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[18]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[19]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[20]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[21]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[22]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[23]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[24]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[25]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[26]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[27]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[28]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[29]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[30]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[31]	16530256	1			T20	391792		T21	1		T22	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321827029

1

T20

840990

T21

32

T22

32

auto[1]

207141163

1

T20

412743

T23

802296

T1

15779

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

420375937

1

T20

953564

T21

32

T22

32

auto[1]

108592255

1

T20

300169

T1

9181

T13

7614

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

388667031

1

T20

861569

T21

32

T22

32

auto[1]

140301161

1

T20

392165

T1

9861

T13

13711

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6117174	1			T20	143338		T21	1		T22	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4325619	1			T20	77176		T23	24001		T1	182
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1707774	1			T20	46782		T1	222		T13	137
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2221228	1			T20	71569		T1	5		T13	31
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	468429	1			T20	5546		T1	119		T13	209
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1690032	1			T20	47381		T1	122		T13	71
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6116153	1			T20	144136		T21	1		T22	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4318202	1			T20	76936		T23	26128		T1	230
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1707726	1			T20	47453		T1	145		T13	99
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2225400	1			T20	70449		T1	3		T13	53
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	469056	1			T20	5219		T1	153		T13	286
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1693719	1			T20	47599		T1	116		T13	187
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6121319	1			T20	145169		T21	1		T22	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4316666	1			T20	76773		T23	24413		T1	155
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1708954	1			T20	48352		T1	155		T13	143
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2223550	1			T20	70113		T1	6		T13	45
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	466874	1			T20	5279		T1	199		T13	229
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1692893	1			T20	46106		T1	138		T13	134
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6126375	1			T20	145974		T21	1		T22	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4312504	1			T20	77322		T23	24239		T1	125
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1707710	1			T20	47442		T1	199		T13	88
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2220323	1			T20	70185		T1	11		T13	50
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	469382	1			T20	5080		T1	185		T13	344
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1693962	1			T20	45789		T1	134		T13	128
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6116097	1			T20	143837		T21	1		T22	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4318142	1			T20	77214		T23	25681		T1	202
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1702029	1			T20	47067		T1	144		T13	133
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2228948	1			T20	70930		T1	1		T13	43
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	469618	1			T20	5102		T1	175		T13	231
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1695422	1			T20	47642		T1	124		T13	126
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6124325	1			T20	144741		T21	1		T22	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4316628	1			T20	77042		T23	25985		T1	211
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1706894	1			T20	48186		T1	166		T13	95
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2227439	1			T20	69852		T1	2		T13	46
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	467319	1			T20	5128		T1	131		T13	324
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1687651	1			T20	46843		T1	138		T13	146
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6133762	1			T20	145529		T21	1		T22	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4311443	1			T20	76876		T23	25414		T1	162
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1706250	1			T20	47247		T1	187		T13	125
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2219012	1			T20	70781		T1	8		T13	27
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	468574	1			T20	5360		T1	130		T13	244
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1691215	1			T20	45999		T1	167		T13	123
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6123450	1			T20	145219		T21	1		T22	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4325424	1			T20	77540		T23	25682		T1	141
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1709179	1			T20	47257		T1	165		T13	146
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2219523	1			T20	69913		T1	2		T13	28
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	465051	1			T20	5005		T1	157		T13	296
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1687629	1			T20	46858		T1	184		T13	101
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6132843	1			T20	145825		T21	1		T22	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4304373	1			T20	77212		T23	25640		T1	187
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1712627	1			T20	47435		T1	179		T13	181
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2219559	1			T20	70050		T1	3		T13	37
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	468114	1			T20	4995		T1	127		T13	240
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1692740	1			T20	46275		T1	151		T13	106
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6133723	1			T20	143859		T21	1		T22	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4309099	1			T20	77259		T23	25955		T1	171
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1706531	1			T20	46947		T1	145		T13	117
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2221698	1			T20	72152		T1	2		T13	31
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	471720	1			T20	5409		T1	176		T13	285
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1687485	1			T20	46166		T1	151		T13	94
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6124681	1			T20	144702		T21	1		T22	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4313095	1			T20	77188		T23	25021		T1	162
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1706237	1			T20	47323		T1	132		T13	115
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2222495	1			T20	70517		T1	1		T13	54
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	469085	1			T20	4987		T1	181		T13	309
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1694663	1			T20	47075		T1	168		T13	130
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6124587	1			T20	144325		T21	1		T22	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4310310	1			T20	77309		T23	25407		T1	229
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1707050	1			T20	47386		T1	172		T13	129
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2228253	1			T20	70586		T1	2		T13	30
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	469038	1			T20	5385		T1	122		T13	242
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1691018	1			T20	46801		T1	122		T13	85
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6130956	1			T20	144917		T21	1		T22	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4310131	1			T20	77152		T23	24283		T1	232
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1706770	1			T20	46985		T1	84		T13	116
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2222860	1			T20	70947		T1	4		T13	26
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	469041	1			T20	5104		T1	210		T13	263
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1690498	1			T20	46687		T1	119		T13	78
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6123638	1			T20	145719		T21	1		T22	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4311638	1			T20	77270		T23	26036		T1	213
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1709151	1			T20	46465		T1	205		T13	109
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2221861	1			T20	71085		T1	3		T13	38
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	469085	1			T20	5157		T1	120		T13	344
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1694883	1			T20	46096		T1	109		T13	122
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6121444	1			T20	144520		T21	1		T22	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4316164	1			T20	76763		T23	25548		T1	218
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1705729	1			T20	48069		T1	131		T13	144
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2223502	1			T20	70015		T1	1		T13	52
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	471369	1			T20	5185		T1	175		T13	265
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1692048	1			T20	47240		T1	126		T13	133
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6121760	1			T20	145094		T21	1		T22	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4313176	1			T20	77206		T23	24720		T1	184
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1711746	1			T20	47669		T1	96		T13	82
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2225060	1			T20	70207		T1	6		T13	33
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	466266	1			T20	5114		T1	211		T13	282
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1692248	1			T20	46502		T1	156		T13	124
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6129190	1			T20	144485		T21	1		T22	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4316292	1			T20	77327		T23	24157		T1	185
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1697897	1			T20	46720		T1	196		T13	132
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2230672	1			T20	71785		T13	39		T2	719
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	470038	1			T20	5111		T1	110		T13	191
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1686167	1			T20	46364		T1	153		T13	119
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6125280	1			T20	145148		T21	1		T22	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4316277	1			T20	77547		T23	25404		T1	167
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1703812	1			T20	47001		T1	94		T13	126
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2229776	1			T20	70454		T1	8		T13	39
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	467687	1			T20	5093		T1	299		T13	282
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1687424	1			T20	46549		T1	82		T13	99
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6137285	1			T20	144010		T21	1		T22	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4316418	1			T20	77145		T23	25121		T1	196
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1697394	1			T20	47494		T1	150		T13	72
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2227418	1			T20	70992		T1	6		T13	30
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	467486	1			T20	5442		T1	168		T13	288
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1684255	1			T20	46709		T1	131		T13	104
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6120008	1			T20	144067		T21	1		T22	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4326740	1			T20	77292		T23	26403		T1	244
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1698178	1			T20	47229		T1	158		T13	161
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2229774	1			T20	70953		T1	3		T13	40
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	466869	1			T20	5331		T1	172		T13	273
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1688687	1			T20	46920		T1	76		T13	106
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6126333	1			T20	145282		T21	1		T22	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4316790	1			T20	76977		T23	25399		T1	191
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1700683	1			T20	46392		T1	180		T13	105
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2234599	1			T20	70986		T1	1		T13	43
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	466744	1			T20	5032		T1	123		T13	311
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1685107	1			T20	47123		T1	148		T13	160
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6145937	1			T20	144817		T21	1		T22	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4309229	1			T20	77705		T23	24443		T1	215
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1699604	1			T20	46454		T1	99		T13	155
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2227239	1			T20	70934		T1	1		T13	33
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	466099	1			T20	5144		T1	206		T13	262
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1682148	1			T20	46738		T1	124		T13	85
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6127488	1			T20	145829		T21	1		T22	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4314155	1			T20	77163		T23	26996		T1	210
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1702820	1			T20	47154		T1	121		T13	99
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2226065	1			T20	69626		T1	2		T13	37
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	469290	1			T20	5065		T1	193		T13	255
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1690438	1			T20	46955		T1	122		T13	109
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6122229	1			T20	145130		T21	1		T22	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4319410	1			T20	77270		T23	24220		T1	183
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1702999	1			T20	46853		T1	137		T13	82
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2225550	1			T20	70940		T1	5		T13	41
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	469062	1			T20	5052		T1	164		T13	297
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1691006	1			T20	46547		T1	162		T13	129
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6135342	1			T20	145222		T21	1		T22	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4314999	1			T20	76766		T23	24209		T1	157
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1700102	1			T20	47407		T1	167		T13	145
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2230720	1			T20	71303		T1	10		T13	26
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	469855	1			T20	5147		T1	175		T13	202
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1679238	1			T20	45947		T1	141		T13	128
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6123539	1			T20	144933		T21	1		T22	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4311426	1			T20	77071		T23	24744		T1	167
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1711360	1			T20	47315		T1	112		T13	91
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2223334	1			T20	70118		T1	6		T13	49
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	469733	1			T20	5313		T1	218		T13	326
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1690864	1			T20	47042		T1	150		T13	147
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6121559	1			T20	144859		T21	1		T22	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4317430	1			T20	77277		T23	24548		T1	176
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1699322	1			T20	47142		T1	195		T13	102
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2233346	1			T20	70719		T1	10		T13	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	470694	1			T20	5130		T1	118		T13	329
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1687905	1			T20	46665		T1	152		T13	136
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6122166	1			T20	145855		T21	1		T22	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4319014	1			T20	77157		T23	23140		T1	204
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1698640	1			T20	46396		T1	146		T13	119
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2239930	1			T20	71038		T1	1		T13	22
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	467778	1			T20	5204		T1	162		T13	271
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1682728	1			T20	46142		T1	135		T13	98
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6119425	1			T20	145544		T21	1		T22	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4316712	1			T20	76858		T23	25238		T1	182
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1703159	1			T20	46579		T1	150		T13	123
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2233262	1			T20	71014		T1	8		T13	34
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	468490	1			T20	5075		T1	201		T13	269
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1689208	1			T20	46722		T1	113		T13	121
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6125093	1			T20	144753		T21	1		T22	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4312536	1			T20	77363		T23	24896		T1	163
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1695891	1			T20	47004		T1	127		T13	148
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2235617	1			T20	71032		T1	7		T13	31
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	470988	1			T20	5180		T1	212		T13	284
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1690131	1			T20	46460		T1	142		T13	97
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6120025	1			T20	145024		T21	1		T22	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4322218	1			T20	77014		T23	24643		T1	252
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1704232	1			T20	47280		T1	124		T13	118
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2232752	1			T20	71078		T1	4		T13	44
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	469840	1			T20	5062		T1	153		T13	291
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1681189	1			T20	46334		T1	116		T13	147
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6132115	1			T20	145502		T21	1		T22	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4314705	1			T20	77091		T23	24582		T1	157
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1706315	1			T20	46582		T1	180		T13	140
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2226198	1			T20	71153		T1	3		T13	39
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	468034	1			T20	5110		T1	163		T13	229
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1682889	1			T20	46354		T1	146		T13	64

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal