Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[1]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[2]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[3]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[4]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[5]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[6]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[7]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[8]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[9]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[10]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[11]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[12]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[13]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[14]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[15]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[16]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[17]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[18]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[19]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[20]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[21]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[22]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[23]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[24]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[25]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[26]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[27]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[28]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[29]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[30]	16530256	1			T20	391792		T21	1		T22	1
bins_for_gpio_bits[31]	16530256	1			T20	391792		T21	1		T22	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321827029

1

T20

840990

T21

32

T22

32

auto[1]

207141163

1

T20

412743

T23

802296

T1

15779

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321819043

1

T20

840984

T21

32

T22

32

auto[1]

207149149

1

T20

412749

T23

802296

T1

15779

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9744169	1			T20	253209		T21	1		T22	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	301769	1			T20	8478		T1	22		T13	25
bins_for_gpio_bits[0]	auto[1]	auto[0]	302007	1			T20	8480		T1	22		T13	25
bins_for_gpio_bits[0]	auto[1]	auto[1]	6182311	1			T20	121625		T23	24001		T1	401
bins_for_gpio_bits[1]	auto[0]	auto[0]	9746951	1			T20	253686		T21	1		T22	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	302072	1			T20	8351		T1	21		T13	17
bins_for_gpio_bits[1]	auto[1]	auto[0]	302328	1			T20	8352		T1	21		T13	17
bins_for_gpio_bits[1]	auto[1]	auto[1]	6178905	1			T20	121403		T23	26128		T1	478
bins_for_gpio_bits[2]	auto[0]	auto[0]	9751852	1			T20	255382		T21	1		T22	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	301730	1			T20	8249		T1	18		T13	22
bins_for_gpio_bits[2]	auto[1]	auto[0]	301971	1			T20	8252		T1	18		T13	22
bins_for_gpio_bits[2]	auto[1]	auto[1]	6174703	1			T20	119909		T23	24413		T1	474
bins_for_gpio_bits[3]	auto[0]	auto[0]	9753076	1			T20	255417		T21	1		T22	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	301065	1			T20	8182		T1	19		T13	16
bins_for_gpio_bits[3]	auto[1]	auto[0]	301332	1			T20	8184		T1	19		T13	16
bins_for_gpio_bits[3]	auto[1]	auto[1]	6174783	1			T20	120009		T23	24239		T1	425
bins_for_gpio_bits[4]	auto[0]	auto[0]	9745275	1			T20	253324		T21	1		T22	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	301537	1			T20	8510		T1	19		T13	23
bins_for_gpio_bits[4]	auto[1]	auto[0]	301799	1			T20	8510		T1	19		T13	23
bins_for_gpio_bits[4]	auto[1]	auto[1]	6181645	1			T20	121448		T23	25681		T1	482
bins_for_gpio_bits[5]	auto[0]	auto[0]	9757690	1			T20	254453		T21	1		T22	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	300709	1			T20	8324		T1	21		T13	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	300968	1			T20	8326		T1	21		T13	16
bins_for_gpio_bits[5]	auto[1]	auto[1]	6170889	1			T20	120689		T23	25985		T1	459
bins_for_gpio_bits[6]	auto[0]	auto[0]	9757621	1			T20	255347		T21	1		T22	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	301147	1			T20	8208		T1	26		T13	24
bins_for_gpio_bits[6]	auto[1]	auto[0]	301403	1			T20	8210		T1	26		T13	24
bins_for_gpio_bits[6]	auto[1]	auto[1]	6170085	1			T20	120027		T23	25414		T1	433
bins_for_gpio_bits[7]	auto[0]	auto[0]	9750167	1			T20	254177		T21	1		T22	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	301742	1			T20	8210		T1	24		T13	25
bins_for_gpio_bits[7]	auto[1]	auto[0]	301985	1			T20	8212		T1	24		T13	25
bins_for_gpio_bits[7]	auto[1]	auto[1]	6176362	1			T20	121193		T23	25682		T1	458
bins_for_gpio_bits[8]	auto[0]	auto[0]	9762370	1			T20	255038		T21	1		T22	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	302426	1			T20	8269		T1	21		T13	29
bins_for_gpio_bits[8]	auto[1]	auto[0]	302659	1			T20	8272		T1	21		T13	28
bins_for_gpio_bits[8]	auto[1]	auto[1]	6162801	1			T20	120213		T23	25640		T1	444
bins_for_gpio_bits[9]	auto[0]	auto[0]	9760593	1			T20	254804		T21	1		T22	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	301140	1			T20	8151		T1	20		T13	18
bins_for_gpio_bits[9]	auto[1]	auto[0]	301359	1			T20	8154		T1	20		T13	18
bins_for_gpio_bits[9]	auto[1]	auto[1]	6167164	1			T20	120683		T23	25955		T1	478
bins_for_gpio_bits[10]	auto[0]	auto[0]	9751616	1			T20	254293		T21	1		T22	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	301554	1			T20	8247		T1	22		T13	21
bins_for_gpio_bits[10]	auto[1]	auto[0]	301797	1			T20	8249		T1	22		T13	21
bins_for_gpio_bits[10]	auto[1]	auto[1]	6175289	1			T20	121003		T23	25021		T1	489
bins_for_gpio_bits[11]	auto[0]	auto[0]	9758364	1			T20	254010		T21	1		T22	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	301284	1			T20	8285		T1	21		T13	24
bins_for_gpio_bits[11]	auto[1]	auto[0]	301526	1			T20	8287		T1	21		T13	24
bins_for_gpio_bits[11]	auto[1]	auto[1]	6169082	1			T20	121210		T23	25407		T1	452
bins_for_gpio_bits[12]	auto[0]	auto[0]	9759420	1			T20	254653		T21	1		T22	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	300908	1			T20	8196		T1	14		T13	22
bins_for_gpio_bits[12]	auto[1]	auto[0]	301166	1			T20	8196		T1	14		T13	22
bins_for_gpio_bits[12]	auto[1]	auto[1]	6168762	1			T20	120747		T23	24283		T1	547
bins_for_gpio_bits[13]	auto[0]	auto[0]	9752543	1			T20	255031		T21	1		T22	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	301852	1			T20	8235		T1	24		T13	15
bins_for_gpio_bits[13]	auto[1]	auto[0]	302107	1			T20	8238		T1	24		T13	15
bins_for_gpio_bits[13]	auto[1]	auto[1]	6173754	1			T20	120288		T23	26036		T1	418
bins_for_gpio_bits[14]	auto[0]	auto[0]	9749008	1			T20	254165		T21	1		T22	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	301439	1			T20	8437		T1	20		T13	22
bins_for_gpio_bits[14]	auto[1]	auto[0]	301667	1			T20	8439		T1	20		T13	21
bins_for_gpio_bits[14]	auto[1]	auto[1]	6178142	1			T20	120751		T23	25548		T1	499
bins_for_gpio_bits[15]	auto[0]	auto[0]	9756842	1			T20	254681		T21	1		T22	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	301486	1			T20	8287		T1	18		T13	16
bins_for_gpio_bits[15]	auto[1]	auto[0]	301724	1			T20	8289		T1	18		T13	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	6170204	1			T20	120535		T23	24720		T1	533
bins_for_gpio_bits[16]	auto[0]	auto[0]	9755530	1			T20	254720		T21	1		T22	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	301966	1			T20	8268		T1	22		T13	26
bins_for_gpio_bits[16]	auto[1]	auto[0]	302229	1			T20	8270		T1	22		T13	26
bins_for_gpio_bits[16]	auto[1]	auto[1]	6170531	1			T20	120534		T23	24157		T1	426
bins_for_gpio_bits[17]	auto[0]	auto[0]	9756928	1			T20	254329		T21	1		T22	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	301695	1			T20	8272		T1	11		T13	18
bins_for_gpio_bits[17]	auto[1]	auto[0]	301940	1			T20	8274		T1	11		T13	18
bins_for_gpio_bits[17]	auto[1]	auto[1]	6169693	1			T20	120917		T23	25404		T1	537
bins_for_gpio_bits[18]	auto[0]	auto[0]	9760153	1			T20	254083		T21	1		T22	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	301696	1			T20	8413		T1	16		T13	13
bins_for_gpio_bits[18]	auto[1]	auto[0]	301944	1			T20	8413		T1	16		T13	13
bins_for_gpio_bits[18]	auto[1]	auto[1]	6166463	1			T20	120883		T23	25121		T1	479
bins_for_gpio_bits[19]	auto[0]	auto[0]	9746017	1			T20	253867		T21	1		T22	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	301719	1			T20	8379		T1	20		T13	26
bins_for_gpio_bits[19]	auto[1]	auto[0]	301943	1			T20	8382		T1	20		T13	25
bins_for_gpio_bits[19]	auto[1]	auto[1]	6180577	1			T20	121164		T23	26403		T1	472
bins_for_gpio_bits[20]	auto[0]	auto[0]	9759477	1			T20	254344		T21	1		T22	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	301894	1			T20	8316		T1	20		T13	17
bins_for_gpio_bits[20]	auto[1]	auto[0]	302138	1			T20	8316		T1	20		T13	16
bins_for_gpio_bits[20]	auto[1]	auto[1]	6166747	1			T20	120816		T23	25399		T1	442
bins_for_gpio_bits[21]	auto[0]	auto[0]	9771020	1			T20	253846		T21	1		T22	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	301477	1			T20	8355		T1	15		T13	28
bins_for_gpio_bits[21]	auto[1]	auto[0]	301760	1			T20	8359		T1	15		T13	28
bins_for_gpio_bits[21]	auto[1]	auto[1]	6155999	1			T20	121232		T23	24443		T1	530
bins_for_gpio_bits[22]	auto[0]	auto[0]	9754246	1			T20	254315		T21	1		T22	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	301892	1			T20	8294		T1	19		T13	24
bins_for_gpio_bits[22]	auto[1]	auto[0]	302127	1			T20	8294		T1	19		T13	23
bins_for_gpio_bits[22]	auto[1]	auto[1]	6171991	1			T20	120889		T23	26996		T1	506
bins_for_gpio_bits[23]	auto[0]	auto[0]	9748022	1			T20	254643		T21	1		T22	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	302514	1			T20	8279		T1	23		T13	16
bins_for_gpio_bits[23]	auto[1]	auto[0]	302756	1			T20	8280		T1	23		T13	16
bins_for_gpio_bits[23]	auto[1]	auto[1]	6176964	1			T20	120590		T23	24220		T1	486
bins_for_gpio_bits[24]	auto[0]	auto[0]	9764802	1			T20	255624		T21	1		T22	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	301110	1			T20	8306		T1	23		T13	25
bins_for_gpio_bits[24]	auto[1]	auto[0]	301362	1			T20	8308		T1	23		T13	25
bins_for_gpio_bits[24]	auto[1]	auto[1]	6162982	1			T20	119554		T23	24209		T1	450
bins_for_gpio_bits[25]	auto[0]	auto[0]	9755700	1			T20	253995		T21	1		T22	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	302267	1			T20	8370		T1	19		T13	14
bins_for_gpio_bits[25]	auto[1]	auto[0]	302533	1			T20	8371		T1	19		T13	14
bins_for_gpio_bits[25]	auto[1]	auto[1]	6169756	1			T20	121056		T23	24744		T1	516
bins_for_gpio_bits[26]	auto[0]	auto[0]	9752266	1			T20	254449		T21	1		T22	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	301741	1			T20	8269		T1	24		T13	16
bins_for_gpio_bits[26]	auto[1]	auto[0]	301961	1			T20	8271		T1	24		T13	16
bins_for_gpio_bits[26]	auto[1]	auto[1]	6174288	1			T20	120803		T23	24548		T1	422
bins_for_gpio_bits[27]	auto[0]	auto[0]	9758983	1			T20	255061		T21	1		T22	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	301477	1			T20	8226		T1	22		T13	17
bins_for_gpio_bits[27]	auto[1]	auto[0]	301753	1			T20	8228		T1	22		T13	17
bins_for_gpio_bits[27]	auto[1]	auto[1]	6168043	1			T20	120277		T23	23140		T1	479
bins_for_gpio_bits[28]	auto[0]	auto[0]	9753049	1			T20	254859		T21	1		T22	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	302491	1			T20	8277		T1	21		T13	23
bins_for_gpio_bits[28]	auto[1]	auto[0]	302797	1			T20	8278		T1	21		T13	23
bins_for_gpio_bits[28]	auto[1]	auto[1]	6171919	1			T20	120378		T23	25238		T1	475
bins_for_gpio_bits[29]	auto[0]	auto[0]	9754481	1			T20	254458		T21	1		T22	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	301873	1			T20	8327		T1	17		T13	24
bins_for_gpio_bits[29]	auto[1]	auto[0]	302120	1			T20	8331		T1	17		T13	24
bins_for_gpio_bits[29]	auto[1]	auto[1]	6171782	1			T20	120676		T23	24896		T1	500
bins_for_gpio_bits[30]	auto[0]	auto[0]	9755448	1			T20	255069		T21	1		T22	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	301315	1			T20	8312		T1	18		T13	19
bins_for_gpio_bits[30]	auto[1]	auto[0]	301561	1			T20	8313		T1	18		T13	19
bins_for_gpio_bits[30]	auto[1]	auto[1]	6171932	1			T20	120098		T23	24643		T1	503
bins_for_gpio_bits[31]	auto[0]	auto[0]	9762998	1			T20	254921		T21	1		T22	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	301379	1			T20	8313		T1	20		T13	21
bins_for_gpio_bits[31]	auto[1]	auto[0]	301630	1			T20	8316		T1	20		T13	21
bins_for_gpio_bits[31]	auto[1]	auto[1]	6164249	1			T20	120242		T23	24582		T1	446