Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9432562 |
1 |
|
|
T20 |
193852 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7343753 |
1 |
|
|
T20 |
195368 |
|
T1 |
304 |
|
T11 |
1477 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15851284 |
1 |
|
|
T20 |
364699 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
925031 |
1 |
|
|
T20 |
24521 |
|
T1 |
15 |
|
T11 |
230 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9466563 |
1 |
|
|
T20 |
191806 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7309752 |
1 |
|
|
T20 |
197414 |
|
T1 |
374 |
|
T11 |
1128 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3195133 |
1 |
|
|
T20 |
84077 |
|
T1 |
180 |
|
T11 |
375 |
| auto[1] |
auto[0] |
auto[1] |
461987 |
1 |
|
|
T20 |
11829 |
|
T1 |
8 |
|
T11 |
92 |
| auto[1] |
auto[1] |
auto[0] |
3189588 |
1 |
|
|
T20 |
88816 |
|
T1 |
179 |
|
T11 |
523 |
| auto[1] |
auto[1] |
auto[1] |
463044 |
1 |
|
|
T20 |
12692 |
|
T1 |
7 |
|
T11 |
138 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9406402 |
1 |
|
|
T20 |
196225 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7369913 |
1 |
|
|
T20 |
192995 |
|
T1 |
432 |
|
T11 |
1333 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15842397 |
1 |
|
|
T20 |
365244 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
933918 |
1 |
|
|
T20 |
23976 |
|
T1 |
18 |
|
T11 |
319 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9417111 |
1 |
|
|
T20 |
194408 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7359204 |
1 |
|
|
T20 |
194812 |
|
T1 |
397 |
|
T11 |
1595 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3204691 |
1 |
|
|
T20 |
86091 |
|
T1 |
139 |
|
T11 |
476 |
| auto[1] |
auto[0] |
auto[1] |
465120 |
1 |
|
|
T20 |
12037 |
|
T1 |
8 |
|
T11 |
131 |
| auto[1] |
auto[1] |
auto[0] |
3220595 |
1 |
|
|
T20 |
84745 |
|
T1 |
240 |
|
T11 |
800 |
| auto[1] |
auto[1] |
auto[1] |
468798 |
1 |
|
|
T20 |
11939 |
|
T1 |
10 |
|
T11 |
188 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9484030 |
1 |
|
|
T20 |
192595 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7292285 |
1 |
|
|
T20 |
196625 |
|
T1 |
344 |
|
T11 |
1122 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15848552 |
1 |
|
|
T20 |
365723 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
927763 |
1 |
|
|
T20 |
23497 |
|
T1 |
12 |
|
T11 |
245 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9457509 |
1 |
|
|
T20 |
197234 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7318806 |
1 |
|
|
T20 |
191986 |
|
T1 |
291 |
|
T11 |
1237 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3209380 |
1 |
|
|
T20 |
83167 |
|
T1 |
118 |
|
T11 |
570 |
| auto[1] |
auto[0] |
auto[1] |
466907 |
1 |
|
|
T20 |
11495 |
|
T1 |
6 |
|
T11 |
135 |
| auto[1] |
auto[1] |
auto[0] |
3181663 |
1 |
|
|
T20 |
85322 |
|
T1 |
161 |
|
T11 |
422 |
| auto[1] |
auto[1] |
auto[1] |
460856 |
1 |
|
|
T20 |
12002 |
|
T1 |
6 |
|
T11 |
110 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9467597 |
1 |
|
|
T20 |
199699 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7308718 |
1 |
|
|
T20 |
189521 |
|
T1 |
282 |
|
T11 |
1420 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15845377 |
1 |
|
|
T20 |
365356 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
930938 |
1 |
|
|
T20 |
23864 |
|
T1 |
15 |
|
T11 |
276 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9434905 |
1 |
|
|
T20 |
195968 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7341410 |
1 |
|
|
T20 |
193252 |
|
T1 |
302 |
|
T11 |
1393 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3203240 |
1 |
|
|
T20 |
87695 |
|
T1 |
179 |
|
T11 |
526 |
| auto[1] |
auto[0] |
auto[1] |
464604 |
1 |
|
|
T20 |
12470 |
|
T1 |
9 |
|
T11 |
121 |
| auto[1] |
auto[1] |
auto[0] |
3207232 |
1 |
|
|
T20 |
81693 |
|
T1 |
108 |
|
T11 |
591 |
| auto[1] |
auto[1] |
auto[1] |
466334 |
1 |
|
|
T20 |
11394 |
|
T1 |
6 |
|
T11 |
155 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9474569 |
1 |
|
|
T20 |
193865 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7301746 |
1 |
|
|
T20 |
195355 |
|
T1 |
321 |
|
T11 |
984 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15839956 |
1 |
|
|
T20 |
364672 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
936359 |
1 |
|
|
T20 |
24548 |
|
T1 |
12 |
|
T11 |
266 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9389827 |
1 |
|
|
T20 |
192823 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7386488 |
1 |
|
|
T20 |
196397 |
|
T1 |
434 |
|
T11 |
1336 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3246046 |
1 |
|
|
T20 |
84196 |
|
T1 |
223 |
|
T11 |
568 |
| auto[1] |
auto[0] |
auto[1] |
471517 |
1 |
|
|
T20 |
12043 |
|
T1 |
7 |
|
T11 |
143 |
| auto[1] |
auto[1] |
auto[0] |
3204083 |
1 |
|
|
T20 |
87653 |
|
T1 |
199 |
|
T11 |
502 |
| auto[1] |
auto[1] |
auto[1] |
464842 |
1 |
|
|
T20 |
12505 |
|
T1 |
5 |
|
T11 |
123 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9440575 |
1 |
|
|
T20 |
198972 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7335740 |
1 |
|
|
T20 |
190248 |
|
T1 |
364 |
|
T11 |
1267 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15853150 |
1 |
|
|
T20 |
364655 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
923165 |
1 |
|
|
T20 |
24565 |
|
T1 |
9 |
|
T11 |
255 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9493085 |
1 |
|
|
T20 |
190719 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7283230 |
1 |
|
|
T20 |
198501 |
|
T1 |
282 |
|
T11 |
1314 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3174669 |
1 |
|
|
T20 |
88328 |
|
T1 |
133 |
|
T11 |
455 |
| auto[1] |
auto[0] |
auto[1] |
460627 |
1 |
|
|
T20 |
12536 |
|
T1 |
6 |
|
T11 |
107 |
| auto[1] |
auto[1] |
auto[0] |
3185396 |
1 |
|
|
T20 |
85608 |
|
T1 |
140 |
|
T11 |
604 |
| auto[1] |
auto[1] |
auto[1] |
462538 |
1 |
|
|
T20 |
12029 |
|
T1 |
3 |
|
T11 |
148 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9467705 |
1 |
|
|
T20 |
196036 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7308610 |
1 |
|
|
T20 |
193184 |
|
T1 |
399 |
|
T11 |
1248 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15850915 |
1 |
|
|
T20 |
365582 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
925400 |
1 |
|
|
T20 |
23638 |
|
T1 |
17 |
|
T11 |
276 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9464427 |
1 |
|
|
T20 |
196537 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7311888 |
1 |
|
|
T20 |
192683 |
|
T1 |
297 |
|
T11 |
1412 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3191025 |
1 |
|
|
T20 |
85775 |
|
T1 |
108 |
|
T11 |
513 |
| auto[1] |
auto[0] |
auto[1] |
462453 |
1 |
|
|
T20 |
12211 |
|
T1 |
5 |
|
T11 |
121 |
| auto[1] |
auto[1] |
auto[0] |
3195463 |
1 |
|
|
T20 |
83270 |
|
T1 |
172 |
|
T11 |
623 |
| auto[1] |
auto[1] |
auto[1] |
462947 |
1 |
|
|
T20 |
11427 |
|
T1 |
12 |
|
T11 |
155 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9448929 |
1 |
|
|
T20 |
195803 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7327386 |
1 |
|
|
T20 |
193417 |
|
T1 |
387 |
|
T11 |
1281 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15851252 |
1 |
|
|
T20 |
365729 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
925063 |
1 |
|
|
T20 |
23491 |
|
T1 |
8 |
|
T11 |
221 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9467905 |
1 |
|
|
T20 |
197681 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7308410 |
1 |
|
|
T20 |
191539 |
|
T1 |
270 |
|
T11 |
1203 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3191591 |
1 |
|
|
T20 |
82958 |
|
T1 |
137 |
|
T11 |
444 |
| auto[1] |
auto[0] |
auto[1] |
461378 |
1 |
|
|
T20 |
11271 |
|
T1 |
2 |
|
T11 |
92 |
| auto[1] |
auto[1] |
auto[0] |
3191756 |
1 |
|
|
T20 |
85090 |
|
T1 |
125 |
|
T11 |
538 |
| auto[1] |
auto[1] |
auto[1] |
463685 |
1 |
|
|
T20 |
12220 |
|
T1 |
6 |
|
T11 |
129 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9470912 |
1 |
|
|
T20 |
196754 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7305403 |
1 |
|
|
T20 |
192466 |
|
T1 |
324 |
|
T11 |
1384 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15855153 |
1 |
|
|
T20 |
366325 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
921162 |
1 |
|
|
T20 |
22895 |
|
T1 |
13 |
|
T11 |
165 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9484975 |
1 |
|
|
T20 |
201334 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7291340 |
1 |
|
|
T20 |
187886 |
|
T1 |
276 |
|
T11 |
852 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3190444 |
1 |
|
|
T20 |
87196 |
|
T1 |
126 |
|
T11 |
252 |
| auto[1] |
auto[0] |
auto[1] |
459853 |
1 |
|
|
T20 |
12250 |
|
T1 |
5 |
|
T11 |
66 |
| auto[1] |
auto[1] |
auto[0] |
3179734 |
1 |
|
|
T20 |
77795 |
|
T1 |
137 |
|
T11 |
435 |
| auto[1] |
auto[1] |
auto[1] |
461309 |
1 |
|
|
T20 |
10645 |
|
T1 |
8 |
|
T11 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9440270 |
1 |
|
|
T20 |
190349 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7336045 |
1 |
|
|
T20 |
198871 |
|
T1 |
240 |
|
T11 |
1079 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15849317 |
1 |
|
|
T20 |
365103 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
926998 |
1 |
|
|
T20 |
24117 |
|
T1 |
8 |
|
T11 |
227 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9454557 |
1 |
|
|
T20 |
194808 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7321758 |
1 |
|
|
T20 |
194412 |
|
T1 |
297 |
|
T11 |
1163 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3186965 |
1 |
|
|
T20 |
80550 |
|
T1 |
208 |
|
T11 |
560 |
| auto[1] |
auto[0] |
auto[1] |
460339 |
1 |
|
|
T20 |
11351 |
|
T1 |
5 |
|
T11 |
140 |
| auto[1] |
auto[1] |
auto[0] |
3207795 |
1 |
|
|
T20 |
89745 |
|
T1 |
81 |
|
T11 |
376 |
| auto[1] |
auto[1] |
auto[1] |
466659 |
1 |
|
|
T20 |
12766 |
|
T1 |
3 |
|
T11 |
87 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9504996 |
1 |
|
|
T20 |
198887 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7271319 |
1 |
|
|
T20 |
190333 |
|
T1 |
302 |
|
T11 |
679 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15848047 |
1 |
|
|
T20 |
365542 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
928268 |
1 |
|
|
T20 |
23678 |
|
T1 |
15 |
|
T11 |
237 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9452216 |
1 |
|
|
T20 |
196354 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7324099 |
1 |
|
|
T20 |
192866 |
|
T1 |
460 |
|
T11 |
1132 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3237753 |
1 |
|
|
T20 |
86412 |
|
T1 |
275 |
|
T11 |
658 |
| auto[1] |
auto[0] |
auto[1] |
471122 |
1 |
|
|
T20 |
12063 |
|
T1 |
10 |
|
T11 |
166 |
| auto[1] |
auto[1] |
auto[0] |
3158078 |
1 |
|
|
T20 |
82776 |
|
T1 |
170 |
|
T11 |
237 |
| auto[1] |
auto[1] |
auto[1] |
457146 |
1 |
|
|
T20 |
11615 |
|
T1 |
5 |
|
T11 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9491054 |
1 |
|
|
T20 |
201323 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7285261 |
1 |
|
|
T20 |
187897 |
|
T1 |
253 |
|
T11 |
1469 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15848880 |
1 |
|
|
T20 |
365088 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
927435 |
1 |
|
|
T20 |
24132 |
|
T1 |
9 |
|
T11 |
225 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9450995 |
1 |
|
|
T20 |
193275 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7325320 |
1 |
|
|
T20 |
195945 |
|
T1 |
221 |
|
T11 |
1212 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3210698 |
1 |
|
|
T20 |
87515 |
|
T1 |
69 |
|
T11 |
403 |
| auto[1] |
auto[0] |
auto[1] |
465427 |
1 |
|
|
T20 |
12164 |
|
T1 |
5 |
|
T11 |
93 |
| auto[1] |
auto[1] |
auto[0] |
3187187 |
1 |
|
|
T20 |
84298 |
|
T1 |
143 |
|
T11 |
584 |
| auto[1] |
auto[1] |
auto[1] |
462008 |
1 |
|
|
T20 |
11968 |
|
T1 |
4 |
|
T11 |
132 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9429071 |
1 |
|
|
T20 |
190906 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7347244 |
1 |
|
|
T20 |
198314 |
|
T1 |
301 |
|
T11 |
1253 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15851672 |
1 |
|
|
T20 |
366174 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
924643 |
1 |
|
|
T20 |
23046 |
|
T1 |
14 |
|
T11 |
266 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9476829 |
1 |
|
|
T20 |
199180 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7299486 |
1 |
|
|
T20 |
190040 |
|
T1 |
510 |
|
T11 |
1389 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3186674 |
1 |
|
|
T20 |
85521 |
|
T1 |
306 |
|
T11 |
524 |
| auto[1] |
auto[0] |
auto[1] |
460927 |
1 |
|
|
T20 |
11876 |
|
T1 |
3 |
|
T11 |
130 |
| auto[1] |
auto[1] |
auto[0] |
3188169 |
1 |
|
|
T20 |
81473 |
|
T1 |
190 |
|
T11 |
599 |
| auto[1] |
auto[1] |
auto[1] |
463716 |
1 |
|
|
T20 |
11170 |
|
T1 |
11 |
|
T11 |
136 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9473101 |
1 |
|
|
T20 |
197546 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7303214 |
1 |
|
|
T20 |
191674 |
|
T1 |
511 |
|
T11 |
1111 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15847324 |
1 |
|
|
T20 |
365800 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
928991 |
1 |
|
|
T20 |
23420 |
|
T1 |
16 |
|
T11 |
285 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9445089 |
1 |
|
|
T20 |
198357 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7331226 |
1 |
|
|
T20 |
190863 |
|
T1 |
406 |
|
T11 |
1422 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3207634 |
1 |
|
|
T20 |
87335 |
|
T1 |
121 |
|
T11 |
551 |
| auto[1] |
auto[0] |
auto[1] |
466357 |
1 |
|
|
T20 |
12278 |
|
T1 |
4 |
|
T11 |
145 |
| auto[1] |
auto[1] |
auto[0] |
3194601 |
1 |
|
|
T20 |
80108 |
|
T1 |
269 |
|
T11 |
586 |
| auto[1] |
auto[1] |
auto[1] |
462634 |
1 |
|
|
T20 |
11142 |
|
T1 |
12 |
|
T11 |
140 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9439781 |
1 |
|
|
T20 |
199870 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7336534 |
1 |
|
|
T20 |
189350 |
|
T1 |
325 |
|
T11 |
1045 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15838581 |
1 |
|
|
T20 |
365217 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
937734 |
1 |
|
|
T20 |
24003 |
|
T1 |
11 |
|
T11 |
216 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9394319 |
1 |
|
|
T20 |
193714 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7381996 |
1 |
|
|
T20 |
195506 |
|
T1 |
338 |
|
T11 |
1109 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3210176 |
1 |
|
|
T20 |
85403 |
|
T1 |
176 |
|
T11 |
559 |
| auto[1] |
auto[0] |
auto[1] |
467411 |
1 |
|
|
T20 |
11899 |
|
T1 |
8 |
|
T11 |
134 |
| auto[1] |
auto[1] |
auto[0] |
3234086 |
1 |
|
|
T20 |
86100 |
|
T1 |
151 |
|
T11 |
334 |
| auto[1] |
auto[1] |
auto[1] |
470323 |
1 |
|
|
T20 |
12104 |
|
T1 |
3 |
|
T11 |
82 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9425688 |
1 |
|
|
T20 |
197870 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7350627 |
1 |
|
|
T20 |
191350 |
|
T1 |
415 |
|
T11 |
1264 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15851586 |
1 |
|
|
T20 |
365387 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
924729 |
1 |
|
|
T20 |
23833 |
|
T1 |
15 |
|
T11 |
222 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9486844 |
1 |
|
|
T20 |
195569 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7289471 |
1 |
|
|
T20 |
193651 |
|
T1 |
381 |
|
T11 |
1120 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3169195 |
1 |
|
|
T20 |
84670 |
|
T1 |
109 |
|
T11 |
391 |
| auto[1] |
auto[0] |
auto[1] |
459617 |
1 |
|
|
T20 |
11766 |
|
T1 |
3 |
|
T11 |
95 |
| auto[1] |
auto[1] |
auto[0] |
3195547 |
1 |
|
|
T20 |
85148 |
|
T1 |
257 |
|
T11 |
507 |
| auto[1] |
auto[1] |
auto[1] |
465112 |
1 |
|
|
T20 |
12067 |
|
T1 |
12 |
|
T11 |
127 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9452191 |
1 |
|
|
T20 |
195662 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7324124 |
1 |
|
|
T20 |
193558 |
|
T1 |
387 |
|
T11 |
1294 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15845629 |
1 |
|
|
T20 |
366083 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
930686 |
1 |
|
|
T20 |
23137 |
|
T1 |
13 |
|
T11 |
215 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9441497 |
1 |
|
|
T20 |
198003 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7334818 |
1 |
|
|
T20 |
191217 |
|
T1 |
340 |
|
T11 |
1120 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3200175 |
1 |
|
|
T20 |
86152 |
|
T1 |
151 |
|
T11 |
303 |
| auto[1] |
auto[0] |
auto[1] |
465815 |
1 |
|
|
T20 |
12083 |
|
T1 |
8 |
|
T11 |
70 |
| auto[1] |
auto[1] |
auto[0] |
3203957 |
1 |
|
|
T20 |
81928 |
|
T1 |
176 |
|
T11 |
602 |
| auto[1] |
auto[1] |
auto[1] |
464871 |
1 |
|
|
T20 |
11054 |
|
T1 |
5 |
|
T11 |
145 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9438863 |
1 |
|
|
T20 |
195263 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7337452 |
1 |
|
|
T20 |
193957 |
|
T1 |
392 |
|
T11 |
1307 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15849458 |
1 |
|
|
T20 |
366270 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
926857 |
1 |
|
|
T20 |
22950 |
|
T1 |
24 |
|
T11 |
202 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9456387 |
1 |
|
|
T20 |
200790 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7319928 |
1 |
|
|
T20 |
188430 |
|
T1 |
446 |
|
T11 |
1014 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3204174 |
1 |
|
|
T20 |
81576 |
|
T1 |
153 |
|
T11 |
465 |
| auto[1] |
auto[0] |
auto[1] |
464896 |
1 |
|
|
T20 |
11211 |
|
T1 |
11 |
|
T11 |
119 |
| auto[1] |
auto[1] |
auto[0] |
3188897 |
1 |
|
|
T20 |
83904 |
|
T1 |
269 |
|
T11 |
347 |
| auto[1] |
auto[1] |
auto[1] |
461961 |
1 |
|
|
T20 |
11739 |
|
T1 |
13 |
|
T11 |
83 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9428216 |
1 |
|
|
T20 |
197807 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7348099 |
1 |
|
|
T20 |
191413 |
|
T1 |
469 |
|
T11 |
1344 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15841406 |
1 |
|
|
T20 |
365758 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
934909 |
1 |
|
|
T20 |
23462 |
|
T1 |
16 |
|
T11 |
259 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9408866 |
1 |
|
|
T20 |
197708 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7367449 |
1 |
|
|
T20 |
191512 |
|
T1 |
372 |
|
T11 |
1285 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3194801 |
1 |
|
|
T20 |
85892 |
|
T1 |
93 |
|
T11 |
403 |
| auto[1] |
auto[0] |
auto[1] |
462551 |
1 |
|
|
T20 |
12001 |
|
T1 |
5 |
|
T11 |
93 |
| auto[1] |
auto[1] |
auto[0] |
3237739 |
1 |
|
|
T20 |
82158 |
|
T1 |
263 |
|
T11 |
623 |
| auto[1] |
auto[1] |
auto[1] |
472358 |
1 |
|
|
T20 |
11461 |
|
T1 |
11 |
|
T11 |
166 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |