Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9483103 |
1 |
|
|
T20 |
201042 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7293212 |
1 |
|
|
T20 |
188178 |
|
T1 |
395 |
|
T11 |
1182 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15846200 |
1 |
|
|
T20 |
364722 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
930115 |
1 |
|
|
T20 |
24498 |
|
T1 |
17 |
|
T11 |
191 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9439850 |
1 |
|
|
T20 |
189177 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7336465 |
1 |
|
|
T20 |
200043 |
|
T1 |
494 |
|
T11 |
972 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3216284 |
1 |
|
|
T20 |
88631 |
|
T1 |
229 |
|
T11 |
374 |
| auto[1] |
auto[0] |
auto[1] |
466915 |
1 |
|
|
T20 |
12523 |
|
T1 |
9 |
|
T11 |
96 |
| auto[1] |
auto[1] |
auto[0] |
3190066 |
1 |
|
|
T20 |
86914 |
|
T1 |
248 |
|
T11 |
407 |
| auto[1] |
auto[1] |
auto[1] |
463200 |
1 |
|
|
T20 |
11975 |
|
T1 |
8 |
|
T11 |
95 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |