Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9477646 |
1 |
|
|
T20 |
195015 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7298669 |
1 |
|
|
T20 |
194205 |
|
T1 |
265 |
|
T11 |
1119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15848487 |
1 |
|
|
T20 |
365748 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
927828 |
1 |
|
|
T20 |
23472 |
|
T1 |
10 |
|
T11 |
258 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9451356 |
1 |
|
|
T20 |
197675 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7324959 |
1 |
|
|
T20 |
191545 |
|
T1 |
258 |
|
T11 |
1323 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3212500 |
1 |
|
|
T20 |
84056 |
|
T1 |
138 |
|
T11 |
533 |
| auto[1] |
auto[0] |
auto[1] |
466366 |
1 |
|
|
T20 |
11670 |
|
T1 |
5 |
|
T11 |
127 |
| auto[1] |
auto[1] |
auto[0] |
3184631 |
1 |
|
|
T20 |
84017 |
|
T1 |
110 |
|
T11 |
532 |
| auto[1] |
auto[1] |
auto[1] |
461462 |
1 |
|
|
T20 |
11802 |
|
T1 |
5 |
|
T11 |
131 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |