Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9427806 |
1 |
|
|
T20 |
187484 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7348509 |
1 |
|
|
T20 |
201736 |
|
T1 |
360 |
|
T11 |
1288 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15850506 |
1 |
|
|
T20 |
365795 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
925809 |
1 |
|
|
T20 |
23425 |
|
T1 |
20 |
|
T11 |
221 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9462120 |
1 |
|
|
T20 |
196433 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7314195 |
1 |
|
|
T20 |
192787 |
|
T1 |
384 |
|
T11 |
1104 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3187788 |
1 |
|
|
T20 |
80495 |
|
T1 |
184 |
|
T11 |
406 |
| auto[1] |
auto[0] |
auto[1] |
461482 |
1 |
|
|
T20 |
11117 |
|
T1 |
12 |
|
T11 |
99 |
| auto[1] |
auto[1] |
auto[0] |
3200598 |
1 |
|
|
T20 |
88867 |
|
T1 |
180 |
|
T11 |
477 |
| auto[1] |
auto[1] |
auto[1] |
464327 |
1 |
|
|
T20 |
12308 |
|
T1 |
8 |
|
T11 |
122 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |