Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9420361 |
1 |
|
|
T20 |
194610 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7355954 |
1 |
|
|
T20 |
194610 |
|
T1 |
423 |
|
T11 |
1243 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15848942 |
1 |
|
|
T20 |
364904 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
927373 |
1 |
|
|
T20 |
24316 |
|
T1 |
7 |
|
T11 |
277 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9474669 |
1 |
|
|
T20 |
190371 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7301646 |
1 |
|
|
T20 |
198849 |
|
T1 |
248 |
|
T11 |
1435 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3186871 |
1 |
|
|
T20 |
85968 |
|
T1 |
77 |
|
T11 |
555 |
| auto[1] |
auto[0] |
auto[1] |
463761 |
1 |
|
|
T20 |
11798 |
|
T1 |
1 |
|
T11 |
122 |
| auto[1] |
auto[1] |
auto[0] |
3187402 |
1 |
|
|
T20 |
88565 |
|
T1 |
164 |
|
T11 |
603 |
| auto[1] |
auto[1] |
auto[1] |
463612 |
1 |
|
|
T20 |
12518 |
|
T1 |
6 |
|
T11 |
155 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |