Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9406402 |
1 |
|
|
T20 |
196225 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
7369913 |
1 |
|
|
T20 |
192995 |
|
T1 |
432 |
|
T11 |
1333 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13809227 |
1 |
|
|
T20 |
317681 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
2967088 |
1 |
|
|
T20 |
71539 |
|
T1 |
258 |
|
T11 |
665 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9436772 |
1 |
|
|
T20 |
194267 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
7339543 |
1 |
|
|
T20 |
194953 |
|
T1 |
345 |
|
T11 |
1345 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2164746 |
1 |
|
|
T20 |
61347 |
|
T1 |
37 |
|
T11 |
309 |
auto[1] |
auto[0] |
auto[1] |
1468233 |
1 |
|
|
T20 |
34994 |
|
T1 |
120 |
|
T11 |
313 |
auto[1] |
auto[1] |
auto[0] |
2207709 |
1 |
|
|
T20 |
62067 |
|
T1 |
50 |
|
T11 |
371 |
auto[1] |
auto[1] |
auto[1] |
1498855 |
1 |
|
|
T20 |
36545 |
|
T1 |
138 |
|
T11 |
352 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |