Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9474569 |
1 |
|
|
T20 |
193865 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7301746 |
1 |
|
|
T20 |
195355 |
|
T1 |
321 |
|
T11 |
984 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13828128 |
1 |
|
|
T20 |
316643 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
2948187 |
1 |
|
|
T20 |
72577 |
|
T1 |
284 |
|
T11 |
797 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9487397 |
1 |
|
|
T20 |
189955 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7288918 |
1 |
|
|
T20 |
199265 |
|
T1 |
330 |
|
T11 |
1585 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2168725 |
1 |
|
|
T20 |
63071 |
|
T1 |
26 |
|
T11 |
532 |
| auto[1] |
auto[0] |
auto[1] |
1480960 |
1 |
|
|
T20 |
36157 |
|
T1 |
122 |
|
T11 |
512 |
| auto[1] |
auto[1] |
auto[0] |
2172006 |
1 |
|
|
T20 |
63617 |
|
T1 |
20 |
|
T11 |
256 |
| auto[1] |
auto[1] |
auto[1] |
1467227 |
1 |
|
|
T20 |
36420 |
|
T1 |
162 |
|
T11 |
285 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |