Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9499016 |
1 |
|
|
T20 |
197717 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7277299 |
1 |
|
|
T20 |
191503 |
|
T1 |
422 |
|
T11 |
1250 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15847705 |
1 |
|
|
T20 |
365926 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
928610 |
1 |
|
|
T20 |
23294 |
|
T1 |
17 |
|
T11 |
223 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9445226 |
1 |
|
|
T20 |
199484 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7331089 |
1 |
|
|
T20 |
189736 |
|
T1 |
377 |
|
T11 |
1131 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3216962 |
1 |
|
|
T20 |
84217 |
|
T1 |
127 |
|
T11 |
501 |
| auto[1] |
auto[0] |
auto[1] |
467033 |
1 |
|
|
T20 |
11745 |
|
T1 |
6 |
|
T11 |
125 |
| auto[1] |
auto[1] |
auto[0] |
3185517 |
1 |
|
|
T20 |
82225 |
|
T1 |
233 |
|
T11 |
407 |
| auto[1] |
auto[1] |
auto[1] |
461577 |
1 |
|
|
T20 |
11549 |
|
T1 |
11 |
|
T11 |
98 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |