Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9440575 |
1 |
|
|
T20 |
198972 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7335740 |
1 |
|
|
T20 |
190248 |
|
T1 |
364 |
|
T11 |
1267 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13822428 |
1 |
|
|
T20 |
321043 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
2953887 |
1 |
|
|
T20 |
68177 |
|
T1 |
164 |
|
T11 |
522 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9481857 |
1 |
|
|
T20 |
203788 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7294458 |
1 |
|
|
T20 |
185432 |
|
T1 |
225 |
|
T11 |
1025 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2161684 |
1 |
|
|
T20 |
60911 |
|
T1 |
33 |
|
T11 |
261 |
| auto[1] |
auto[0] |
auto[1] |
1476434 |
1 |
|
|
T20 |
35025 |
|
T1 |
91 |
|
T11 |
260 |
| auto[1] |
auto[1] |
auto[0] |
2178887 |
1 |
|
|
T20 |
56344 |
|
T1 |
28 |
|
T11 |
242 |
| auto[1] |
auto[1] |
auto[1] |
1477453 |
1 |
|
|
T20 |
33152 |
|
T1 |
73 |
|
T11 |
262 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |