Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9467705 |
1 |
|
|
T20 |
196036 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
7308610 |
1 |
|
|
T20 |
193184 |
|
T1 |
399 |
|
T11 |
1248 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
13814560 |
1 |
|
|
T20 |
319988 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
2961755 |
1 |
|
|
T20 |
69232 |
|
T1 |
310 |
|
T11 |
662 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9448464 |
1 |
|
|
T20 |
200133 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
7327851 |
1 |
|
|
T20 |
189087 |
|
T1 |
385 |
|
T11 |
1317 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2182755 |
1 |
|
|
T20 |
59618 |
|
T1 |
19 |
|
T11 |
351 |
auto[1] |
auto[0] |
auto[1] |
1481313 |
1 |
|
|
T20 |
34764 |
|
T1 |
158 |
|
T11 |
396 |
auto[1] |
auto[1] |
auto[0] |
2183341 |
1 |
|
|
T20 |
60237 |
|
T1 |
56 |
|
T11 |
304 |
auto[1] |
auto[1] |
auto[1] |
1480442 |
1 |
|
|
T20 |
34468 |
|
T1 |
152 |
|
T11 |
266 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |