Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9504996 |
1 |
|
|
T20 |
198887 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7271319 |
1 |
|
|
T20 |
190333 |
|
T1 |
302 |
|
T11 |
679 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13829357 |
1 |
|
|
T20 |
318035 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
2946958 |
1 |
|
|
T20 |
71185 |
|
T1 |
236 |
|
T11 |
660 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9461110 |
1 |
|
|
T20 |
193194 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7315205 |
1 |
|
|
T20 |
196026 |
|
T1 |
317 |
|
T11 |
1283 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2203213 |
1 |
|
|
T20 |
65077 |
|
T1 |
41 |
|
T11 |
433 |
| auto[1] |
auto[0] |
auto[1] |
1481253 |
1 |
|
|
T20 |
36472 |
|
T1 |
101 |
|
T11 |
477 |
| auto[1] |
auto[1] |
auto[0] |
2165034 |
1 |
|
|
T20 |
59764 |
|
T1 |
40 |
|
T11 |
190 |
| auto[1] |
auto[1] |
auto[1] |
1465705 |
1 |
|
|
T20 |
34713 |
|
T1 |
135 |
|
T11 |
183 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |