Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9491054 |
1 |
|
|
T20 |
201323 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7285261 |
1 |
|
|
T20 |
187897 |
|
T1 |
253 |
|
T11 |
1469 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13816088 |
1 |
|
|
T20 |
318179 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
2960227 |
1 |
|
|
T20 |
71041 |
|
T1 |
300 |
|
T11 |
705 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9452876 |
1 |
|
|
T20 |
196855 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7323439 |
1 |
|
|
T20 |
192365 |
|
T1 |
382 |
|
T11 |
1438 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2193081 |
1 |
|
|
T20 |
60451 |
|
T1 |
55 |
|
T11 |
264 |
| auto[1] |
auto[0] |
auto[1] |
1483106 |
1 |
|
|
T20 |
35199 |
|
T1 |
184 |
|
T11 |
257 |
| auto[1] |
auto[1] |
auto[0] |
2170131 |
1 |
|
|
T20 |
60873 |
|
T1 |
27 |
|
T11 |
469 |
| auto[1] |
auto[1] |
auto[1] |
1477121 |
1 |
|
|
T20 |
35842 |
|
T1 |
116 |
|
T11 |
448 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |