Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9473101 |
1 |
|
|
T20 |
197546 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7303214 |
1 |
|
|
T20 |
191674 |
|
T1 |
511 |
|
T11 |
1111 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13818661 |
1 |
|
|
T20 |
318813 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
2957654 |
1 |
|
|
T20 |
70407 |
|
T1 |
242 |
|
T11 |
582 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9449302 |
1 |
|
|
T20 |
196826 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7327013 |
1 |
|
|
T20 |
192394 |
|
T1 |
342 |
|
T11 |
1188 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2207678 |
1 |
|
|
T20 |
62406 |
|
T1 |
33 |
|
T11 |
293 |
| auto[1] |
auto[0] |
auto[1] |
1489934 |
1 |
|
|
T20 |
35200 |
|
T1 |
50 |
|
T11 |
303 |
| auto[1] |
auto[1] |
auto[0] |
2161681 |
1 |
|
|
T20 |
59581 |
|
T1 |
67 |
|
T11 |
313 |
| auto[1] |
auto[1] |
auto[1] |
1467720 |
1 |
|
|
T20 |
35207 |
|
T1 |
192 |
|
T11 |
279 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |