Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9431297 |
1 |
|
|
T20 |
200795 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7345018 |
1 |
|
|
T20 |
188425 |
|
T1 |
282 |
|
T11 |
1465 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15853178 |
1 |
|
|
T20 |
365416 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
923137 |
1 |
|
|
T20 |
23804 |
|
T1 |
9 |
|
T11 |
284 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9485374 |
1 |
|
|
T20 |
196146 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7290941 |
1 |
|
|
T20 |
193074 |
|
T1 |
313 |
|
T11 |
1432 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3173831 |
1 |
|
|
T20 |
86685 |
|
T1 |
165 |
|
T11 |
516 |
| auto[1] |
auto[0] |
auto[1] |
459498 |
1 |
|
|
T20 |
12240 |
|
T1 |
6 |
|
T11 |
122 |
| auto[1] |
auto[1] |
auto[0] |
3193973 |
1 |
|
|
T20 |
82585 |
|
T1 |
139 |
|
T11 |
632 |
| auto[1] |
auto[1] |
auto[1] |
463639 |
1 |
|
|
T20 |
11564 |
|
T1 |
3 |
|
T11 |
162 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |