Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9425688 |
1 |
|
|
T20 |
197870 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7350627 |
1 |
|
|
T20 |
191350 |
|
T1 |
415 |
|
T11 |
1264 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13839983 |
1 |
|
|
T20 |
321071 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
2936332 |
1 |
|
|
T20 |
68149 |
|
T1 |
223 |
|
T11 |
735 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9507740 |
1 |
|
|
T20 |
200742 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7268575 |
1 |
|
|
T20 |
188478 |
|
T1 |
278 |
|
T11 |
1384 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2159887 |
1 |
|
|
T20 |
60942 |
|
T1 |
11 |
|
T11 |
330 |
| auto[1] |
auto[0] |
auto[1] |
1467435 |
1 |
|
|
T20 |
34621 |
|
T1 |
114 |
|
T11 |
343 |
| auto[1] |
auto[1] |
auto[0] |
2172356 |
1 |
|
|
T20 |
59387 |
|
T1 |
44 |
|
T11 |
319 |
| auto[1] |
auto[1] |
auto[1] |
1468897 |
1 |
|
|
T20 |
33528 |
|
T1 |
109 |
|
T11 |
392 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |