Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9452191 |
1 |
|
|
T20 |
195662 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7324124 |
1 |
|
|
T20 |
193558 |
|
T1 |
387 |
|
T11 |
1294 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13825288 |
1 |
|
|
T20 |
316192 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
2951027 |
1 |
|
|
T20 |
73028 |
|
T1 |
269 |
|
T11 |
647 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9479208 |
1 |
|
|
T20 |
186913 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7297107 |
1 |
|
|
T20 |
202307 |
|
T1 |
328 |
|
T11 |
1297 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2168751 |
1 |
|
|
T20 |
63961 |
|
T1 |
17 |
|
T11 |
308 |
| auto[1] |
auto[0] |
auto[1] |
1478155 |
1 |
|
|
T20 |
36097 |
|
T1 |
96 |
|
T11 |
298 |
| auto[1] |
auto[1] |
auto[0] |
2177329 |
1 |
|
|
T20 |
65318 |
|
T1 |
42 |
|
T11 |
342 |
| auto[1] |
auto[1] |
auto[1] |
1472872 |
1 |
|
|
T20 |
36931 |
|
T1 |
173 |
|
T11 |
349 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |