Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9498098 |
1 |
|
|
T20 |
197297 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7278217 |
1 |
|
|
T20 |
191923 |
|
T1 |
476 |
|
T11 |
932 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15848924 |
1 |
|
|
T20 |
366470 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
927391 |
1 |
|
|
T20 |
22750 |
|
T1 |
8 |
|
T11 |
228 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9465428 |
1 |
|
|
T20 |
201763 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7310887 |
1 |
|
|
T20 |
187457 |
|
T1 |
262 |
|
T11 |
1155 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3217823 |
1 |
|
|
T20 |
83187 |
|
T1 |
140 |
|
T11 |
607 |
| auto[1] |
auto[0] |
auto[1] |
467417 |
1 |
|
|
T20 |
11483 |
|
T1 |
2 |
|
T11 |
148 |
| auto[1] |
auto[1] |
auto[0] |
3165673 |
1 |
|
|
T20 |
81520 |
|
T1 |
114 |
|
T11 |
320 |
| auto[1] |
auto[1] |
auto[1] |
459974 |
1 |
|
|
T20 |
11267 |
|
T1 |
6 |
|
T11 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |