Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9459391 |
1 |
|
|
T20 |
197762 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
7316924 |
1 |
|
|
T20 |
191458 |
|
T1 |
353 |
|
T11 |
1609 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15853998 |
1 |
|
|
T20 |
365504 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
922317 |
1 |
|
|
T20 |
23716 |
|
T1 |
11 |
|
T11 |
296 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9495180 |
1 |
|
|
T20 |
195766 |
|
T21 |
1 |
|
T22 |
1 |
auto[1] |
7281135 |
1 |
|
|
T20 |
193454 |
|
T1 |
273 |
|
T11 |
1520 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
3176768 |
1 |
|
|
T20 |
85540 |
|
T1 |
162 |
|
T11 |
432 |
auto[1] |
auto[0] |
auto[1] |
459252 |
1 |
|
|
T20 |
12032 |
|
T1 |
6 |
|
T11 |
97 |
auto[1] |
auto[1] |
auto[0] |
3182050 |
1 |
|
|
T20 |
84198 |
|
T1 |
100 |
|
T11 |
792 |
auto[1] |
auto[1] |
auto[1] |
463065 |
1 |
|
|
T20 |
11684 |
|
T1 |
5 |
|
T11 |
199 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |