Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9443194 |
1 |
|
|
T20 |
188266 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7333121 |
1 |
|
|
T20 |
200954 |
|
T1 |
364 |
|
T11 |
1140 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15850904 |
1 |
|
|
T20 |
366501 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
925411 |
1 |
|
|
T20 |
22719 |
|
T1 |
12 |
|
T11 |
198 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9468709 |
1 |
|
|
T20 |
200916 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7307606 |
1 |
|
|
T20 |
188304 |
|
T1 |
380 |
|
T11 |
1030 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3205798 |
1 |
|
|
T20 |
80419 |
|
T1 |
176 |
|
T11 |
427 |
| auto[1] |
auto[0] |
auto[1] |
465129 |
1 |
|
|
T20 |
10862 |
|
T1 |
4 |
|
T11 |
117 |
| auto[1] |
auto[1] |
auto[0] |
3176397 |
1 |
|
|
T20 |
85166 |
|
T1 |
192 |
|
T11 |
405 |
| auto[1] |
auto[1] |
auto[1] |
460282 |
1 |
|
|
T20 |
11857 |
|
T1 |
8 |
|
T11 |
81 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |