Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9427112 |
1 |
|
|
T20 |
194946 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7349203 |
1 |
|
|
T20 |
194274 |
|
T1 |
175 |
|
T11 |
1137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15851938 |
1 |
|
|
T20 |
365708 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
924377 |
1 |
|
|
T20 |
23512 |
|
T1 |
10 |
|
T11 |
206 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9481556 |
1 |
|
|
T20 |
197426 |
|
T21 |
1 |
|
T22 |
1 |
| auto[1] |
7294759 |
1 |
|
|
T20 |
191794 |
|
T1 |
440 |
|
T11 |
1040 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3190306 |
1 |
|
|
T20 |
84483 |
|
T1 |
334 |
|
T11 |
557 |
| auto[1] |
auto[0] |
auto[1] |
463882 |
1 |
|
|
T20 |
11885 |
|
T1 |
8 |
|
T11 |
135 |
| auto[1] |
auto[1] |
auto[0] |
3180076 |
1 |
|
|
T20 |
83799 |
|
T1 |
96 |
|
T11 |
277 |
| auto[1] |
auto[1] |
auto[1] |
460495 |
1 |
|
|
T20 |
11627 |
|
T1 |
2 |
|
T11 |
71 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |