Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
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T758 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2912931172 Jun 22 04:33:03 PM PDT 24 Jun 22 04:33:04 PM PDT 24 13321953 ps
T759 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.943448755 Jun 22 04:32:36 PM PDT 24 Jun 22 04:32:40 PM PDT 24 56913636 ps
T760 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2999508106 Jun 22 04:32:47 PM PDT 24 Jun 22 04:32:49 PM PDT 24 270052653 ps
T761 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2666987109 Jun 22 04:33:06 PM PDT 24 Jun 22 04:33:07 PM PDT 24 26516757 ps
T76 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.639982309 Jun 22 04:32:41 PM PDT 24 Jun 22 04:32:43 PM PDT 24 23493914 ps
T762 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3783461034 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:50 PM PDT 24 28938964 ps
T86 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.522705238 Jun 22 04:32:39 PM PDT 24 Jun 22 04:32:42 PM PDT 24 314765382 ps
T763 /workspace/coverage/cover_reg_top/12.gpio_intr_test.2481223243 Jun 22 04:32:42 PM PDT 24 Jun 22 04:32:43 PM PDT 24 48678017 ps
T764 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.669566582 Jun 22 04:32:48 PM PDT 24 Jun 22 04:32:49 PM PDT 24 42965545 ps
T765 /workspace/coverage/cover_reg_top/27.gpio_intr_test.2211136008 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:50 PM PDT 24 28200610 ps
T766 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.706213962 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:38 PM PDT 24 11795720 ps
T767 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.670295108 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:37 PM PDT 24 90024889 ps
T768 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1290824575 Jun 22 04:32:52 PM PDT 24 Jun 22 04:32:53 PM PDT 24 17814675 ps
T769 /workspace/coverage/cover_reg_top/44.gpio_intr_test.1069111916 Jun 22 04:32:51 PM PDT 24 Jun 22 04:32:52 PM PDT 24 30171283 ps
T770 /workspace/coverage/cover_reg_top/14.gpio_intr_test.268539532 Jun 22 04:32:43 PM PDT 24 Jun 22 04:32:45 PM PDT 24 23441491 ps
T771 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.558318388 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:41 PM PDT 24 109828864 ps
T772 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1097444844 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:41 PM PDT 24 539719667 ps
T773 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3663186096 Jun 22 04:32:36 PM PDT 24 Jun 22 04:32:41 PM PDT 24 32958514 ps
T774 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2332878330 Jun 22 04:32:43 PM PDT 24 Jun 22 04:32:45 PM PDT 24 76473333 ps
T775 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4133300849 Jun 22 04:33:02 PM PDT 24 Jun 22 04:33:03 PM PDT 24 36638442 ps
T776 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.736607912 Jun 22 04:32:39 PM PDT 24 Jun 22 04:32:42 PM PDT 24 223454443 ps
T777 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1199017735 Jun 22 04:32:41 PM PDT 24 Jun 22 04:32:44 PM PDT 24 29343145 ps
T778 /workspace/coverage/cover_reg_top/43.gpio_intr_test.312855683 Jun 22 04:33:00 PM PDT 24 Jun 22 04:33:01 PM PDT 24 16346362 ps
T779 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3409255994 Jun 22 04:32:56 PM PDT 24 Jun 22 04:32:58 PM PDT 24 25477946 ps
T780 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.448401477 Jun 22 04:32:48 PM PDT 24 Jun 22 04:32:50 PM PDT 24 40780632 ps
T781 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2196382921 Jun 22 04:32:47 PM PDT 24 Jun 22 04:32:48 PM PDT 24 43057547 ps
T782 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2557648912 Jun 22 04:32:36 PM PDT 24 Jun 22 04:32:40 PM PDT 24 19633214 ps
T783 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3975842376 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:51 PM PDT 24 43243999 ps
T784 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1978242077 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:42 PM PDT 24 183579773 ps
T785 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.332672990 Jun 22 04:32:44 PM PDT 24 Jun 22 04:32:47 PM PDT 24 721267508 ps
T786 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4169162791 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:42 PM PDT 24 59367366 ps
T77 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1398725478 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:50 PM PDT 24 36562359 ps
T787 /workspace/coverage/cover_reg_top/39.gpio_intr_test.1767993951 Jun 22 04:33:14 PM PDT 24 Jun 22 04:33:16 PM PDT 24 44032280 ps
T788 /workspace/coverage/cover_reg_top/42.gpio_intr_test.473666857 Jun 22 04:32:53 PM PDT 24 Jun 22 04:32:54 PM PDT 24 104878631 ps
T87 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4210681868 Jun 22 04:32:56 PM PDT 24 Jun 22 04:32:59 PM PDT 24 16953759 ps
T789 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1850127100 Jun 22 04:32:55 PM PDT 24 Jun 22 04:32:57 PM PDT 24 389760214 ps
T790 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.118021314 Jun 22 04:32:51 PM PDT 24 Jun 22 04:32:53 PM PDT 24 348682368 ps
T791 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2190832433 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:51 PM PDT 24 271193844 ps
T792 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2976395805 Jun 22 04:32:56 PM PDT 24 Jun 22 04:32:59 PM PDT 24 421926859 ps
T793 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2545980573 Jun 22 04:32:40 PM PDT 24 Jun 22 04:32:42 PM PDT 24 28426528 ps
T794 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2759726315 Jun 22 04:32:56 PM PDT 24 Jun 22 04:32:59 PM PDT 24 120737383 ps
T795 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.901344629 Jun 22 04:32:40 PM PDT 24 Jun 22 04:32:42 PM PDT 24 57292757 ps
T796 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2805365744 Jun 22 04:32:55 PM PDT 24 Jun 22 04:32:57 PM PDT 24 124536601 ps
T797 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1442911972 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:37 PM PDT 24 16317904 ps
T798 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3130166823 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:40 PM PDT 24 115913602 ps
T799 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3345666711 Jun 22 04:32:52 PM PDT 24 Jun 22 04:32:53 PM PDT 24 18770294 ps
T800 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.317588766 Jun 22 04:32:33 PM PDT 24 Jun 22 04:32:35 PM PDT 24 14821282 ps
T801 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.70676752 Jun 22 04:32:55 PM PDT 24 Jun 22 04:32:56 PM PDT 24 56369142 ps
T802 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3229819706 Jun 22 04:32:59 PM PDT 24 Jun 22 04:33:02 PM PDT 24 209379092 ps
T803 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2163498667 Jun 22 04:32:36 PM PDT 24 Jun 22 04:32:39 PM PDT 24 16928241 ps
T804 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3594709442 Jun 22 04:32:44 PM PDT 24 Jun 22 04:32:45 PM PDT 24 101260295 ps
T805 /workspace/coverage/cover_reg_top/45.gpio_intr_test.704322881 Jun 22 04:32:52 PM PDT 24 Jun 22 04:32:53 PM PDT 24 68985302 ps
T806 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.299798462 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:37 PM PDT 24 13551699 ps
T807 /workspace/coverage/cover_reg_top/1.gpio_intr_test.4203338148 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:38 PM PDT 24 98064152 ps
T808 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.991675768 Jun 22 04:32:42 PM PDT 24 Jun 22 04:32:44 PM PDT 24 33703282 ps
T809 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2105875858 Jun 22 04:32:38 PM PDT 24 Jun 22 04:32:42 PM PDT 24 75511344 ps
T810 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3627642150 Jun 22 04:32:52 PM PDT 24 Jun 22 04:32:53 PM PDT 24 42940001 ps
T811 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1212937942 Jun 22 04:32:59 PM PDT 24 Jun 22 04:33:00 PM PDT 24 25924045 ps
T812 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1563276576 Jun 22 04:32:48 PM PDT 24 Jun 22 04:32:50 PM PDT 24 31038384 ps
T813 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3614537101 Jun 22 04:32:50 PM PDT 24 Jun 22 04:32:52 PM PDT 24 63240566 ps
T814 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3694079775 Jun 22 04:32:43 PM PDT 24 Jun 22 04:32:45 PM PDT 24 65695825 ps
T815 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2776131963 Jun 22 04:32:55 PM PDT 24 Jun 22 04:32:57 PM PDT 24 13061520 ps
T816 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2512733673 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:41 PM PDT 24 31887851 ps
T78 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1172527343 Jun 22 04:32:39 PM PDT 24 Jun 22 04:32:41 PM PDT 24 15369493 ps
T817 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2694619687 Jun 22 04:32:41 PM PDT 24 Jun 22 04:32:43 PM PDT 24 49141482 ps
T818 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1999778246 Jun 22 04:32:43 PM PDT 24 Jun 22 04:32:45 PM PDT 24 32676430 ps
T819 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2795635094 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:38 PM PDT 24 38252880 ps
T820 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1538425414 Jun 22 04:32:32 PM PDT 24 Jun 22 04:32:34 PM PDT 24 157740806 ps
T821 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3884034958 Jun 22 04:33:04 PM PDT 24 Jun 22 04:33:05 PM PDT 24 18975202 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2664905642 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:51 PM PDT 24 123059503 ps
T823 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.521135330 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:51 PM PDT 24 108266964 ps
T824 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2105843994 Jun 22 04:32:56 PM PDT 24 Jun 22 04:32:58 PM PDT 24 17810837 ps
T825 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1540048333 Jun 22 04:32:54 PM PDT 24 Jun 22 04:32:56 PM PDT 24 30206870 ps
T826 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.364613209 Jun 22 04:32:45 PM PDT 24 Jun 22 04:32:48 PM PDT 24 75325124 ps
T827 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1295040452 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:38 PM PDT 24 124407399 ps
T828 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.798501864 Jun 22 04:32:33 PM PDT 24 Jun 22 04:32:35 PM PDT 24 211482389 ps
T829 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.380809598 Jun 22 04:32:39 PM PDT 24 Jun 22 04:32:43 PM PDT 24 205773736 ps
T830 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3520411179 Jun 22 04:33:00 PM PDT 24 Jun 22 04:33:01 PM PDT 24 40453265 ps
T831 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1683816769 Jun 22 04:32:43 PM PDT 24 Jun 22 04:32:46 PM PDT 24 136593529 ps
T79 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.989894791 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:36 PM PDT 24 12863635 ps
T832 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1762191174 Jun 22 04:32:33 PM PDT 24 Jun 22 04:32:35 PM PDT 24 160913096 ps
T833 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.399910015 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:40 PM PDT 24 45098964 ps
T834 /workspace/coverage/cover_reg_top/23.gpio_intr_test.987412198 Jun 22 04:33:00 PM PDT 24 Jun 22 04:33:02 PM PDT 24 18196530 ps
T835 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3292979927 Jun 22 04:32:41 PM PDT 24 Jun 22 04:32:43 PM PDT 24 28024817 ps
T836 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.199039450 Jun 22 04:32:35 PM PDT 24 Jun 22 04:32:40 PM PDT 24 51711002 ps
T837 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1337456155 Jun 22 04:32:49 PM PDT 24 Jun 22 04:32:50 PM PDT 24 36818528 ps
T838 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3504709409 Jun 22 04:32:58 PM PDT 24 Jun 22 04:33:00 PM PDT 24 54881826 ps
T839 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3586405563 Jun 22 04:32:37 PM PDT 24 Jun 22 04:32:40 PM PDT 24 14500543 ps
T840 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2074001653 Jun 22 04:32:34 PM PDT 24 Jun 22 04:32:36 PM PDT 24 135852789 ps
T841 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1064276472 Jun 22 04:32:48 PM PDT 24 Jun 22 04:32:51 PM PDT 24 63399244 ps
T842 /workspace/coverage/cover_reg_top/20.gpio_intr_test.3683038972 Jun 22 04:32:50 PM PDT 24 Jun 22 04:32:51 PM PDT 24 15366611 ps
T80 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2741945355 Jun 22 04:32:56 PM PDT 24 Jun 22 04:32:58 PM PDT 24 11416921 ps
T843 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1444102239 Jun 22 04:32:52 PM PDT 24 Jun 22 04:32:53 PM PDT 24 49742424 ps
T844 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2584188482 Jun 22 04:33:03 PM PDT 24 Jun 22 04:33:04 PM PDT 24 27907085 ps
T845 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1903926947 Jun 22 04:32:36 PM PDT 24 Jun 22 04:32:39 PM PDT 24 38221375 ps
T846 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1954490382 Jun 22 04:32:58 PM PDT 24 Jun 22 04:32:59 PM PDT 24 12668496 ps
T847 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4151386110 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:52 PM PDT 24 66105963 ps
T848 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2958946151 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:51 PM PDT 24 134440919 ps
T849 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1161146171 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:51 PM PDT 24 120982246 ps
T850 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237838161 Jun 22 04:35:32 PM PDT 24 Jun 22 04:35:33 PM PDT 24 47495087 ps
T851 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.961380202 Jun 22 04:35:43 PM PDT 24 Jun 22 04:35:44 PM PDT 24 40182765 ps
T852 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1986523569 Jun 22 04:35:52 PM PDT 24 Jun 22 04:35:54 PM PDT 24 49225353 ps
T853 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2137619761 Jun 22 04:35:56 PM PDT 24 Jun 22 04:35:59 PM PDT 24 231781879 ps
T854 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4039118122 Jun 22 04:35:46 PM PDT 24 Jun 22 04:35:47 PM PDT 24 76753963 ps
T855 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2263230324 Jun 22 04:35:44 PM PDT 24 Jun 22 04:35:45 PM PDT 24 221993024 ps
T856 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.435764969 Jun 22 04:35:52 PM PDT 24 Jun 22 04:35:54 PM PDT 24 562464964 ps
T857 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1172896086 Jun 22 04:35:46 PM PDT 24 Jun 22 04:35:48 PM PDT 24 59340441 ps
T858 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2537420500 Jun 22 04:35:54 PM PDT 24 Jun 22 04:35:56 PM PDT 24 84671067 ps
T859 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.375325213 Jun 22 04:35:59 PM PDT 24 Jun 22 04:36:02 PM PDT 24 189117259 ps
T860 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3697755918 Jun 22 04:35:37 PM PDT 24 Jun 22 04:35:39 PM PDT 24 131999605 ps
T861 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1500157136 Jun 22 04:35:55 PM PDT 24 Jun 22 04:35:58 PM PDT 24 155305144 ps
T862 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2835619807 Jun 22 04:35:54 PM PDT 24 Jun 22 04:35:57 PM PDT 24 82888005 ps
T863 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1153141157 Jun 22 04:35:38 PM PDT 24 Jun 22 04:35:39 PM PDT 24 145600129 ps
T864 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1219111544 Jun 22 04:35:59 PM PDT 24 Jun 22 04:36:02 PM PDT 24 232859980 ps
T865 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.808563437 Jun 22 04:35:53 PM PDT 24 Jun 22 04:35:55 PM PDT 24 264701675 ps
T866 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4144040876 Jun 22 04:35:45 PM PDT 24 Jun 22 04:35:46 PM PDT 24 53919538 ps
T867 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4005336341 Jun 22 04:35:58 PM PDT 24 Jun 22 04:36:01 PM PDT 24 42918538 ps
T868 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1167791660 Jun 22 04:35:48 PM PDT 24 Jun 22 04:35:49 PM PDT 24 75670026 ps
T869 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1239440112 Jun 22 04:35:25 PM PDT 24 Jun 22 04:35:27 PM PDT 24 118889296 ps
T870 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3815914586 Jun 22 04:36:03 PM PDT 24 Jun 22 04:36:05 PM PDT 24 219525199 ps
T871 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3663383874 Jun 22 04:35:43 PM PDT 24 Jun 22 04:35:44 PM PDT 24 38084254 ps
T872 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.453337094 Jun 22 04:35:55 PM PDT 24 Jun 22 04:35:58 PM PDT 24 137097411 ps
T873 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1403475124 Jun 22 04:35:46 PM PDT 24 Jun 22 04:35:47 PM PDT 24 156912660 ps
T874 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1564672043 Jun 22 04:35:45 PM PDT 24 Jun 22 04:35:47 PM PDT 24 40816775 ps
T875 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1661342453 Jun 22 04:35:54 PM PDT 24 Jun 22 04:35:56 PM PDT 24 84422468 ps
T876 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1064007322 Jun 22 04:35:42 PM PDT 24 Jun 22 04:35:44 PM PDT 24 209128902 ps
T877 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.155674855 Jun 22 04:35:52 PM PDT 24 Jun 22 04:35:53 PM PDT 24 105771164 ps
T878 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1781499661 Jun 22 04:35:49 PM PDT 24 Jun 22 04:35:50 PM PDT 24 146066546 ps
T879 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.561480595 Jun 22 04:35:42 PM PDT 24 Jun 22 04:35:43 PM PDT 24 29279234 ps
T880 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1431143193 Jun 22 04:35:31 PM PDT 24 Jun 22 04:35:33 PM PDT 24 86953576 ps
T881 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.660571308 Jun 22 04:35:54 PM PDT 24 Jun 22 04:35:56 PM PDT 24 58765928 ps
T882 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3133024837 Jun 22 04:35:45 PM PDT 24 Jun 22 04:35:47 PM PDT 24 55946814 ps
T883 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101497171 Jun 22 04:35:42 PM PDT 24 Jun 22 04:35:44 PM PDT 24 234691680 ps
T884 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2421557590 Jun 22 04:35:56 PM PDT 24 Jun 22 04:35:59 PM PDT 24 71199536 ps
T885 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1913585445 Jun 22 04:35:41 PM PDT 24 Jun 22 04:35:42 PM PDT 24 45490248 ps
T886 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2909025326 Jun 22 04:35:40 PM PDT 24 Jun 22 04:35:42 PM PDT 24 182922842 ps
T887 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.495463999 Jun 22 04:36:08 PM PDT 24 Jun 22 04:36:09 PM PDT 24 75193329 ps
T888 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2213754752 Jun 22 04:36:11 PM PDT 24 Jun 22 04:36:13 PM PDT 24 69096089 ps
T889 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.522068904 Jun 22 04:35:45 PM PDT 24 Jun 22 04:35:47 PM PDT 24 323224348 ps
T890 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.863693711 Jun 22 04:35:57 PM PDT 24 Jun 22 04:36:00 PM PDT 24 43373424 ps
T891 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.239408267 Jun 22 04:36:33 PM PDT 24 Jun 22 04:36:35 PM PDT 24 162120318 ps
T892 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2786652834 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:52 PM PDT 24 240776511 ps
T893 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2418783762 Jun 22 04:36:18 PM PDT 24 Jun 22 04:36:20 PM PDT 24 125715892 ps
T894 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3021088209 Jun 22 04:35:23 PM PDT 24 Jun 22 04:35:25 PM PDT 24 500251701 ps
T895 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3331876560 Jun 22 04:35:57 PM PDT 24 Jun 22 04:36:01 PM PDT 24 102524697 ps
T896 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1174821514 Jun 22 04:35:48 PM PDT 24 Jun 22 04:35:55 PM PDT 24 42253583 ps
T897 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3134130934 Jun 22 04:35:39 PM PDT 24 Jun 22 04:35:41 PM PDT 24 140453022 ps
T898 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.382814551 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:52 PM PDT 24 52052410 ps
T899 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3219174193 Jun 22 04:35:58 PM PDT 24 Jun 22 04:36:01 PM PDT 24 100106310 ps
T900 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707866903 Jun 22 04:35:48 PM PDT 24 Jun 22 04:35:49 PM PDT 24 41003393 ps
T901 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.17747119 Jun 22 04:35:23 PM PDT 24 Jun 22 04:35:25 PM PDT 24 495416368 ps
T902 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1550671607 Jun 22 04:35:56 PM PDT 24 Jun 22 04:35:59 PM PDT 24 267254071 ps
T903 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1958302253 Jun 22 04:35:23 PM PDT 24 Jun 22 04:35:25 PM PDT 24 167607304 ps
T904 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.196593414 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:51 PM PDT 24 169567944 ps
T905 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.667381014 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:51 PM PDT 24 283753347 ps
T906 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3755977513 Jun 22 04:35:35 PM PDT 24 Jun 22 04:35:37 PM PDT 24 99641864 ps
T907 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2235863486 Jun 22 04:35:44 PM PDT 24 Jun 22 04:35:46 PM PDT 24 101347909 ps
T908 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3922748821 Jun 22 04:35:54 PM PDT 24 Jun 22 04:36:01 PM PDT 24 59112542 ps
T909 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1167575865 Jun 22 04:35:55 PM PDT 24 Jun 22 04:35:58 PM PDT 24 35220396 ps
T910 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1664527839 Jun 22 04:35:52 PM PDT 24 Jun 22 04:35:54 PM PDT 24 49943833 ps
T911 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1920969031 Jun 22 04:35:42 PM PDT 24 Jun 22 04:35:44 PM PDT 24 114903592 ps
T912 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3396882309 Jun 22 04:35:57 PM PDT 24 Jun 22 04:36:01 PM PDT 24 639671346 ps
T913 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.813925306 Jun 22 04:35:42 PM PDT 24 Jun 22 04:35:44 PM PDT 24 94264114 ps
T914 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3986951276 Jun 22 04:35:37 PM PDT 24 Jun 22 04:35:38 PM PDT 24 237659384 ps
T915 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2549781457 Jun 22 04:35:42 PM PDT 24 Jun 22 04:35:43 PM PDT 24 34645237 ps
T916 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39068396 Jun 22 04:35:45 PM PDT 24 Jun 22 04:35:47 PM PDT 24 77144525 ps
T917 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946250292 Jun 22 04:35:37 PM PDT 24 Jun 22 04:35:38 PM PDT 24 103585712 ps
T918 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1210187090 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:51 PM PDT 24 117430788 ps
T919 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3591773402 Jun 22 04:35:48 PM PDT 24 Jun 22 04:35:50 PM PDT 24 31635090 ps
T920 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.564761096 Jun 22 04:35:49 PM PDT 24 Jun 22 04:35:51 PM PDT 24 40738922 ps
T921 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2203221014 Jun 22 04:35:46 PM PDT 24 Jun 22 04:35:48 PM PDT 24 113794221 ps
T922 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650812631 Jun 22 04:35:50 PM PDT 24 Jun 22 04:35:52 PM PDT 24 127292393 ps
T923 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1389625147 Jun 22 04:35:34 PM PDT 24 Jun 22 04:35:36 PM PDT 24 558490927 ps
T924 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2960339969 Jun 22 04:35:55 PM PDT 24 Jun 22 04:35:57 PM PDT 24 29598059 ps
T925 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.757297725 Jun 22 04:36:02 PM PDT 24 Jun 22 04:36:04 PM PDT 24 287279864 ps
T926 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1980392173 Jun 22 04:35:39 PM PDT 24 Jun 22 04:35:40 PM PDT 24 94745046 ps
T927 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1328872698 Jun 22 04:35:58 PM PDT 24 Jun 22 04:36:02 PM PDT 24 46562527 ps
T928 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3034693936 Jun 22 04:36:33 PM PDT 24 Jun 22 04:36:34 PM PDT 24 197055665 ps
T929 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237556837 Jun 22 04:35:56 PM PDT 24 Jun 22 04:35:59 PM PDT 24 125162480 ps
T930 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4089831409 Jun 22 04:35:34 PM PDT 24 Jun 22 04:35:35 PM PDT 24 205146233 ps
T931 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3805201066 Jun 22 04:35:37 PM PDT 24 Jun 22 04:35:39 PM PDT 24 464394433 ps
T932 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3938089168 Jun 22 04:35:51 PM PDT 24 Jun 22 04:35:53 PM PDT 24 47260411 ps
T933 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2160948519 Jun 22 04:35:51 PM PDT 24 Jun 22 04:35:53 PM PDT 24 55908081 ps
T934 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4260422469 Jun 22 04:35:34 PM PDT 24 Jun 22 04:35:36 PM PDT 24 34375636 ps
T935 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1192283537 Jun 22 04:35:46 PM PDT 24 Jun 22 04:35:47 PM PDT 24 287703616 ps
T936 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3595234793 Jun 22 04:35:26 PM PDT 24 Jun 22 04:35:27 PM PDT 24 142681271 ps
T937 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.15951646 Jun 22 04:35:42 PM PDT 24 Jun 22 04:35:44 PM PDT 24 52373141 ps
T938 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2789822110 Jun 22 04:35:49 PM PDT 24 Jun 22 04:35:50 PM PDT 24 139991871 ps
T939 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3796971413 Jun 22 04:35:43 PM PDT 24 Jun 22 04:35:44 PM PDT 24 143888535 ps
T940 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1077271701 Jun 22 04:35:53 PM PDT 24 Jun 22 04:35:55 PM PDT 24 135554261 ps
T941 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4210018444 Jun 22 04:35:37 PM PDT 24 Jun 22 04:35:38 PM PDT 24 85280226 ps
T942 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.138635182 Jun 22 04:36:03 PM PDT 24 Jun 22 04:36:04 PM PDT 24 90859909 ps
T943 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3775521250 Jun 22 04:35:51 PM PDT 24 Jun 22 04:35:53 PM PDT 24 33501381 ps
T944 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1631914745 Jun 22 04:35:48 PM PDT 24 Jun 22 04:35:49 PM PDT 24 171108217 ps
T945 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1697159139 Jun 22 04:35:52 PM PDT 24 Jun 22 04:35:54 PM PDT 24 41353826 ps
T946 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.900842759 Jun 22 04:35:39 PM PDT 24 Jun 22 04:35:41 PM PDT 24 98907739 ps

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2918982494
Short name T20
Test name
Test status
Simulation time 144664742400 ps
CPU time 1402.65 seconds
Started Jun 22 04:24:12 PM PDT 24
Finished Jun 22 04:47:36 PM PDT 24
Peak memory 197944 kb
Host smart-8a5dba7f-db62-4388-879a-2557fe7a480f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2918982494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2918982494
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3885146595
Short name T93
Test name
Test status
Simulation time 283008876 ps
CPU time 2.73 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 197788 kb
Host smart-6fcfafb0-48b6-4e47-8787-c6c9d4f886c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885146595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3885146595
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2833267421
Short name T1
Test name
Test status
Simulation time 289905725 ps
CPU time 2.03 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 197764 kb
Host smart-d6964802-c424-47d8-a005-7baf2a9dba0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833267421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2833267421
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3756342090
Short name T31
Test name
Test status
Simulation time 37506452 ps
CPU time 0.81 seconds
Started Jun 22 04:24:05 PM PDT 24
Finished Jun 22 04:24:06 PM PDT 24
Peak memory 213476 kb
Host smart-f509550c-78e1-438b-88b1-af841b59ab97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756342090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3756342090
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3123020667
Short name T69
Test name
Test status
Simulation time 46967679 ps
CPU time 0.66 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 194140 kb
Host smart-3e376a13-8e48-45db-943a-02d0414fc18e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123020667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3123020667
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3879565275
Short name T40
Test name
Test status
Simulation time 598339167 ps
CPU time 1.4 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 197704 kb
Host smart-625d9b48-76c7-4cae-8fd0-7271d741684e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879565275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3879565275
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1986219680
Short name T145
Test name
Test status
Simulation time 11690416 ps
CPU time 0.61 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:27 PM PDT 24
Peak memory 193604 kb
Host smart-13a5f8c0-3907-4dfd-9c4c-e9b0e60d44d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986219680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1986219680
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.4106437807
Short name T85
Test name
Test status
Simulation time 14036994 ps
CPU time 0.61 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 194816 kb
Host smart-fead87f4-3938-42b4-ac55-b0431a044e35
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106437807 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.4106437807
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.1850127100
Short name T789
Test name
Test status
Simulation time 389760214 ps
CPU time 1.38 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:32:57 PM PDT 24
Peak memory 197700 kb
Host smart-21b9da04-e263-46e6-b288-043013a5e52c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850127100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.1850127100
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.670295108
Short name T767
Test name
Test status
Simulation time 90024889 ps
CPU time 0.75 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 195536 kb
Host smart-53541536-8152-4bd4-94a8-a2b4cda01d1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670295108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.670295108
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.283955979
Short name T88
Test name
Test status
Simulation time 714658182 ps
CPU time 2.35 seconds
Started Jun 22 04:32:38 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 196700 kb
Host smart-bb063c19-22d0-4157-b8ff-544f039b7e40
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283955979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.283955979
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.943448755
Short name T759
Test name
Test status
Simulation time 56913636 ps
CPU time 0.65 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 195196 kb
Host smart-97fedae0-8ceb-477a-a35f-a064c1edaf6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943448755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.943448755
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.1762191174
Short name T832
Test name
Test status
Simulation time 160913096 ps
CPU time 0.98 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 197516 kb
Host smart-3ed84611-ad18-4f54-b3ab-723f73ddde04
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762191174 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.1762191174
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2795635094
Short name T819
Test name
Test status
Simulation time 38252880 ps
CPU time 0.6 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 193812 kb
Host smart-e1ffa24c-c1af-439b-a68b-821cccc34658
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795635094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2795635094
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.308630839
Short name T752
Test name
Test status
Simulation time 47608056 ps
CPU time 0.6 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 193972 kb
Host smart-7bb74c37-0737-4b92-9963-d29d0b10b335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308630839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.308630839
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.299798462
Short name T806
Test name
Test status
Simulation time 13551699 ps
CPU time 0.66 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 194188 kb
Host smart-8586b988-5961-4ae6-ba03-aa7fe80072af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299798462 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.299798462
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3663186096
Short name T773
Test name
Test status
Simulation time 32958514 ps
CPU time 1.69 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 197636 kb
Host smart-bd2f41e7-ebb4-45a3-b61e-f835228f3d5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663186096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3663186096
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2537746502
Short name T38
Test name
Test status
Simulation time 680189253 ps
CPU time 1.09 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 197648 kb
Host smart-04de0875-c803-4f7a-9fbc-191c695dbfcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537746502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2537746502
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.399910015
Short name T833
Test name
Test status
Simulation time 45098964 ps
CPU time 0.66 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 194376 kb
Host smart-314b9644-919b-4312-acc6-f01840e9417c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399910015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.gpio_csr_aliasing.399910015
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2885386787
Short name T750
Test name
Test status
Simulation time 221707571 ps
CPU time 2.19 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 197628 kb
Host smart-9700a103-9924-439b-96ad-7329439ced98
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885386787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2885386787
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1475545190
Short name T73
Test name
Test status
Simulation time 20274885 ps
CPU time 0.56 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:32:34 PM PDT 24
Peak memory 194188 kb
Host smart-d3a16a04-828b-42c8-8750-1caaf457ed0a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475545190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1475545190
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3130166823
Short name T798
Test name
Test status
Simulation time 115913602 ps
CPU time 1.4 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 197664 kb
Host smart-146ca5b4-89d9-4327-8bee-5c7206d952f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130166823 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3130166823
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1873714263
Short name T90
Test name
Test status
Simulation time 15989286 ps
CPU time 0.64 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 195036 kb
Host smart-5a1ea5cd-878a-4876-b7d0-8306fd28cfd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873714263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1873714263
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.4203338148
Short name T807
Test name
Test status
Simulation time 98064152 ps
CPU time 0.62 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 194016 kb
Host smart-2a376440-126b-4062-8ca5-62bf07dcb3b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203338148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.4203338148
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1097444844
Short name T772
Test name
Test status
Simulation time 539719667 ps
CPU time 1.63 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 197660 kb
Host smart-99396740-bfad-4289-bd44-2841abeba8ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097444844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1097444844
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.798501864
Short name T828
Test name
Test status
Simulation time 211482389 ps
CPU time 1.14 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 197748 kb
Host smart-ec795f38-9131-414c-9b32-a613a8623e75
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798501864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.gpio_tl_intg_err.798501864
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2196382921
Short name T781
Test name
Test status
Simulation time 43057547 ps
CPU time 0.92 seconds
Started Jun 22 04:32:47 PM PDT 24
Finished Jun 22 04:32:48 PM PDT 24
Peak memory 197516 kb
Host smart-fe5dbd35-d8ac-4007-81c2-c567e7390130
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196382921 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2196382921
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2776131963
Short name T815
Test name
Test status
Simulation time 13061520 ps
CPU time 0.56 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:32:57 PM PDT 24
Peak memory 193516 kb
Host smart-976f3d68-3f2b-4b2b-bce3-95f7f0d474c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776131963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2776131963
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.3739507883
Short name T744
Test name
Test status
Simulation time 39845187 ps
CPU time 0.6 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:57 PM PDT 24
Peak memory 193224 kb
Host smart-7f580b0f-9b55-4882-b39a-c6c5d02f2f11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739507883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.3739507883
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3594709442
Short name T804
Test name
Test status
Simulation time 101260295 ps
CPU time 0.75 seconds
Started Jun 22 04:32:44 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 196444 kb
Host smart-59d6a096-74f8-4b02-b3a0-bb96e5dc61ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594709442 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3594709442
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2999508106
Short name T760
Test name
Test status
Simulation time 270052653 ps
CPU time 1.72 seconds
Started Jun 22 04:32:47 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 197652 kb
Host smart-3f17e385-1b15-4d03-b892-b042763d215a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999508106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2999508106
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.296929095
Short name T29
Test name
Test status
Simulation time 1709191787 ps
CPU time 1.54 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:46 PM PDT 24
Peak memory 197684 kb
Host smart-debfd595-eec7-445d-990b-01ad6ab0c40a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296929095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.296929095
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2152373631
Short name T756
Test name
Test status
Simulation time 51437193 ps
CPU time 1.3 seconds
Started Jun 22 04:32:42 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 197720 kb
Host smart-2635edb3-ec0c-4cb3-9d79-3e626f605782
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152373631 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2152373631
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.816014792
Short name T74
Test name
Test status
Simulation time 82524472 ps
CPU time 0.61 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 194512 kb
Host smart-9a9c4d36-a607-402b-be91-b60e49ec95a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816014792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio
_csr_rw.816014792
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.185479094
Short name T725
Test name
Test status
Simulation time 12319435 ps
CPU time 0.6 seconds
Started Jun 22 04:32:42 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 193924 kb
Host smart-d728e731-26d6-4d77-bdc9-4c0268305699
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185479094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.185479094
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1938352092
Short name T81
Test name
Test status
Simulation time 36980034 ps
CPU time 0.64 seconds
Started Jun 22 04:32:54 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 194860 kb
Host smart-a1d26b39-100c-40d0-9fc7-72aa5571469d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938352092 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1938352092
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2432180345
Short name T727
Test name
Test status
Simulation time 38440113 ps
CPU time 1.14 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 197848 kb
Host smart-9768bea4-50c9-4643-9ef6-977534e336d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432180345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2432180345
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.4102343653
Short name T37
Test name
Test status
Simulation time 151362726 ps
CPU time 1.16 seconds
Started Jun 22 04:32:57 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 197600 kb
Host smart-e1735d34-8792-42a3-8d48-1e2a9ec2b896
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102343653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.4102343653
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1199017735
Short name T777
Test name
Test status
Simulation time 29343145 ps
CPU time 1.39 seconds
Started Jun 22 04:32:41 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 197652 kb
Host smart-5e12b04d-aeb3-4013-ba9f-ce865a6e9aa3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199017735 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1199017735
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1066692781
Short name T71
Test name
Test status
Simulation time 17209080 ps
CPU time 0.62 seconds
Started Jun 22 04:32:41 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 194524 kb
Host smart-c51ceef1-e5eb-4d18-9e95-d6b99327c158
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066692781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1066692781
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2481223243
Short name T763
Test name
Test status
Simulation time 48678017 ps
CPU time 0.62 seconds
Started Jun 22 04:32:42 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 193948 kb
Host smart-7acc7412-9590-4259-b722-64690f2073e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481223243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2481223243
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3576410063
Short name T82
Test name
Test status
Simulation time 108250656 ps
CPU time 0.81 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 195960 kb
Host smart-38875e11-751f-430a-a5b0-81c082122d1f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576410063 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3576410063
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.332672990
Short name T785
Test name
Test status
Simulation time 721267508 ps
CPU time 2.77 seconds
Started Jun 22 04:32:44 PM PDT 24
Finished Jun 22 04:32:47 PM PDT 24
Peak memory 197568 kb
Host smart-b25136a5-5ff5-4ace-8b00-eb04b4bf8b60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332672990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.332672990
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2392299911
Short name T41
Test name
Test status
Simulation time 428342678 ps
CPU time 1.4 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 197684 kb
Host smart-297486db-e4da-488e-a401-967e78369025
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392299911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2392299911
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3975842376
Short name T783
Test name
Test status
Simulation time 43243999 ps
CPU time 0.75 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 197468 kb
Host smart-e401fdbb-e247-49ee-9568-03cc9074beec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975842376 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3975842376
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.669566582
Short name T764
Test name
Test status
Simulation time 42965545 ps
CPU time 0.6 seconds
Started Jun 22 04:32:48 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 194608 kb
Host smart-c5e52f6e-4538-4a83-820b-e9374b3f4ee6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669566582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.669566582
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1999778246
Short name T818
Test name
Test status
Simulation time 32676430 ps
CPU time 0.6 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 193284 kb
Host smart-e570ca36-9c8b-49fa-8c78-7fcab106af3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999778246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1999778246
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.394642129
Short name T84
Test name
Test status
Simulation time 15000458 ps
CPU time 0.62 seconds
Started Jun 22 04:32:45 PM PDT 24
Finished Jun 22 04:32:46 PM PDT 24
Peak memory 194604 kb
Host smart-502145e5-61aa-4b17-a2d3-f7fa42024d94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394642129 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.394642129
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1683816769
Short name T831
Test name
Test status
Simulation time 136593529 ps
CPU time 1.88 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:46 PM PDT 24
Peak memory 197696 kb
Host smart-73e32d93-acbe-4b14-ab6e-7b23ee07ba8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683816769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1683816769
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.3627642150
Short name T810
Test name
Test status
Simulation time 42940001 ps
CPU time 0.95 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 197480 kb
Host smart-fab27ac2-4266-4321-bda8-5b70f8e28467
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627642150 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.3627642150
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2741945355
Short name T80
Test name
Test status
Simulation time 11416921 ps
CPU time 0.6 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 194000 kb
Host smart-1cf63686-6ae7-47bf-8840-8917bdbd2952
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741945355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2741945355
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.268539532
Short name T770
Test name
Test status
Simulation time 23441491 ps
CPU time 0.64 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 194296 kb
Host smart-299a045b-c8bc-45c2-9c1b-3ef1e14271b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268539532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.268539532
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2105843994
Short name T824
Test name
Test status
Simulation time 17810837 ps
CPU time 0.75 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 195840 kb
Host smart-061a4cfe-d604-41f5-97e0-a86dea026221
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105843994 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2105843994
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1064276472
Short name T841
Test name
Test status
Simulation time 63399244 ps
CPU time 1.73 seconds
Started Jun 22 04:32:48 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 197600 kb
Host smart-ebf73982-ed8a-46e7-9299-b0999fb3cc85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064276472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1064276472
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.521135330
Short name T823
Test name
Test status
Simulation time 108266964 ps
CPU time 1.11 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 197716 kb
Host smart-4979b3f7-5aa5-49a2-b904-e5f1b77fcadb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521135330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.521135330
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.2016750449
Short name T741
Test name
Test status
Simulation time 16506104 ps
CPU time 0.64 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:54 PM PDT 24
Peak memory 196524 kb
Host smart-990cdf36-ba29-46e7-bbfe-5e7806b5651b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016750449 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.2016750449
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2209712172
Short name T740
Test name
Test status
Simulation time 12459156 ps
CPU time 0.58 seconds
Started Jun 22 04:32:53 PM PDT 24
Finished Jun 22 04:32:54 PM PDT 24
Peak memory 194200 kb
Host smart-1938bed1-5738-4e3b-a143-d42f8123f1e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209712172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2209712172
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.542207759
Short name T715
Test name
Test status
Simulation time 77422953 ps
CPU time 0.65 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:32:56 PM PDT 24
Peak memory 193324 kb
Host smart-52e391dd-0cd4-413d-a069-07d900c7f15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542207759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.542207759
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.4210681868
Short name T87
Test name
Test status
Simulation time 16953759 ps
CPU time 0.77 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 195828 kb
Host smart-1fd40a5f-4949-4a14-b388-6afd6b8e8862
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210681868 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.4210681868
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.552192992
Short name T746
Test name
Test status
Simulation time 918163958 ps
CPU time 2.85 seconds
Started Jun 22 04:33:09 PM PDT 24
Finished Jun 22 04:33:13 PM PDT 24
Peak memory 197696 kb
Host smart-82501e93-7a73-41a1-8a13-c93c2b4a9aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552192992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.552192992
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1988305079
Short name T739
Test name
Test status
Simulation time 130516406 ps
CPU time 1.07 seconds
Started Jun 22 04:33:56 PM PDT 24
Finished Jun 22 04:33:58 PM PDT 24
Peak memory 197648 kb
Host smart-6aadc6da-9de5-45ab-adb3-50a0b918e5d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988305079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1988305079
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3103571129
Short name T732
Test name
Test status
Simulation time 68399763 ps
CPU time 0.92 seconds
Started Jun 22 04:34:04 PM PDT 24
Finished Jun 22 04:34:07 PM PDT 24
Peak memory 197516 kb
Host smart-ef800070-eee8-4d15-b87e-094e34bc5685
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103571129 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3103571129
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4133300849
Short name T775
Test name
Test status
Simulation time 36638442 ps
CPU time 0.61 seconds
Started Jun 22 04:33:02 PM PDT 24
Finished Jun 22 04:33:03 PM PDT 24
Peak memory 193936 kb
Host smart-fb277f0d-dfc9-456e-a0fc-0b8f5f187ff6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133300849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4133300849
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.4190717625
Short name T749
Test name
Test status
Simulation time 12145749 ps
CPU time 0.6 seconds
Started Jun 22 04:33:01 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 193872 kb
Host smart-7c3139d0-550c-4a40-8540-ee4164328ffe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190717625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.4190717625
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1212937942
Short name T811
Test name
Test status
Simulation time 25924045 ps
CPU time 0.74 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 195772 kb
Host smart-f479a219-1917-4f22-9d32-5c34b8466b48
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212937942 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1212937942
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3326887499
Short name T733
Test name
Test status
Simulation time 878731929 ps
CPU time 2.83 seconds
Started Jun 22 04:32:58 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 197660 kb
Host smart-017c1ea9-e87b-4033-a1ff-9835cc05fe72
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326887499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3326887499
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.102780945
Short name T35
Test name
Test status
Simulation time 375925461 ps
CPU time 1.44 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:55 PM PDT 24
Peak memory 198064 kb
Host smart-ca137cec-2c3f-41eb-8df6-2de414370d12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102780945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.102780945
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.448401477
Short name T780
Test name
Test status
Simulation time 40780632 ps
CPU time 0.96 seconds
Started Jun 22 04:32:48 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 197516 kb
Host smart-8f43a07d-a4c8-4d35-b99c-b87671b88680
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448401477 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.448401477
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.1398725478
Short name T77
Test name
Test status
Simulation time 36562359 ps
CPU time 0.63 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 195180 kb
Host smart-611bc76d-f44f-4272-aa5d-52f659ad1990
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398725478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.1398725478
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3345666711
Short name T799
Test name
Test status
Simulation time 18770294 ps
CPU time 0.58 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 193292 kb
Host smart-5938a990-187d-4bd5-bbbc-770fe0f64995
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345666711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3345666711
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3172726091
Short name T70
Test name
Test status
Simulation time 121914977 ps
CPU time 0.83 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 195720 kb
Host smart-3840c37b-9550-4610-9352-bb0e9f885f39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172726091 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3172726091
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2664905642
Short name T822
Test name
Test status
Simulation time 123059503 ps
CPU time 1.71 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 197636 kb
Host smart-5f30ffa5-567b-483e-9170-766c0e722f16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664905642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2664905642
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.118021314
Short name T790
Test name
Test status
Simulation time 348682368 ps
CPU time 1.34 seconds
Started Jun 22 04:32:51 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 197668 kb
Host smart-5c0b00cc-f506-4ff7-b302-a347a2df29cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118021314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.118021314
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3478533176
Short name T753
Test name
Test status
Simulation time 48158878 ps
CPU time 0.9 seconds
Started Jun 22 04:33:13 PM PDT 24
Finished Jun 22 04:33:15 PM PDT 24
Peak memory 197420 kb
Host smart-370b5eb9-006f-449b-a718-74b1b2e4347f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478533176 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3478533176
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2127060884
Short name T89
Test name
Test status
Simulation time 62178126 ps
CPU time 0.56 seconds
Started Jun 22 04:32:48 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 193524 kb
Host smart-bdc14ee3-3b7f-4475-9567-756158b358c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127060884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2127060884
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2973891796
Short name T730
Test name
Test status
Simulation time 45145314 ps
CPU time 0.6 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 193952 kb
Host smart-592ed58b-b96a-4966-a2a2-09c8d0573afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973891796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2973891796
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1540048333
Short name T825
Test name
Test status
Simulation time 30206870 ps
CPU time 0.83 seconds
Started Jun 22 04:32:54 PM PDT 24
Finished Jun 22 04:32:56 PM PDT 24
Peak memory 196472 kb
Host smart-1f848394-b0ad-452e-8b9d-1ffee38b0d19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540048333 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1540048333
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3229819706
Short name T802
Test name
Test status
Simulation time 209379092 ps
CPU time 2.26 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 197660 kb
Host smart-cd027981-0c23-4be2-9f1f-118c64ad0555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229819706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3229819706
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3614537101
Short name T813
Test name
Test status
Simulation time 63240566 ps
CPU time 0.65 seconds
Started Jun 22 04:32:50 PM PDT 24
Finished Jun 22 04:32:52 PM PDT 24
Peak memory 196564 kb
Host smart-5cb7f89f-46d9-4af5-8621-0b30b9acab7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614537101 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3614537101
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1563276576
Short name T812
Test name
Test status
Simulation time 31038384 ps
CPU time 0.57 seconds
Started Jun 22 04:32:48 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 192952 kb
Host smart-812872c5-8447-46a4-999e-b814e73dd84a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563276576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1563276576
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1954490382
Short name T846
Test name
Test status
Simulation time 12668496 ps
CPU time 0.64 seconds
Started Jun 22 04:32:58 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 193412 kb
Host smart-5cf069d6-4eb9-43af-8e8f-2b87b6440325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954490382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1954490382
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.70676752
Short name T801
Test name
Test status
Simulation time 56369142 ps
CPU time 0.81 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:32:56 PM PDT 24
Peak memory 196536 kb
Host smart-73eb813d-1fb6-4331-8afe-f58556825bb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70676752 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.gpio_same_csr_outstanding.70676752
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3819885019
Short name T721
Test name
Test status
Simulation time 42675326 ps
CPU time 2.2 seconds
Started Jun 22 04:32:48 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 197720 kb
Host smart-f1a0ac09-1640-48b3-9d56-7b45348dfb4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819885019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3819885019
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.430090263
Short name T39
Test name
Test status
Simulation time 90097468 ps
CPU time 1.13 seconds
Started Jun 22 04:32:53 PM PDT 24
Finished Jun 22 04:32:55 PM PDT 24
Peak memory 197708 kb
Host smart-62650b03-3367-4544-829f-3c333e46b329
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430090263 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.gpio_tl_intg_err.430090263
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.989894791
Short name T79
Test name
Test status
Simulation time 12863635 ps
CPU time 0.71 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 194168 kb
Host smart-4b431de3-1954-47e3-92ac-32056a817fd1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989894791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.989894791
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1295040452
Short name T827
Test name
Test status
Simulation time 124407399 ps
CPU time 1.52 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 197664 kb
Host smart-56578838-fe41-4a47-aced-01f01d295656
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295040452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1295040452
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.317588766
Short name T800
Test name
Test status
Simulation time 14821282 ps
CPU time 0.6 seconds
Started Jun 22 04:32:33 PM PDT 24
Finished Jun 22 04:32:35 PM PDT 24
Peak memory 194308 kb
Host smart-708fa702-d475-424b-8708-1304e186afa2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317588766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.317588766
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2074001653
Short name T840
Test name
Test status
Simulation time 135852789 ps
CPU time 1.52 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:36 PM PDT 24
Peak memory 197708 kb
Host smart-ba6d7e23-3ed6-4d4c-b241-62fb2b1d311f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074001653 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2074001653
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.706213962
Short name T766
Test name
Test status
Simulation time 11795720 ps
CPU time 0.56 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 194124 kb
Host smart-a4177c0f-d0a3-4580-8618-cfff65ac002f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706213962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.706213962
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.716429430
Short name T748
Test name
Test status
Simulation time 17240294 ps
CPU time 0.62 seconds
Started Jun 22 04:32:38 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 193292 kb
Host smart-004e94cc-bb29-4240-97ba-4261cd1609f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716429430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.716429430
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3055863473
Short name T83
Test name
Test status
Simulation time 461484443 ps
CPU time 0.76 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 195532 kb
Host smart-9dffe4ba-66cd-4c73-b61f-b0a59f434a12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055863473 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3055863473
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.199039450
Short name T836
Test name
Test status
Simulation time 51711002 ps
CPU time 2.57 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 197660 kb
Host smart-c7b4ecfd-5856-4503-9e83-088cd48f2099
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199039450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.199039450
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3400518001
Short name T36
Test name
Test status
Simulation time 48757389 ps
CPU time 0.86 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 197456 kb
Host smart-ed1f34ea-a492-4ec1-b640-9c1e2e1ed0e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400518001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3400518001
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.3683038972
Short name T842
Test name
Test status
Simulation time 15366611 ps
CPU time 0.57 seconds
Started Jun 22 04:32:50 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 193976 kb
Host smart-25bdc77a-fb44-4993-b4dc-e826e1788b6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683038972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.3683038972
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2400871243
Short name T729
Test name
Test status
Simulation time 17426232 ps
CPU time 0.67 seconds
Started Jun 22 04:33:10 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 193356 kb
Host smart-cfd5f3c5-f7ea-40b2-84f9-9ac89d2e8269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400871243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2400871243
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1337456155
Short name T837
Test name
Test status
Simulation time 36818528 ps
CPU time 0.57 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 193212 kb
Host smart-66e55e9d-e791-4c56-b835-1aa2f4dc0e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337456155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1337456155
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.987412198
Short name T834
Test name
Test status
Simulation time 18196530 ps
CPU time 0.62 seconds
Started Jun 22 04:33:00 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 193312 kb
Host smart-0407cccd-7e2e-4f51-a422-f9a9da21e67d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987412198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.987412198
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2912931172
Short name T758
Test name
Test status
Simulation time 13321953 ps
CPU time 0.63 seconds
Started Jun 22 04:33:03 PM PDT 24
Finished Jun 22 04:33:04 PM PDT 24
Peak memory 193332 kb
Host smart-5b51c8ef-d235-419f-8d53-0e350605eeea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912931172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2912931172
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.3756835877
Short name T724
Test name
Test status
Simulation time 11316988 ps
CPU time 0.58 seconds
Started Jun 22 04:32:57 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 193896 kb
Host smart-d69a6061-1495-430e-a81d-9b3de484ed3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756835877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.3756835877
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.26064476
Short name T728
Test name
Test status
Simulation time 18679038 ps
CPU time 0.61 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 193908 kb
Host smart-ece132e2-a986-41bc-b470-903bd557a281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26064476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.26064476
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2211136008
Short name T765
Test name
Test status
Simulation time 28200610 ps
CPU time 0.58 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 193232 kb
Host smart-7ab117d3-20ed-43e0-8b54-4082b0331355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211136008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2211136008
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1290824575
Short name T768
Test name
Test status
Simulation time 17814675 ps
CPU time 0.55 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 193224 kb
Host smart-36f842b8-5988-4a6f-a461-e839b3c11332
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290824575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1290824575
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3783461034
Short name T762
Test name
Test status
Simulation time 28938964 ps
CPU time 0.57 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:50 PM PDT 24
Peak memory 193280 kb
Host smart-749f21eb-2bea-46b4-a811-818c3bf6cca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783461034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3783461034
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2557648912
Short name T782
Test name
Test status
Simulation time 19633214 ps
CPU time 0.69 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 193992 kb
Host smart-02cd6a1d-10f9-4520-8635-84cbb93b39f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557648912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2557648912
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4169162791
Short name T786
Test name
Test status
Simulation time 59367366 ps
CPU time 2.12 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 196540 kb
Host smart-6878ca4a-9f11-428b-ab20-d604274d48af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169162791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4169162791
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2163498667
Short name T803
Test name
Test status
Simulation time 16928241 ps
CPU time 0.61 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 194268 kb
Host smart-327b2de1-2bac-4957-ad6d-d58f7ad00245
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163498667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2163498667
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.82592541
Short name T747
Test name
Test status
Simulation time 19080262 ps
CPU time 0.93 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:38 PM PDT 24
Peak memory 197452 kb
Host smart-bff9adde-df11-4bd2-af67-42ace8d9402c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82592541 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.82592541
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.1442911972
Short name T797
Test name
Test status
Simulation time 16317904 ps
CPU time 0.64 seconds
Started Jun 22 04:32:34 PM PDT 24
Finished Jun 22 04:32:37 PM PDT 24
Peak memory 194412 kb
Host smart-16341eab-b948-4597-8368-5bbe0240984c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442911972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.1442911972
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3860995346
Short name T751
Test name
Test status
Simulation time 55106947 ps
CPU time 0.59 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 193344 kb
Host smart-6b3e2486-f434-4653-8de5-85ebcd3ba740
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860995346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3860995346
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.4011952982
Short name T68
Test name
Test status
Simulation time 36360570 ps
CPU time 0.74 seconds
Started Jun 22 04:32:35 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 195524 kb
Host smart-35d6d879-a671-4441-bc78-5799c14c8d6e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011952982 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.4011952982
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.2552294199
Short name T757
Test name
Test status
Simulation time 170336289 ps
CPU time 1.12 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 197720 kb
Host smart-3a90e517-a429-4887-acae-da88181a7415
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552294199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.2552294199
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1538425414
Short name T820
Test name
Test status
Simulation time 157740806 ps
CPU time 0.85 seconds
Started Jun 22 04:32:32 PM PDT 24
Finished Jun 22 04:32:34 PM PDT 24
Peak memory 196804 kb
Host smart-ba7df4f7-cd06-4217-b2e0-2ac6e62095a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538425414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1538425414
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3520411179
Short name T830
Test name
Test status
Simulation time 40453265 ps
CPU time 0.58 seconds
Started Jun 22 04:33:00 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 193632 kb
Host smart-950fc198-9ac8-44dc-b01d-4bd7278c1943
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520411179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3520411179
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2877217072
Short name T726
Test name
Test status
Simulation time 35212724 ps
CPU time 0.57 seconds
Started Jun 22 04:32:59 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 193244 kb
Host smart-d177d1dc-fdd6-46c9-b8ba-a4225e3fa416
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877217072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2877217072
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2666987109
Short name T761
Test name
Test status
Simulation time 26516757 ps
CPU time 0.6 seconds
Started Jun 22 04:33:06 PM PDT 24
Finished Jun 22 04:33:07 PM PDT 24
Peak memory 193284 kb
Host smart-3b186ccc-3926-4e6a-94ce-1269ee7cbefa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666987109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2666987109
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3632094899
Short name T737
Test name
Test status
Simulation time 28381155 ps
CPU time 0.57 seconds
Started Jun 22 04:32:50 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 193196 kb
Host smart-adf3ebc1-08e3-468f-b708-d00854156d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632094899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3632094899
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3409255994
Short name T779
Test name
Test status
Simulation time 25477946 ps
CPU time 0.54 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 193244 kb
Host smart-eee6259b-3025-46d0-9bec-30e4446263a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409255994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3409255994
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3504709409
Short name T838
Test name
Test status
Simulation time 54881826 ps
CPU time 0.64 seconds
Started Jun 22 04:32:58 PM PDT 24
Finished Jun 22 04:33:00 PM PDT 24
Peak memory 193284 kb
Host smart-6f28223c-0c1c-4f6e-bd28-4009257169a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504709409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3504709409
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.779083550
Short name T720
Test name
Test status
Simulation time 16889211 ps
CPU time 0.61 seconds
Started Jun 22 04:33:01 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 193908 kb
Host smart-0d4d277a-3fbe-4e81-9bb4-89432e81b1b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779083550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.779083550
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3639432283
Short name T742
Test name
Test status
Simulation time 31697290 ps
CPU time 0.56 seconds
Started Jun 22 04:33:02 PM PDT 24
Finished Jun 22 04:33:03 PM PDT 24
Peak memory 193252 kb
Host smart-2a836005-f02e-487d-9e3b-37b7a761172a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639432283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3639432283
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3285413303
Short name T722
Test name
Test status
Simulation time 30325499 ps
CPU time 0.61 seconds
Started Jun 22 04:33:01 PM PDT 24
Finished Jun 22 04:33:02 PM PDT 24
Peak memory 193240 kb
Host smart-b9d7200f-97ff-42a3-945b-7b7230ddf5a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285413303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3285413303
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.1767993951
Short name T787
Test name
Test status
Simulation time 44032280 ps
CPU time 0.56 seconds
Started Jun 22 04:33:14 PM PDT 24
Finished Jun 22 04:33:16 PM PDT 24
Peak memory 193276 kb
Host smart-561de77d-905f-4c43-9ced-f1fd038283bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767993951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.1767993951
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.948696385
Short name T75
Test name
Test status
Simulation time 31608078 ps
CPU time 0.84 seconds
Started Jun 22 04:32:45 PM PDT 24
Finished Jun 22 04:32:46 PM PDT 24
Peak memory 195688 kb
Host smart-8fc8d79c-64de-47ec-b221-5cbc96777717
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948696385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.948696385
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.1748404001
Short name T736
Test name
Test status
Simulation time 1015388166 ps
CPU time 1.52 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 197664 kb
Host smart-2ad391db-3014-4dc1-a761-dffad7df1529
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748404001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.1748404001
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1172527343
Short name T78
Test name
Test status
Simulation time 15369493 ps
CPU time 0.7 seconds
Started Jun 22 04:32:39 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 194640 kb
Host smart-43776c9c-b566-4a04-9d0e-99756fc58ffd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172527343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1172527343
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.558318388
Short name T771
Test name
Test status
Simulation time 109828864 ps
CPU time 1.43 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 197696 kb
Host smart-887169dd-24c2-4c4f-9870-9a859266b914
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558318388 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.558318388
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1977930199
Short name T731
Test name
Test status
Simulation time 16948535 ps
CPU time 0.61 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 194564 kb
Host smart-99303c8c-1b89-4ea0-8693-c9940af6660f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977930199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1977930199
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3586405563
Short name T839
Test name
Test status
Simulation time 14500543 ps
CPU time 0.56 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 193204 kb
Host smart-242d81ec-f162-4990-8d82-a48d58e3c9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586405563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3586405563
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2512733673
Short name T816
Test name
Test status
Simulation time 31887851 ps
CPU time 0.72 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:41 PM PDT 24
Peak memory 195416 kb
Host smart-905725a4-ae75-4da8-98b7-3b80ebeffe6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512733673 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2512733673
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1978242077
Short name T784
Test name
Test status
Simulation time 183579773 ps
CPU time 1.98 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 197680 kb
Host smart-e3b398bb-5c27-4756-92da-94b2c183d7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978242077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1978242077
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2105875858
Short name T809
Test name
Test status
Simulation time 75511344 ps
CPU time 1.11 seconds
Started Jun 22 04:32:38 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 197608 kb
Host smart-9304712c-b634-468d-80d3-5ad2981157f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105875858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2105875858
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2584188482
Short name T844
Test name
Test status
Simulation time 27907085 ps
CPU time 0.62 seconds
Started Jun 22 04:33:03 PM PDT 24
Finished Jun 22 04:33:04 PM PDT 24
Peak memory 193588 kb
Host smart-e5d0cb4b-8cf8-4a31-a1f7-a84f792cc117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584188482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2584188482
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1307494110
Short name T738
Test name
Test status
Simulation time 13751250 ps
CPU time 0.57 seconds
Started Jun 22 04:32:51 PM PDT 24
Finished Jun 22 04:32:52 PM PDT 24
Peak memory 193952 kb
Host smart-152f2fd0-1fc0-4ecd-bc0e-74fccf670676
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307494110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1307494110
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.473666857
Short name T788
Test name
Test status
Simulation time 104878631 ps
CPU time 0.58 seconds
Started Jun 22 04:32:53 PM PDT 24
Finished Jun 22 04:32:54 PM PDT 24
Peak memory 193412 kb
Host smart-8a8a27cb-0e0d-4238-9731-46c9dc54eb80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473666857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.473666857
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.312855683
Short name T778
Test name
Test status
Simulation time 16346362 ps
CPU time 0.59 seconds
Started Jun 22 04:33:00 PM PDT 24
Finished Jun 22 04:33:01 PM PDT 24
Peak memory 193252 kb
Host smart-fe9ef748-b132-47ce-b9f6-b56c20f789ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312855683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.312855683
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1069111916
Short name T769
Test name
Test status
Simulation time 30171283 ps
CPU time 0.54 seconds
Started Jun 22 04:32:51 PM PDT 24
Finished Jun 22 04:32:52 PM PDT 24
Peak memory 193248 kb
Host smart-1e638040-7f55-4b7c-a043-0b427d87628b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069111916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1069111916
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.704322881
Short name T805
Test name
Test status
Simulation time 68985302 ps
CPU time 0.57 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 193268 kb
Host smart-caeaf144-7124-4ad4-b50a-55ae2b19c493
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704322881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.704322881
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2359619633
Short name T723
Test name
Test status
Simulation time 28196602 ps
CPU time 0.6 seconds
Started Jun 22 04:33:07 PM PDT 24
Finished Jun 22 04:33:08 PM PDT 24
Peak memory 193328 kb
Host smart-c27d8bb4-cfe3-4358-bb09-dd5c530ac8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359619633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2359619633
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3884034958
Short name T821
Test name
Test status
Simulation time 18975202 ps
CPU time 0.59 seconds
Started Jun 22 04:33:04 PM PDT 24
Finished Jun 22 04:33:05 PM PDT 24
Peak memory 193284 kb
Host smart-328c51d5-da36-4852-8d8d-23315bf8ce3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884034958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3884034958
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1444102239
Short name T843
Test name
Test status
Simulation time 49742424 ps
CPU time 0.59 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 193284 kb
Host smart-6a11e498-705d-4a8a-89be-995c3d70f15f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444102239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1444102239
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1669278724
Short name T734
Test name
Test status
Simulation time 133489111 ps
CPU time 0.57 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:53 PM PDT 24
Peak memory 193292 kb
Host smart-21ce7d2e-ab4e-407c-a9e9-88e4edbc4136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669278724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1669278724
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3553191744
Short name T743
Test name
Test status
Simulation time 117559051 ps
CPU time 1.24 seconds
Started Jun 22 04:32:39 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 197696 kb
Host smart-e18c1c4f-50cf-4189-a73a-5d2ece273e79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553191744 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3553191744
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1934516379
Short name T754
Test name
Test status
Simulation time 21516083 ps
CPU time 0.58 seconds
Started Jun 22 04:32:37 PM PDT 24
Finished Jun 22 04:32:40 PM PDT 24
Peak memory 194304 kb
Host smart-9f8c1c6d-836f-4cae-8e51-a552628c45ab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934516379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1934516379
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2723198989
Short name T717
Test name
Test status
Simulation time 48243683 ps
CPU time 0.58 seconds
Started Jun 22 04:32:41 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 193252 kb
Host smart-85a2209f-f3a5-4bef-a5dc-bf2ca1fcc847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723198989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2723198989
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.522705238
Short name T86
Test name
Test status
Simulation time 314765382 ps
CPU time 0.81 seconds
Started Jun 22 04:32:39 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 194888 kb
Host smart-e24159ef-7e3b-4147-884b-e3d3f483f582
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522705238 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.522705238
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.380809598
Short name T829
Test name
Test status
Simulation time 205773736 ps
CPU time 2.14 seconds
Started Jun 22 04:32:39 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 198092 kb
Host smart-e9d47502-2a5f-4657-b5f6-4a850ad54de7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380809598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.380809598
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.736607912
Short name T776
Test name
Test status
Simulation time 223454443 ps
CPU time 1.18 seconds
Started Jun 22 04:32:39 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 196680 kb
Host smart-7d4b1fed-df8b-4f16-9c27-8fbabd755e42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736607912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.736607912
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.3694079775
Short name T814
Test name
Test status
Simulation time 65695825 ps
CPU time 0.76 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 197452 kb
Host smart-e90d529b-9f4b-4df2-b3c3-66eef55ea339
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694079775 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.3694079775
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1903926947
Short name T845
Test name
Test status
Simulation time 38221375 ps
CPU time 0.56 seconds
Started Jun 22 04:32:36 PM PDT 24
Finished Jun 22 04:32:39 PM PDT 24
Peak memory 194196 kb
Host smart-9d6874b6-ef49-4a3d-b9ff-eee310821f0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903926947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1903926947
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2755255028
Short name T745
Test name
Test status
Simulation time 14748307 ps
CPU time 0.61 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:58 PM PDT 24
Peak memory 193308 kb
Host smart-3eb625fc-82ae-4156-bea2-d437fcdd6403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755255028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2755255028
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.620231187
Short name T72
Test name
Test status
Simulation time 344321215 ps
CPU time 0.72 seconds
Started Jun 22 04:32:40 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 195892 kb
Host smart-fd418552-0cc2-4436-9894-38742432cb4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620231187 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.620231187
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2976395805
Short name T792
Test name
Test status
Simulation time 421926859 ps
CPU time 2.3 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 197640 kb
Host smart-8c048671-3015-45cd-9efd-24791141f1aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976395805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2976395805
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2190832433
Short name T791
Test name
Test status
Simulation time 271193844 ps
CPU time 1.12 seconds
Started Jun 22 04:32:49 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 197604 kb
Host smart-9069304c-5dae-47bc-a2d6-4acc2d2a0172
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190832433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2190832433
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.991675768
Short name T808
Test name
Test status
Simulation time 33703282 ps
CPU time 0.94 seconds
Started Jun 22 04:32:42 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 197492 kb
Host smart-7c149e6a-2cd6-47b2-a8a1-c059a6df96e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991675768 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.991675768
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2201419445
Short name T755
Test name
Test status
Simulation time 61382767 ps
CPU time 0.62 seconds
Started Jun 22 04:32:42 PM PDT 24
Finished Jun 22 04:32:44 PM PDT 24
Peak memory 194492 kb
Host smart-ccfccc67-1995-4daa-9137-a33b269ec7ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201419445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2201419445
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.960302889
Short name T716
Test name
Test status
Simulation time 68806255 ps
CPU time 0.58 seconds
Started Jun 22 04:32:40 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 193276 kb
Host smart-aaf3d926-681a-4330-aa88-2f3f375a6037
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960302889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.960302889
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.901344629
Short name T795
Test name
Test status
Simulation time 57292757 ps
CPU time 0.75 seconds
Started Jun 22 04:32:40 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 196180 kb
Host smart-d9b77610-f32f-4c4d-8baf-12e2fbf3cdc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901344629 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.901344629
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.364613209
Short name T826
Test name
Test status
Simulation time 75325124 ps
CPU time 2.06 seconds
Started Jun 22 04:32:45 PM PDT 24
Finished Jun 22 04:32:48 PM PDT 24
Peak memory 197636 kb
Host smart-9ecbb75f-d954-4449-9727-d81dcd3a290b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364613209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.364613209
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2759726315
Short name T794
Test name
Test status
Simulation time 120737383 ps
CPU time 1.11 seconds
Started Jun 22 04:32:56 PM PDT 24
Finished Jun 22 04:32:59 PM PDT 24
Peak memory 197680 kb
Host smart-462fb511-1526-4316-a378-c141d3e94e37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759726315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2759726315
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.2805365744
Short name T796
Test name
Test status
Simulation time 124536601 ps
CPU time 1.4 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:32:57 PM PDT 24
Peak memory 197720 kb
Host smart-796a8b1e-503b-4355-94e8-2bc00530f279
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805365744 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.2805365744
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.639982309
Short name T76
Test name
Test status
Simulation time 23493914 ps
CPU time 0.6 seconds
Started Jun 22 04:32:41 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 193848 kb
Host smart-5e7281b4-c36d-4669-a8ec-954905e366a4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639982309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.639982309
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2694619687
Short name T817
Test name
Test status
Simulation time 49141482 ps
CPU time 0.6 seconds
Started Jun 22 04:32:41 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 193344 kb
Host smart-e864139b-fb41-402d-b3d3-a1e2a24d2605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694619687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2694619687
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3292979927
Short name T835
Test name
Test status
Simulation time 28024817 ps
CPU time 0.82 seconds
Started Jun 22 04:32:41 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 196548 kb
Host smart-92287d3c-f681-48c5-a03c-eb9528b8927b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292979927 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3292979927
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2332878330
Short name T774
Test name
Test status
Simulation time 76473333 ps
CPU time 1.41 seconds
Started Jun 22 04:32:43 PM PDT 24
Finished Jun 22 04:32:45 PM PDT 24
Peak memory 197660 kb
Host smart-76fa003a-73fd-4cb8-b57b-0a9b4cc55506
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332878330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2332878330
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1825057479
Short name T30
Test name
Test status
Simulation time 120184666 ps
CPU time 1.39 seconds
Started Jun 22 04:32:48 PM PDT 24
Finished Jun 22 04:32:49 PM PDT 24
Peak memory 197664 kb
Host smart-de6698cc-57ac-42bb-95c6-08abf6857b25
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825057479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1825057479
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1622244970
Short name T718
Test name
Test status
Simulation time 107294232 ps
CPU time 0.92 seconds
Started Jun 22 04:32:50 PM PDT 24
Finished Jun 22 04:32:51 PM PDT 24
Peak memory 197456 kb
Host smart-b76547d0-bb87-4bd2-8497-d446707735f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622244970 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1622244970
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2287091980
Short name T735
Test name
Test status
Simulation time 182728636 ps
CPU time 0.57 seconds
Started Jun 22 04:32:55 PM PDT 24
Finished Jun 22 04:32:56 PM PDT 24
Peak memory 193888 kb
Host smart-5a740639-0bd6-4614-bdaa-58d95478fcfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287091980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2287091980
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2545980573
Short name T793
Test name
Test status
Simulation time 28426528 ps
CPU time 0.71 seconds
Started Jun 22 04:32:40 PM PDT 24
Finished Jun 22 04:32:42 PM PDT 24
Peak memory 195236 kb
Host smart-b0c549a3-a1f4-46c9-868d-bde1d62a2a99
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545980573 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2545980573
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4191587063
Short name T719
Test name
Test status
Simulation time 199152115 ps
CPU time 1.36 seconds
Started Jun 22 04:32:40 PM PDT 24
Finished Jun 22 04:32:43 PM PDT 24
Peak memory 197664 kb
Host smart-1c6f7393-62f8-4321-943c-cc32a1771309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191587063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4191587063
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3755341146
Short name T28
Test name
Test status
Simulation time 197204871 ps
CPU time 0.82 seconds
Started Jun 22 04:32:52 PM PDT 24
Finished Jun 22 04:32:54 PM PDT 24
Peak memory 196520 kb
Host smart-68673fbc-3d41-4623-a3aa-f744eb22769a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755341146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3755341146
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2645369145
Short name T441
Test name
Test status
Simulation time 33809888 ps
CPU time 0.58 seconds
Started Jun 22 04:23:38 PM PDT 24
Finished Jun 22 04:23:38 PM PDT 24
Peak memory 193584 kb
Host smart-be9c1ef4-c96e-49b4-aaf2-8d3be43332ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645369145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2645369145
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.4124625068
Short name T481
Test name
Test status
Simulation time 71260886 ps
CPU time 0.79 seconds
Started Jun 22 04:23:34 PM PDT 24
Finished Jun 22 04:23:36 PM PDT 24
Peak memory 194260 kb
Host smart-b03900ea-c463-4c71-bced-e3db8bbf94ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124625068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.4124625068
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3217603321
Short name T355
Test name
Test status
Simulation time 397405116 ps
CPU time 13.72 seconds
Started Jun 22 04:23:55 PM PDT 24
Finished Jun 22 04:24:09 PM PDT 24
Peak memory 196684 kb
Host smart-68d3919d-691d-4c7e-9b6f-a7fc1e10c343
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217603321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3217603321
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2550818111
Short name T533
Test name
Test status
Simulation time 67661054 ps
CPU time 0.91 seconds
Started Jun 22 04:23:42 PM PDT 24
Finished Jun 22 04:23:43 PM PDT 24
Peak memory 197420 kb
Host smart-a80a6507-5059-41a1-a38a-954823a68d66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550818111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2550818111
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3340898189
Short name T365
Test name
Test status
Simulation time 75019473 ps
CPU time 1.35 seconds
Started Jun 22 04:24:48 PM PDT 24
Finished Jun 22 04:24:50 PM PDT 24
Peak memory 195560 kb
Host smart-710a625d-eaf8-4e5c-a454-25f6736615a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340898189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3340898189
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.545310573
Short name T623
Test name
Test status
Simulation time 128301908 ps
CPU time 1.52 seconds
Started Jun 22 04:23:56 PM PDT 24
Finished Jun 22 04:23:58 PM PDT 24
Peak memory 196700 kb
Host smart-1d91ed95-8673-458c-925c-38c478715564
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545310573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 0.gpio_intr_with_filter_rand_intr_event.545310573
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1199640190
Short name T584
Test name
Test status
Simulation time 129847883 ps
CPU time 2.53 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:15 PM PDT 24
Peak memory 196672 kb
Host smart-80c160ea-bb87-47b9-87a6-e634652985f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199640190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1199640190
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.4100233008
Short name T173
Test name
Test status
Simulation time 265695538 ps
CPU time 1.11 seconds
Started Jun 22 04:23:41 PM PDT 24
Finished Jun 22 04:23:42 PM PDT 24
Peak memory 195876 kb
Host smart-5b69ff00-d3be-43eb-a33d-eb996977880c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100233008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.4100233008
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3829327513
Short name T217
Test name
Test status
Simulation time 656397426 ps
CPU time 1.24 seconds
Started Jun 22 04:23:55 PM PDT 24
Finished Jun 22 04:23:57 PM PDT 24
Peak memory 195972 kb
Host smart-a31ba80c-ddf3-406e-b6bc-a6a1e61ebc96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829327513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3829327513
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.1981673706
Short name T238
Test name
Test status
Simulation time 493182563 ps
CPU time 2.35 seconds
Started Jun 22 04:23:44 PM PDT 24
Finished Jun 22 04:23:46 PM PDT 24
Peak memory 198168 kb
Host smart-f7c53e5e-2041-4260-ae60-f6d46483997e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981673706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.1981673706
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.61749392
Short name T42
Test name
Test status
Simulation time 37673946 ps
CPU time 0.81 seconds
Started Jun 22 04:24:07 PM PDT 24
Finished Jun 22 04:24:09 PM PDT 24
Peak memory 213904 kb
Host smart-b90e80b7-8acf-4a39-bddd-1169238d6758
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61749392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.61749392
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3731146047
Short name T529
Test name
Test status
Simulation time 161583656 ps
CPU time 1.34 seconds
Started Jun 22 04:23:35 PM PDT 24
Finished Jun 22 04:23:37 PM PDT 24
Peak memory 195760 kb
Host smart-a3e9ba55-b68d-4932-b533-b98c3d577e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731146047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3731146047
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3041440673
Short name T297
Test name
Test status
Simulation time 41773697 ps
CPU time 1.07 seconds
Started Jun 22 04:23:36 PM PDT 24
Finished Jun 22 04:23:37 PM PDT 24
Peak memory 195992 kb
Host smart-5bc34acf-22c1-40b6-9466-539af697b90c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041440673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3041440673
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3554239382
Short name T416
Test name
Test status
Simulation time 7683349020 ps
CPU time 107.12 seconds
Started Jun 22 04:23:50 PM PDT 24
Finished Jun 22 04:25:38 PM PDT 24
Peak memory 197916 kb
Host smart-da877952-1ba1-4fbf-8496-772a4821f95f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554239382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3554239382
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1204680977
Short name T614
Test name
Test status
Simulation time 231746889410 ps
CPU time 556.09 seconds
Started Jun 22 04:24:06 PM PDT 24
Finished Jun 22 04:33:24 PM PDT 24
Peak memory 196868 kb
Host smart-1f08647f-437f-4f8d-90e8-b9c901646a0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1204680977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1204680977
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.568454457
Short name T275
Test name
Test status
Simulation time 12091949 ps
CPU time 0.66 seconds
Started Jun 22 04:24:07 PM PDT 24
Finished Jun 22 04:24:08 PM PDT 24
Peak memory 192800 kb
Host smart-2acdb9ec-47ad-420a-937c-4905aeb4e344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568454457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.568454457
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1908531940
Short name T237
Test name
Test status
Simulation time 23296443 ps
CPU time 0.81 seconds
Started Jun 22 04:24:18 PM PDT 24
Finished Jun 22 04:24:20 PM PDT 24
Peak memory 195636 kb
Host smart-7709d4c3-e431-46a1-bf45-af642d6c7cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908531940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1908531940
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.17019054
Short name T595
Test name
Test status
Simulation time 2625864039 ps
CPU time 22.23 seconds
Started Jun 22 04:23:54 PM PDT 24
Finished Jun 22 04:24:16 PM PDT 24
Peak memory 196664 kb
Host smart-4eb1f4be-7114-457a-addf-c996e8ba6dee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress.17019054
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.3113034908
Short name T578
Test name
Test status
Simulation time 43648333 ps
CPU time 0.83 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 195612 kb
Host smart-ea5b5d39-d60e-4f5d-8527-88c7edff1db2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113034908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.3113034908
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.2666977299
Short name T527
Test name
Test status
Simulation time 803478176 ps
CPU time 0.97 seconds
Started Jun 22 04:24:10 PM PDT 24
Finished Jun 22 04:24:12 PM PDT 24
Peak memory 195560 kb
Host smart-dc396db2-76fd-488b-bd84-e25b93f87709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666977299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.2666977299
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1067435620
Short name T231
Test name
Test status
Simulation time 68271385 ps
CPU time 2.76 seconds
Started Jun 22 04:24:03 PM PDT 24
Finished Jun 22 04:24:07 PM PDT 24
Peak memory 197928 kb
Host smart-17771af5-c4ae-4381-af3c-8480b8a3718c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067435620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1067435620
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.4167891226
Short name T239
Test name
Test status
Simulation time 76012636 ps
CPU time 1.17 seconds
Started Jun 22 04:23:53 PM PDT 24
Finished Jun 22 04:23:54 PM PDT 24
Peak memory 195728 kb
Host smart-57468af4-9417-4ba5-ac18-c7a1d089ddfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167891226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
4167891226
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.1049377445
Short name T306
Test name
Test status
Simulation time 63044909 ps
CPU time 1.16 seconds
Started Jun 22 04:23:40 PM PDT 24
Finished Jun 22 04:23:42 PM PDT 24
Peak memory 195032 kb
Host smart-a71713f5-9991-4cd9-9173-46e506dd5cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049377445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.1049377445
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2312636445
Short name T62
Test name
Test status
Simulation time 16524058 ps
CPU time 0.68 seconds
Started Jun 22 04:23:59 PM PDT 24
Finished Jun 22 04:24:00 PM PDT 24
Peak memory 195120 kb
Host smart-ee113b04-e228-44b1-ae79-b21c2c12730e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312636445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2312636445
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2706568313
Short name T463
Test name
Test status
Simulation time 365694715 ps
CPU time 5.02 seconds
Started Jun 22 04:23:51 PM PDT 24
Finished Jun 22 04:23:57 PM PDT 24
Peak memory 196960 kb
Host smart-76016b1c-406e-4b45-af8a-3049365faf66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706568313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2706568313
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3896025647
Short name T32
Test name
Test status
Simulation time 6049487629 ps
CPU time 1.44 seconds
Started Jun 22 04:23:45 PM PDT 24
Finished Jun 22 04:23:47 PM PDT 24
Peak memory 214320 kb
Host smart-94bfb457-658d-4aa8-9099-acbb410c2f63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896025647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3896025647
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.1033756296
Short name T418
Test name
Test status
Simulation time 28113103 ps
CPU time 0.82 seconds
Started Jun 22 04:23:54 PM PDT 24
Finished Jun 22 04:23:55 PM PDT 24
Peak memory 194916 kb
Host smart-e3d806ee-abba-4d95-8bfe-c8cc721edad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033756296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.1033756296
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2117361381
Short name T456
Test name
Test status
Simulation time 123971213 ps
CPU time 1.3 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:27 PM PDT 24
Peak memory 195288 kb
Host smart-4050a64f-bff2-4f32-b8f9-b7855514bceb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117361381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2117361381
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1564873623
Short name T202
Test name
Test status
Simulation time 2108038694 ps
CPU time 21.46 seconds
Started Jun 22 04:24:10 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 197804 kb
Host smart-a33eb4be-cbd9-471c-8048-20ee41ef052a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564873623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1564873623
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2593096591
Short name T547
Test name
Test status
Simulation time 39781807344 ps
CPU time 494.08 seconds
Started Jun 22 04:23:44 PM PDT 24
Finished Jun 22 04:31:59 PM PDT 24
Peak memory 197148 kb
Host smart-9c6ebf31-dfa0-4000-8b3f-5575bfcf6cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2593096591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2593096591
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1075727116
Short name T696
Test name
Test status
Simulation time 19037919 ps
CPU time 0.55 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 193476 kb
Host smart-9cdfacc2-353d-4708-9333-7dd1c69df56e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075727116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1075727116
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.4155526118
Short name T410
Test name
Test status
Simulation time 26788532 ps
CPU time 0.6 seconds
Started Jun 22 04:24:14 PM PDT 24
Finished Jun 22 04:24:16 PM PDT 24
Peak memory 193632 kb
Host smart-d11ca382-e586-4e45-9960-c8dcf25be009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155526118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.4155526118
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3823249682
Short name T638
Test name
Test status
Simulation time 2228670769 ps
CPU time 12.39 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:25 PM PDT 24
Peak memory 196680 kb
Host smart-a67b82a0-a8f7-4dfe-adf1-9cf0aca32864
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823249682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3823249682
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3125687289
Short name T348
Test name
Test status
Simulation time 56382026 ps
CPU time 0.72 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:10 PM PDT 24
Peak memory 194396 kb
Host smart-0771cf50-e216-4ece-b2b0-e5436391f210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125687289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3125687289
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2002961704
Short name T148
Test name
Test status
Simulation time 48155475 ps
CPU time 0.99 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:10 PM PDT 24
Peak memory 196656 kb
Host smart-003e6168-8ff4-4ec6-a17e-97ecbc0a9a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002961704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2002961704
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3964431558
Short name T221
Test name
Test status
Simulation time 200888668 ps
CPU time 2.1 seconds
Started Jun 22 04:24:16 PM PDT 24
Finished Jun 22 04:24:19 PM PDT 24
Peak memory 196152 kb
Host smart-d988b3e8-1377-430d-975a-6d068d0e35ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964431558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3964431558
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3465140527
Short name T424
Test name
Test status
Simulation time 108995012 ps
CPU time 1.96 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 196004 kb
Host smart-9b3c6d6a-bccd-40f9-9609-812ba42a4e0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465140527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3465140527
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1197234140
Short name T508
Test name
Test status
Simulation time 108561238 ps
CPU time 1.25 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 195332 kb
Host smart-0c45eac0-15d6-4dae-90a0-b50d6c950c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197234140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1197234140
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3861997633
Short name T230
Test name
Test status
Simulation time 20299123 ps
CPU time 0.86 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 195272 kb
Host smart-fc409bb5-26ff-4138-89df-16e4cd84f586
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861997633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3861997633
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1102849163
Short name T3
Test name
Test status
Simulation time 2415612042 ps
CPU time 3.19 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:15 PM PDT 24
Peak memory 197692 kb
Host smart-10bf9868-7885-4091-8675-35f67e1faa4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102849163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1102849163
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.32547068
Short name T492
Test name
Test status
Simulation time 55531023 ps
CPU time 0.91 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 195940 kb
Host smart-d80a2d85-cd23-4e37-b2a3-ad50880c0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32547068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.32547068
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1016834722
Short name T555
Test name
Test status
Simulation time 286453084 ps
CPU time 1.28 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:24:17 PM PDT 24
Peak memory 196352 kb
Host smart-39b4e228-8725-4af9-9af1-067ccb3b0285
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016834722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1016834722
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3852168342
Short name T282
Test name
Test status
Simulation time 16766538493 ps
CPU time 52.05 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:25:08 PM PDT 24
Peak memory 197112 kb
Host smart-09466b82-80dd-41f0-8987-38f0887773d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852168342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3852168342
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1465865314
Short name T59
Test name
Test status
Simulation time 277784676378 ps
CPU time 1091.52 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:42:28 PM PDT 24
Peak memory 197996 kb
Host smart-02918fbc-2946-42b1-ab5e-773dec6648cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1465865314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1465865314
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2260405937
Short name T257
Test name
Test status
Simulation time 18610150 ps
CPU time 0.57 seconds
Started Jun 22 04:24:16 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 194308 kb
Host smart-e5ecc246-a76b-46e3-817f-c26581eebe4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260405937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2260405937
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3860457378
Short name T63
Test name
Test status
Simulation time 153038071 ps
CPU time 0.94 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:24:17 PM PDT 24
Peak memory 195504 kb
Host smart-e5c215bf-e034-4add-8a4a-6eacbe60b981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860457378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3860457378
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2750952977
Short name T102
Test name
Test status
Simulation time 501337448 ps
CPU time 26.87 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:49 PM PDT 24
Peak memory 197912 kb
Host smart-7e9adfda-88cd-46bc-ab84-4d285941f7e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750952977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2750952977
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2810636515
Short name T677
Test name
Test status
Simulation time 93386011 ps
CPU time 1.06 seconds
Started Jun 22 04:24:16 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 197736 kb
Host smart-5a44e2ac-8a34-4b91-a419-801b051bc65a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810636515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2810636515
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2697648661
Short name T513
Test name
Test status
Simulation time 43905293 ps
CPU time 0.68 seconds
Started Jun 22 04:24:10 PM PDT 24
Finished Jun 22 04:24:12 PM PDT 24
Peak memory 194784 kb
Host smart-c63cf4e9-cbea-45d5-ba57-04b559844e10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697648661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2697648661
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1140882500
Short name T127
Test name
Test status
Simulation time 142699786 ps
CPU time 1.51 seconds
Started Jun 22 04:24:06 PM PDT 24
Finished Jun 22 04:24:09 PM PDT 24
Peak memory 196464 kb
Host smart-045a06af-0784-46b1-993f-a6895ac8ebf3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140882500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1140882500
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1565755407
Short name T359
Test name
Test status
Simulation time 166202594 ps
CPU time 1.27 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:24 PM PDT 24
Peak memory 197112 kb
Host smart-fa91fb3c-42f1-4dc3-8448-b6cc8e88fb12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565755407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1565755407
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2971240711
Short name T440
Test name
Test status
Simulation time 27614113 ps
CPU time 0.93 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 195716 kb
Host smart-cc291f38-b0f6-403e-bdc1-39c3035d9f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971240711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2971240711
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.808945976
Short name T618
Test name
Test status
Simulation time 25988330 ps
CPU time 0.99 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:25 PM PDT 24
Peak memory 196460 kb
Host smart-2fee92f7-ca3a-465e-8d8c-d624b5d717ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808945976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.808945976
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.104879168
Short name T109
Test name
Test status
Simulation time 115052075 ps
CPU time 1.98 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 197804 kb
Host smart-1cf38ac7-4cc6-4f58-abaf-45ab22119199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104879168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.104879168
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.137821357
Short name T15
Test name
Test status
Simulation time 138527135 ps
CPU time 0.97 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:27 PM PDT 24
Peak memory 195492 kb
Host smart-22530e72-1362-4dfb-be83-c5adb35ca9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137821357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.137821357
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3604940367
Short name T114
Test name
Test status
Simulation time 52120460 ps
CPU time 1.37 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:10 PM PDT 24
Peak memory 196452 kb
Host smart-bb33b84b-512a-4504-9c32-fe2292cd39f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604940367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3604940367
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.4273537392
Short name T2
Test name
Test status
Simulation time 47979276372 ps
CPU time 109.08 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:26:16 PM PDT 24
Peak memory 197920 kb
Host smart-35d7acd3-1e67-47f8-9c7d-f4cd2b9abf67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273537392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.4273537392
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.1150247318
Short name T54
Test name
Test status
Simulation time 153635294217 ps
CPU time 1799.05 seconds
Started Jun 22 04:24:22 PM PDT 24
Finished Jun 22 04:54:23 PM PDT 24
Peak memory 197988 kb
Host smart-2ff82ffa-ca61-4ecd-be30-73ca72105db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1150247318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.1150247318
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1188189434
Short name T524
Test name
Test status
Simulation time 72322720 ps
CPU time 0.56 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 193816 kb
Host smart-64250c56-b26e-49cb-90d0-fb5b0be35d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188189434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1188189434
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1954605059
Short name T184
Test name
Test status
Simulation time 37394160 ps
CPU time 0.82 seconds
Started Jun 22 04:24:20 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 195684 kb
Host smart-f6cf2c36-9d4f-4300-843b-76a7fe200a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954605059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1954605059
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.785694918
Short name T228
Test name
Test status
Simulation time 165769768 ps
CPU time 5.61 seconds
Started Jun 22 04:24:12 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 196060 kb
Host smart-63c3b415-d645-4932-acf7-77013737fd04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785694918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.785694918
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1282827627
Short name T453
Test name
Test status
Simulation time 620435469 ps
CPU time 0.9 seconds
Started Jun 22 04:24:17 PM PDT 24
Finished Jun 22 04:24:19 PM PDT 24
Peak memory 194832 kb
Host smart-516265f3-e039-4bcc-9096-52bb020bded3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282827627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1282827627
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2529861898
Short name T467
Test name
Test status
Simulation time 73764213 ps
CPU time 0.88 seconds
Started Jun 22 04:24:20 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 194380 kb
Host smart-5417805d-96c8-49f5-81d7-a69182a9b7d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529861898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2529861898
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.3954093362
Short name T135
Test name
Test status
Simulation time 42848603 ps
CPU time 1.91 seconds
Started Jun 22 04:24:14 PM PDT 24
Finished Jun 22 04:24:17 PM PDT 24
Peak memory 198296 kb
Host smart-6dc625a3-ea79-4053-b105-1e5db13d7aff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954093362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.3954093362
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.3027936023
Short name T214
Test name
Test status
Simulation time 57718601 ps
CPU time 1.92 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:24 PM PDT 24
Peak memory 195476 kb
Host smart-41c99465-227e-47a6-94d8-5deacb9c4c6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027936023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.3027936023
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1406054794
Short name T124
Test name
Test status
Simulation time 269533485 ps
CPU time 1.44 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:12 PM PDT 24
Peak memory 196300 kb
Host smart-afe7a15d-528a-410c-a04c-c199d6ea554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406054794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1406054794
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1638256639
Short name T130
Test name
Test status
Simulation time 18582260 ps
CPU time 0.75 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:23 PM PDT 24
Peak memory 195228 kb
Host smart-0483d0d3-6010-4da6-8ea3-588a26e3315d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638256639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1638256639
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2713764695
Short name T460
Test name
Test status
Simulation time 401155032 ps
CPU time 4.54 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 197744 kb
Host smart-7aa4bf26-8b81-4541-ba07-167843ae868f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713764695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2713764695
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.846410031
Short name T393
Test name
Test status
Simulation time 37387254 ps
CPU time 0.99 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 195712 kb
Host smart-408594eb-99b2-4ed9-8316-4bbf7a9f7138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846410031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.846410031
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2464684545
Short name T391
Test name
Test status
Simulation time 59266769 ps
CPU time 0.93 seconds
Started Jun 22 04:24:17 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 196036 kb
Host smart-0c352c59-c10b-437a-8074-2c08ab77c930
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464684545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2464684545
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.756454931
Short name T604
Test name
Test status
Simulation time 15401789065 ps
CPU time 197.03 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:28:42 PM PDT 24
Peak memory 197940 kb
Host smart-b1c03858-d4ad-4d59-b153-e8037e639997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756454931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.756454931
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.2706706613
Short name T55
Test name
Test status
Simulation time 36214481302 ps
CPU time 1071.66 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:42:17 PM PDT 24
Peak memory 197960 kb
Host smart-b2eccc47-410e-4b3e-a9ac-869495b51d51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2706706613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.2706706613
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.37005982
Short name T213
Test name
Test status
Simulation time 73957786 ps
CPU time 0.56 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:23 PM PDT 24
Peak memory 194024 kb
Host smart-f70dbb12-63b6-4ebb-9c6e-28205f12a863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37005982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.37005982
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.252643244
Short name T624
Test name
Test status
Simulation time 33490831 ps
CPU time 0.77 seconds
Started Jun 22 04:24:13 PM PDT 24
Finished Jun 22 04:24:14 PM PDT 24
Peak memory 194956 kb
Host smart-5bc46649-4821-42d5-9266-f0ddc94042e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252643244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.252643244
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1596169232
Short name T126
Test name
Test status
Simulation time 1101469028 ps
CPU time 8.54 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:36 PM PDT 24
Peak memory 196644 kb
Host smart-8f3c13c8-dd8b-4859-bef0-be4aa253fe38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596169232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1596169232
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.200480438
Short name T329
Test name
Test status
Simulation time 55223747 ps
CPU time 0.98 seconds
Started Jun 22 04:24:22 PM PDT 24
Finished Jun 22 04:24:25 PM PDT 24
Peak memory 196700 kb
Host smart-550d4a54-fa46-438d-98ad-20198fd276c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200480438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.200480438
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1642173912
Short name T500
Test name
Test status
Simulation time 20195966 ps
CPU time 0.64 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 193988 kb
Host smart-adab4047-f6a0-40d1-9d50-2c0b940e64f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642173912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1642173912
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2741365208
Short name T368
Test name
Test status
Simulation time 27070958 ps
CPU time 1.1 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 197464 kb
Host smart-b962b5a2-dd5b-4d49-965e-4bbf17a9ef6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741365208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2741365208
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.52369301
Short name T144
Test name
Test status
Simulation time 367798902 ps
CPU time 1.9 seconds
Started Jun 22 04:24:16 PM PDT 24
Finished Jun 22 04:24:19 PM PDT 24
Peak memory 196788 kb
Host smart-3d80f81c-e081-4200-9066-5a3a12715698
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52369301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.52369301
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.3766197538
Short name T371
Test name
Test status
Simulation time 180648365 ps
CPU time 0.94 seconds
Started Jun 22 04:24:14 PM PDT 24
Finished Jun 22 04:24:15 PM PDT 24
Peak memory 195632 kb
Host smart-c9a8c5ca-666a-467f-adb5-4561560e5a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766197538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.3766197538
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.4166962032
Short name T18
Test name
Test status
Simulation time 69240374 ps
CPU time 0.83 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:24:16 PM PDT 24
Peak memory 196348 kb
Host smart-2ddc1d88-e1e5-42bf-93c7-c872b848d97a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166962032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.4166962032
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3478340061
Short name T317
Test name
Test status
Simulation time 779662706 ps
CPU time 3.04 seconds
Started Jun 22 04:24:10 PM PDT 24
Finished Jun 22 04:24:14 PM PDT 24
Peak memory 197740 kb
Host smart-ad1d763f-21e0-40a3-875d-68129d1e3064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478340061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3478340061
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.697642175
Short name T558
Test name
Test status
Simulation time 71914088 ps
CPU time 1.32 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:27 PM PDT 24
Peak memory 195336 kb
Host smart-9d12e5ff-2fe7-4e3d-b73d-fe30151dbcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697642175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.697642175
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.351799007
Short name T256
Test name
Test status
Simulation time 196658263 ps
CPU time 0.79 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 195620 kb
Host smart-320c0f8a-113a-40c4-931f-791b315c8770
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351799007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.351799007
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1637213739
Short name T380
Test name
Test status
Simulation time 24980867865 ps
CPU time 96.57 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:26:06 PM PDT 24
Peak memory 197956 kb
Host smart-b2d701e8-656b-41a3-a56c-02555adf8688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637213739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1637213739
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2733099277
Short name T561
Test name
Test status
Simulation time 15687581 ps
CPU time 0.58 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 194444 kb
Host smart-6a692693-3ea4-4f98-9f29-be67c083db42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733099277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2733099277
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2473131530
Short name T581
Test name
Test status
Simulation time 693371621 ps
CPU time 0.86 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 196140 kb
Host smart-5c9ea0d2-c43c-413b-b581-1df21cd56321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473131530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2473131530
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.4244112078
Short name T412
Test name
Test status
Simulation time 1238338066 ps
CPU time 14.48 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:45 PM PDT 24
Peak memory 196924 kb
Host smart-19d5547e-fd34-40bf-8eb3-22a41d9b1cae
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244112078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.4244112078
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.817095194
Short name T697
Test name
Test status
Simulation time 217078467 ps
CPU time 1.05 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 196416 kb
Host smart-e7fcedda-b878-4c70-8902-eeeb2f602be7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817095194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.817095194
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.1338258326
Short name T12
Test name
Test status
Simulation time 46968010 ps
CPU time 0.86 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 197140 kb
Host smart-c09b4be1-5802-403e-8d25-2616215db02e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338258326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.1338258326
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.3651335267
Short name T664
Test name
Test status
Simulation time 460937718 ps
CPU time 2.49 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 195628 kb
Host smart-90f11644-f1c9-46df-bf6f-6e11a6520d74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651335267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.3651335267
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3805965737
Short name T658
Test name
Test status
Simulation time 66722259 ps
CPU time 1.14 seconds
Started Jun 22 04:24:16 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 195656 kb
Host smart-02814315-716e-4154-9f80-c9a543abcf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805965737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3805965737
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.3592533135
Short name T510
Test name
Test status
Simulation time 35157702 ps
CPU time 1.33 seconds
Started Jun 22 04:24:20 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 197864 kb
Host smart-3f8dda34-f043-4df8-b2ec-f443c18052ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592533135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.3592533135
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.876018183
Short name T405
Test name
Test status
Simulation time 122556191 ps
CPU time 2.84 seconds
Started Jun 22 04:24:14 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 197764 kb
Host smart-d259cfff-c5af-4dfe-a2ae-733cbe84bfc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876018183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.876018183
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.927719801
Short name T222
Test name
Test status
Simulation time 34905996 ps
CPU time 0.8 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 196116 kb
Host smart-11e0ef23-4ec7-4c48-98b9-9729674d0f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927719801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.927719801
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1819548615
Short name T358
Test name
Test status
Simulation time 49724266 ps
CPU time 1.09 seconds
Started Jun 22 04:24:22 PM PDT 24
Finished Jun 22 04:24:25 PM PDT 24
Peak memory 195976 kb
Host smart-aa370886-f16d-464b-8a7a-dfdc362bb182
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819548615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1819548615
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.690196720
Short name T636
Test name
Test status
Simulation time 8447504405 ps
CPU time 29.24 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:25:02 PM PDT 24
Peak memory 197916 kb
Host smart-3045f460-5c1d-4285-a1fe-b6067521e6f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690196720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.690196720
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1294767276
Short name T430
Test name
Test status
Simulation time 150087088284 ps
CPU time 900.49 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:39:27 PM PDT 24
Peak memory 197984 kb
Host smart-9989d157-11fa-4e80-86a0-4fe70db34d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1294767276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1294767276
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1828538205
Short name T343
Test name
Test status
Simulation time 38234301 ps
CPU time 0.55 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 193596 kb
Host smart-8be3ce55-48d5-4c9f-b359-0f00aada4f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828538205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1828538205
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3462076380
Short name T655
Test name
Test status
Simulation time 59539603 ps
CPU time 0.73 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 194880 kb
Host smart-61349f86-40cf-47f1-b041-cd5a93abf7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462076380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3462076380
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2366592740
Short name T439
Test name
Test status
Simulation time 447574629 ps
CPU time 21.51 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:46 PM PDT 24
Peak memory 197024 kb
Host smart-f730b16d-2163-4a32-8b1c-d2f0f7ea217d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366592740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2366592740
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3852225036
Short name T162
Test name
Test status
Simulation time 55858104 ps
CPU time 0.87 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:25 PM PDT 24
Peak memory 195644 kb
Host smart-637ce071-a365-4e5b-b3b6-5a734b525ede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852225036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3852225036
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.775229905
Short name T364
Test name
Test status
Simulation time 196780337 ps
CPU time 1.24 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 196016 kb
Host smart-644124a1-2508-4a94-a93c-80db34a3a476
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775229905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.775229905
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3918694789
Short name T153
Test name
Test status
Simulation time 126446224 ps
CPU time 2.85 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 197624 kb
Host smart-c3c29848-184e-4f44-841e-38d064e5cf2d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918694789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3918694789
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.892219917
Short name T603
Test name
Test status
Simulation time 218185301 ps
CPU time 1.65 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 195628 kb
Host smart-6403cbf3-b0aa-4c67-9832-a1441ed25884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892219917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
892219917
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1959313866
Short name T223
Test name
Test status
Simulation time 31354689 ps
CPU time 0.9 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:29 PM PDT 24
Peak memory 196248 kb
Host smart-df4a913f-1312-40b1-a1ea-7cf10ae158fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959313866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1959313866
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.2714252820
Short name T567
Test name
Test status
Simulation time 107422753 ps
CPU time 1.02 seconds
Started Jun 22 04:24:20 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 195792 kb
Host smart-2d2ceb6e-9633-4ad8-b62c-058bfd94afaa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714252820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.2714252820
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3209315489
Short name T542
Test name
Test status
Simulation time 1301714619 ps
CPU time 5.86 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 197784 kb
Host smart-48433540-709f-42d0-a0d2-a75184cbdcec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209315489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3209315489
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3880015138
Short name T525
Test name
Test status
Simulation time 69459253 ps
CPU time 1.2 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 196512 kb
Host smart-4fc55b43-5401-44fb-9eb3-9bd29a490885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880015138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3880015138
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.201612318
Short name T196
Test name
Test status
Simulation time 284210570 ps
CPU time 1.47 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:27 PM PDT 24
Peak memory 197680 kb
Host smart-2ca532ab-5d1b-47eb-9a0c-2045542534b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201612318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.201612318
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1542031450
Short name T473
Test name
Test status
Simulation time 16974486548 ps
CPU time 221.55 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:28:06 PM PDT 24
Peak memory 197872 kb
Host smart-d15897d0-5a6f-402a-9bc5-22bd5a294997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542031450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1542031450
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1989464683
Short name T379
Test name
Test status
Simulation time 242369890786 ps
CPU time 2332.4 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 05:03:14 PM PDT 24
Peak memory 198424 kb
Host smart-9ba10c9d-dd71-413f-b989-b59754a853f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1989464683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1989464683
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2382426435
Short name T360
Test name
Test status
Simulation time 21222444 ps
CPU time 0.59 seconds
Started Jun 22 04:24:22 PM PDT 24
Finished Jun 22 04:24:24 PM PDT 24
Peak memory 192756 kb
Host smart-04090989-8f2b-438e-b9e9-ff45e571ee0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382426435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2382426435
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.3732985852
Short name T281
Test name
Test status
Simulation time 152153457 ps
CPU time 0.89 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:23 PM PDT 24
Peak memory 195760 kb
Host smart-423438a8-7ae5-4893-b71c-031a22a09c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732985852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.3732985852
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.733881541
Short name T292
Test name
Test status
Simulation time 410736271 ps
CPU time 10.46 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:36 PM PDT 24
Peak memory 195344 kb
Host smart-20545e99-faa0-4672-b5c6-186488783776
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733881541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.733881541
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2475327840
Short name T517
Test name
Test status
Simulation time 65771403 ps
CPU time 0.68 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 194204 kb
Host smart-5437cee0-e266-415c-8acf-1d17ec8c99d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475327840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2475327840
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.691745771
Short name T149
Test name
Test status
Simulation time 28309372 ps
CPU time 0.73 seconds
Started Jun 22 04:24:22 PM PDT 24
Finished Jun 22 04:24:24 PM PDT 24
Peak memory 195224 kb
Host smart-3efb6e40-d1e5-48f6-81d5-9a1f330ff7d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691745771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.691745771
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.4162453306
Short name T181
Test name
Test status
Simulation time 24895802 ps
CPU time 1.02 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:24 PM PDT 24
Peak memory 196632 kb
Host smart-6a0081db-9492-4e30-b61c-6c8f1db8bc8b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162453306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.4162453306
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1441338104
Short name T332
Test name
Test status
Simulation time 81763946 ps
CPU time 1.84 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 196300 kb
Host smart-acd8d7c4-284c-4045-9275-e301a3f237b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441338104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1441338104
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.384191766
Short name T97
Test name
Test status
Simulation time 125439682 ps
CPU time 1.17 seconds
Started Jun 22 04:24:18 PM PDT 24
Finished Jun 22 04:24:20 PM PDT 24
Peak memory 196724 kb
Host smart-a14d7ac9-71e3-4686-8663-1857f126ca24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384191766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.384191766
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.4263136878
Short name T193
Test name
Test status
Simulation time 42084909 ps
CPU time 0.61 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 193936 kb
Host smart-5a5f37e1-9faf-4f9b-85ce-2cd90e7358f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263136878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.4263136878
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.371538490
Short name T187
Test name
Test status
Simulation time 605383997 ps
CPU time 4.71 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 197708 kb
Host smart-1e4535e3-56b4-44cb-a90a-942e777e404c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371538490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.371538490
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.157905043
Short name T630
Test name
Test status
Simulation time 619800264 ps
CPU time 0.8 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 195132 kb
Host smart-720b2fce-0ca2-4984-a073-041ec37dde3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157905043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.157905043
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.4133810864
Short name T159
Test name
Test status
Simulation time 151927016 ps
CPU time 0.9 seconds
Started Jun 22 04:24:20 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 195820 kb
Host smart-1bec1604-49d2-48d1-8bf8-8df753e565f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133810864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.4133810864
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.3831283540
Short name T703
Test name
Test status
Simulation time 5623994139 ps
CPU time 62.63 seconds
Started Jun 22 04:24:22 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 197928 kb
Host smart-2d31c7f4-79a9-4f73-a760-b82419526292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831283540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.3831283540
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.850900604
Short name T631
Test name
Test status
Simulation time 40786313 ps
CPU time 0.55 seconds
Started Jun 22 04:24:20 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 192468 kb
Host smart-23761a3c-c1db-4a3b-b510-dce8777a8f9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850900604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.850900604
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3137630029
Short name T376
Test name
Test status
Simulation time 78107252 ps
CPU time 0.95 seconds
Started Jun 22 04:24:19 PM PDT 24
Finished Jun 22 04:24:20 PM PDT 24
Peak memory 195780 kb
Host smart-e3b58a07-78df-41d8-95ab-06eece1df5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137630029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3137630029
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1229304052
Short name T455
Test name
Test status
Simulation time 414116942 ps
CPU time 13.42 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:40 PM PDT 24
Peak memory 195860 kb
Host smart-22ce24f2-b2c3-4d2e-a141-1af00e5e78f1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229304052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1229304052
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.306636880
Short name T128
Test name
Test status
Simulation time 60155785 ps
CPU time 1.01 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:29 PM PDT 24
Peak memory 196856 kb
Host smart-386e8419-274d-4da7-bf01-8f810d866665
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306636880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.306636880
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2443667654
Short name T51
Test name
Test status
Simulation time 21872456 ps
CPU time 0.63 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:29 PM PDT 24
Peak memory 194028 kb
Host smart-49f7e0e9-06ec-46e0-97de-dc221ff796ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443667654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2443667654
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1720745692
Short name T628
Test name
Test status
Simulation time 262893381 ps
CPU time 2.34 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 197824 kb
Host smart-4be64b07-0f91-48dc-bc05-85d1fdd5c865
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720745692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1720745692
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.591649009
Short name T16
Test name
Test status
Simulation time 90727022 ps
CPU time 1.94 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 196592 kb
Host smart-cddfbcee-164a-4a1c-8376-1a20da28d1da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591649009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
591649009
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.478709508
Short name T419
Test name
Test status
Simulation time 53311490 ps
CPU time 0.67 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:29 PM PDT 24
Peak memory 194048 kb
Host smart-dc853224-b0ee-4330-baed-b8f5170aeacf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478709508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.478709508
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.17640778
Short name T66
Test name
Test status
Simulation time 129574026 ps
CPU time 1.17 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:23 PM PDT 24
Peak memory 196640 kb
Host smart-7dd4ed72-7028-4639-850c-ada9872a2f79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17640778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup_
pulldown.17640778
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3922415854
Short name T111
Test name
Test status
Simulation time 480770401 ps
CPU time 4.81 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 197740 kb
Host smart-9af0807b-0b42-44b2-941e-1fd69222ef84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922415854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3922415854
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3056731041
Short name T685
Test name
Test status
Simulation time 307895671 ps
CPU time 1.32 seconds
Started Jun 22 04:24:20 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 195624 kb
Host smart-112e7e00-f880-4865-b879-d416c3084097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056731041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3056731041
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.196989401
Short name T477
Test name
Test status
Simulation time 172118651 ps
CPU time 1.41 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 197764 kb
Host smart-beeff4b0-2bfc-4b07-91bb-3ea746d77187
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196989401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.196989401
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.3080017634
Short name T398
Test name
Test status
Simulation time 3536258661 ps
CPU time 35.23 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:25:02 PM PDT 24
Peak memory 197944 kb
Host smart-f17f2ca0-fc48-43cc-8313-5f4f1c71879b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080017634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.3080017634
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.650239001
Short name T599
Test name
Test status
Simulation time 20812380 ps
CPU time 0.57 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 193560 kb
Host smart-64028d2d-e4b8-4df4-a81c-7252ec975838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650239001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.650239001
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1718332634
Short name T608
Test name
Test status
Simulation time 182394972 ps
CPU time 0.76 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 195548 kb
Host smart-f2593851-a98d-42dd-9b92-4a3a7bb18384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718332634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1718332634
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3095413483
Short name T50
Test name
Test status
Simulation time 4560188237 ps
CPU time 7.9 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 196716 kb
Host smart-c4faa50b-3c0e-400c-9a6e-26e99afd47bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095413483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3095413483
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2180893995
Short name T175
Test name
Test status
Simulation time 37754205 ps
CPU time 0.69 seconds
Started Jun 22 04:26:38 PM PDT 24
Finished Jun 22 04:26:40 PM PDT 24
Peak memory 194500 kb
Host smart-ec2f4f58-985d-4221-a625-50f41fe16bd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180893995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2180893995
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3452871650
Short name T101
Test name
Test status
Simulation time 39192385 ps
CPU time 0.85 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 196980 kb
Host smart-8fc2e433-a655-497f-8497-cfba3311b363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452871650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3452871650
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1260785826
Short name T709
Test name
Test status
Simulation time 157125670 ps
CPU time 1.81 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 197896 kb
Host smart-90105bc7-239c-4ba5-9b5c-1d03b92aac74
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260785826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1260785826
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2239702193
Short name T137
Test name
Test status
Simulation time 1801349691 ps
CPU time 2.46 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:35 PM PDT 24
Peak memory 196952 kb
Host smart-dd6ac320-0eba-4e86-97ea-e377aa9e105b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239702193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2239702193
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2376222284
Short name T158
Test name
Test status
Simulation time 76748059 ps
CPU time 1.23 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 195648 kb
Host smart-0ad9f638-02b4-43e5-8a2d-ceb4840cf623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376222284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2376222284
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2313500233
Short name T399
Test name
Test status
Simulation time 345737008 ps
CPU time 0.88 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:42 PM PDT 24
Peak memory 197120 kb
Host smart-7a3b967b-8e6a-46dc-a828-a5166375e7d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313500233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2313500233
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.376272707
Short name T277
Test name
Test status
Simulation time 63121129 ps
CPU time 2.61 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:25 PM PDT 24
Peak memory 197496 kb
Host smart-41dc329e-dc7f-4f3f-a1f7-7bf6c397a021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376272707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.376272707
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.759376552
Short name T448
Test name
Test status
Simulation time 381451411 ps
CPU time 1.53 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 195660 kb
Host smart-9a9c8e9b-618d-4e4e-9bd4-68ae2df09a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759376552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.759376552
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.1970599583
Short name T65
Test name
Test status
Simulation time 35370786 ps
CPU time 0.95 seconds
Started Jun 22 04:24:35 PM PDT 24
Finished Jun 22 04:24:36 PM PDT 24
Peak memory 195572 kb
Host smart-856024fd-9975-44a2-9481-6cfe597179d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970599583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.1970599583
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1350704853
Short name T683
Test name
Test status
Simulation time 25546988841 ps
CPU time 80.44 seconds
Started Jun 22 04:24:33 PM PDT 24
Finished Jun 22 04:25:55 PM PDT 24
Peak memory 197908 kb
Host smart-402051d8-6639-4c62-85a1-164cfa9a53bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350704853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1350704853
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.943163035
Short name T426
Test name
Test status
Simulation time 66846192188 ps
CPU time 520.91 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:33:11 PM PDT 24
Peak memory 198044 kb
Host smart-e57f3722-d938-4f25-a3c2-29f2c56b103b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=943163035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.943163035
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.238719350
Short name T316
Test name
Test status
Simulation time 50600805 ps
CPU time 0.79 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 196216 kb
Host smart-c7958922-74c3-45ed-97d0-d7b86bd3e9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238719350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.238719350
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2298018885
Short name T506
Test name
Test status
Simulation time 324194114 ps
CPU time 16.69 seconds
Started Jun 22 04:24:59 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 196784 kb
Host smart-f3ba8e3f-ecca-4b5d-8fe2-ffc45cac2406
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298018885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2298018885
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.317634390
Short name T486
Test name
Test status
Simulation time 19205583 ps
CPU time 0.59 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 194468 kb
Host smart-96789a1e-dcac-4618-aa2c-19c5246f62ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317634390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.317634390
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2498454202
Short name T386
Test name
Test status
Simulation time 40945233 ps
CPU time 1.23 seconds
Started Jun 22 04:24:33 PM PDT 24
Finished Jun 22 04:24:35 PM PDT 24
Peak memory 197108 kb
Host smart-4c702d8b-3b91-43da-8df2-1092c2008c6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498454202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2498454202
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2417932412
Short name T91
Test name
Test status
Simulation time 194215757 ps
CPU time 1.99 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 196236 kb
Host smart-407ab5c5-519f-43d2-b9e1-0bfc6640114e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417932412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2417932412
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2721279749
Short name T494
Test name
Test status
Simulation time 133502411 ps
CPU time 3 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 197088 kb
Host smart-658db09e-2002-4c65-b7ee-3fdf5a105676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721279749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2721279749
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3651226281
Short name T113
Test name
Test status
Simulation time 140170307 ps
CPU time 0.88 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 195692 kb
Host smart-dda28984-f39e-4b37-aeff-05c7b3d37df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651226281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3651226281
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.901661329
Short name T390
Test name
Test status
Simulation time 125366167 ps
CPU time 0.86 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 195804 kb
Host smart-60ff40ba-99d3-4991-8619-198d0c83bb93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901661329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.901661329
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.992688302
Short name T556
Test name
Test status
Simulation time 161173122 ps
CPU time 2.8 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 197740 kb
Host smart-4bd5b755-d0d8-418a-a184-589dec02f06d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992688302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ran
dom_long_reg_writes_reg_reads.992688302
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1820482911
Short name T566
Test name
Test status
Simulation time 364266155 ps
CPU time 1.31 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 196444 kb
Host smart-3ff4876f-0778-4248-adb2-ddd9c044e27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820482911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1820482911
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1112099261
Short name T344
Test name
Test status
Simulation time 79289550 ps
CPU time 0.97 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 195284 kb
Host smart-a0f59f8e-b11c-46a8-b3b1-4a80cc3bd629
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112099261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1112099261
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3652125106
Short name T6
Test name
Test status
Simulation time 18311539488 ps
CPU time 220.42 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:28:11 PM PDT 24
Peak memory 197960 kb
Host smart-10b388a3-da17-43ce-bbeb-3887798466d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652125106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3652125106
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1518307979
Short name T185
Test name
Test status
Simulation time 15520765 ps
CPU time 0.57 seconds
Started Jun 22 04:23:47 PM PDT 24
Finished Jun 22 04:23:48 PM PDT 24
Peak memory 193708 kb
Host smart-3d5670e6-e006-4c92-a270-740ef860d134
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518307979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1518307979
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1776731040
Short name T269
Test name
Test status
Simulation time 20077061 ps
CPU time 0.7 seconds
Started Jun 22 04:23:41 PM PDT 24
Finished Jun 22 04:23:43 PM PDT 24
Peak memory 192884 kb
Host smart-3c4b08ba-555a-48c8-9da3-5cf35c495a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776731040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1776731040
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1080914244
Short name T260
Test name
Test status
Simulation time 325347422 ps
CPU time 16.5 seconds
Started Jun 22 04:24:17 PM PDT 24
Finished Jun 22 04:24:35 PM PDT 24
Peak memory 196732 kb
Host smart-3a1d7554-d790-420a-9c7e-1b9e33d456fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080914244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1080914244
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.652014158
Short name T261
Test name
Test status
Simulation time 255658323 ps
CPU time 0.95 seconds
Started Jun 22 04:24:02 PM PDT 24
Finished Jun 22 04:24:03 PM PDT 24
Peak memory 196124 kb
Host smart-3788e67c-c3fa-49ba-9288-e1b076d814b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652014158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.652014158
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3155649189
Short name T347
Test name
Test status
Simulation time 317239531 ps
CPU time 1.19 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 195740 kb
Host smart-bf926ca8-0552-4248-99c2-17124b98d8d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155649189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3155649189
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1270522083
Short name T333
Test name
Test status
Simulation time 452760648 ps
CPU time 2.52 seconds
Started Jun 22 04:24:07 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 197848 kb
Host smart-6b161879-f473-4e56-94a0-7d92178ed817
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270522083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1270522083
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1070402839
Short name T244
Test name
Test status
Simulation time 145895754 ps
CPU time 2.86 seconds
Started Jun 22 04:24:13 PM PDT 24
Finished Jun 22 04:24:17 PM PDT 24
Peak memory 197844 kb
Host smart-1c3739f9-ced6-4b0f-b01c-259d324f6b17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070402839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1070402839
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2352772469
Short name T389
Test name
Test status
Simulation time 82855282 ps
CPU time 0.97 seconds
Started Jun 22 04:24:03 PM PDT 24
Finished Jun 22 04:24:05 PM PDT 24
Peak memory 195804 kb
Host smart-006e76b4-2ad4-4f6a-96ba-31f5721c3b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352772469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2352772469
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1321968983
Short name T215
Test name
Test status
Simulation time 17096520 ps
CPU time 0.69 seconds
Started Jun 22 04:23:39 PM PDT 24
Finished Jun 22 04:23:40 PM PDT 24
Peak memory 195756 kb
Host smart-5469cfe3-90eb-4a1e-a5b3-5bf4ca7e4f7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321968983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1321968983
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3696925718
Short name T232
Test name
Test status
Simulation time 581783808 ps
CPU time 3.24 seconds
Started Jun 22 04:24:03 PM PDT 24
Finished Jun 22 04:24:06 PM PDT 24
Peak memory 197764 kb
Host smart-cec4d2a5-6316-49a6-8f4a-ba53bee6b632
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696925718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3696925718
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.2104101990
Short name T356
Test name
Test status
Simulation time 41859750 ps
CPU time 1.18 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 195340 kb
Host smart-e3bae6d4-c9a9-4845-8df6-ba707904078a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104101990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2104101990
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.2364132332
Short name T670
Test name
Test status
Simulation time 50017856 ps
CPU time 1.16 seconds
Started Jun 22 04:24:01 PM PDT 24
Finished Jun 22 04:24:02 PM PDT 24
Peak memory 196216 kb
Host smart-e17e9c38-7e4b-4eb6-832d-03608eb0860d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364132332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.2364132332
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.190485060
Short name T60
Test name
Test status
Simulation time 28736170070 ps
CPU time 196.23 seconds
Started Jun 22 04:23:44 PM PDT 24
Finished Jun 22 04:27:00 PM PDT 24
Peak memory 197916 kb
Host smart-39d4adc1-9a4f-42a7-a0a8-92a43de8e773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190485060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.190485060
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2119053440
Short name T384
Test name
Test status
Simulation time 14065982 ps
CPU time 0.56 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:29 PM PDT 24
Peak memory 193596 kb
Host smart-bbd30e50-cedb-4481-a4c0-2b39afda5688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119053440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2119053440
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.234516372
Short name T653
Test name
Test status
Simulation time 47062795 ps
CPU time 0.62 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 194984 kb
Host smart-6392ca84-1aa0-414f-832e-0cc8cecb80a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234516372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.234516372
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3355397254
Short name T642
Test name
Test status
Simulation time 2439774668 ps
CPU time 16.67 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:48 PM PDT 24
Peak memory 195516 kb
Host smart-90b2794a-74b3-4a2c-8f73-e683399753e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355397254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3355397254
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3591211486
Short name T302
Test name
Test status
Simulation time 55301898 ps
CPU time 0.8 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:23 PM PDT 24
Peak memory 195800 kb
Host smart-98c65341-20ce-4b27-ac17-500646bb9276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591211486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3591211486
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.3840604715
Short name T49
Test name
Test status
Simulation time 39980394 ps
CPU time 1.12 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:29 PM PDT 24
Peak memory 195932 kb
Host smart-330aef0e-1d3b-4037-af90-92c8a26c5897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840604715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.3840604715
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3827417116
Short name T708
Test name
Test status
Simulation time 72623980 ps
CPU time 0.9 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 195640 kb
Host smart-0bbbee2a-df08-4037-9d77-82ddd208749f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827417116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3827417116
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4219338179
Short name T234
Test name
Test status
Simulation time 33662294 ps
CPU time 1.12 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:29 PM PDT 24
Peak memory 196180 kb
Host smart-32e05554-1d62-446d-a000-c7ba838b59e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219338179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4219338179
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2737546493
Short name T403
Test name
Test status
Simulation time 37130132 ps
CPU time 0.94 seconds
Started Jun 22 04:24:34 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 197120 kb
Host smart-c83cea4d-c7fe-4a90-aeaa-769a17950097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737546493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2737546493
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3212693340
Short name T276
Test name
Test status
Simulation time 39357496 ps
CPU time 1.02 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 196436 kb
Host smart-8743c28d-1c24-4987-9603-425cfec40226
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212693340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3212693340
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1314315326
Short name T362
Test name
Test status
Simulation time 256822605 ps
CPU time 4.29 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 197784 kb
Host smart-3443cf05-c50b-4c04-b107-45123ffab21e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314315326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1314315326
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.183478296
Short name T435
Test name
Test status
Simulation time 164377273 ps
CPU time 1.01 seconds
Started Jun 22 04:24:34 PM PDT 24
Finished Jun 22 04:24:36 PM PDT 24
Peak memory 195520 kb
Host smart-cd7d8419-4e46-4015-9521-2ecf521c5269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183478296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.183478296
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.2856736706
Short name T141
Test name
Test status
Simulation time 369550555 ps
CPU time 1.13 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 195292 kb
Host smart-1335af21-6621-4df3-91c9-9259e0984ba2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856736706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.2856736706
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1231553758
Short name T650
Test name
Test status
Simulation time 3894556987 ps
CPU time 54.47 seconds
Started Jun 22 04:25:01 PM PDT 24
Finished Jun 22 04:25:56 PM PDT 24
Peak memory 197888 kb
Host smart-d3e504d4-3a9b-4c36-ac8f-feeeaa008948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231553758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1231553758
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.2786383795
Short name T270
Test name
Test status
Simulation time 12516493 ps
CPU time 0.58 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 193772 kb
Host smart-8e4c0fe1-9ec9-4ba0-b06a-0dcfff71ee02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786383795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.2786383795
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1555900443
Short name T169
Test name
Test status
Simulation time 151551494 ps
CPU time 0.71 seconds
Started Jun 22 04:24:45 PM PDT 24
Finished Jun 22 04:24:46 PM PDT 24
Peak memory 193808 kb
Host smart-4ccea708-4ee4-4248-82af-4c1ab5eae3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555900443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1555900443
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.97200813
Short name T134
Test name
Test status
Simulation time 444639582 ps
CPU time 12.14 seconds
Started Jun 22 04:25:43 PM PDT 24
Finished Jun 22 04:25:56 PM PDT 24
Peak memory 196064 kb
Host smart-804f2415-0667-4af6-89ae-4f066a28f8a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97200813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stress
.97200813
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.589263721
Short name T438
Test name
Test status
Simulation time 61172915 ps
CPU time 1 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 196168 kb
Host smart-7810d3f6-26da-40c8-b3ef-452cb7ae0034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589263721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.589263721
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3287769134
Short name T174
Test name
Test status
Simulation time 487755167 ps
CPU time 1.2 seconds
Started Jun 22 04:24:28 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 196524 kb
Host smart-28e9c212-d761-4e0c-a037-85b349d78894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287769134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3287769134
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2801617996
Short name T367
Test name
Test status
Simulation time 308954889 ps
CPU time 1.31 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 196432 kb
Host smart-36935e25-f78e-47e4-b1ca-26d2c11e288a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801617996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2801617996
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2123539583
Short name T300
Test name
Test status
Simulation time 446952448 ps
CPU time 3.5 seconds
Started Jun 22 04:24:34 PM PDT 24
Finished Jun 22 04:24:38 PM PDT 24
Peak memory 196888 kb
Host smart-6d34bf49-382c-49b5-8c58-0b68057aa8f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123539583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2123539583
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2281785609
Short name T255
Test name
Test status
Simulation time 14332769 ps
CPU time 0.66 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 194040 kb
Host smart-95e4eb51-3f62-4af2-96c7-cdc33d2d3ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281785609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2281785609
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1972161280
Short name T475
Test name
Test status
Simulation time 110277895 ps
CPU time 0.88 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 195708 kb
Host smart-4e23fc7e-70df-4341-b327-8684c55a0687
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972161280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1972161280
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2535339044
Short name T469
Test name
Test status
Simulation time 771557752 ps
CPU time 3.91 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 197772 kb
Host smart-4c1eea8e-7bd2-4e31-a1ce-d07ddb9cfe0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535339044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2535339044
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3083039190
Short name T501
Test name
Test status
Simulation time 60593810 ps
CPU time 0.98 seconds
Started Jun 22 04:24:47 PM PDT 24
Finished Jun 22 04:24:48 PM PDT 24
Peak memory 196220 kb
Host smart-f9b0df1f-4a42-4730-8dee-c22431396ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083039190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3083039190
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1700597767
Short name T251
Test name
Test status
Simulation time 20300307 ps
CPU time 0.86 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 194864 kb
Host smart-52975b83-4fe0-42b0-93c8-0298e87fff62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700597767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1700597767
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1508736145
Short name T209
Test name
Test status
Simulation time 8094652253 ps
CPU time 109.19 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:26:17 PM PDT 24
Peak memory 197968 kb
Host smart-0853a4eb-7b0a-45aa-b1d2-ad2f41a98860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508736145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1508736145
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.796786821
Short name T627
Test name
Test status
Simulation time 18340175352 ps
CPU time 157.83 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:27:06 PM PDT 24
Peak memory 197764 kb
Host smart-8a4ddac3-82ce-40e9-8778-7f83ee2488f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=796786821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.796786821
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.74318070
Short name T336
Test name
Test status
Simulation time 25283291 ps
CPU time 0.56 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 193664 kb
Host smart-0d01a975-18b7-4a05-bb0a-fd369ed5cd1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74318070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.74318070
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2179741325
Short name T687
Test name
Test status
Simulation time 61852116 ps
CPU time 0.87 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 195912 kb
Host smart-715770f8-feb1-4a89-858c-abcd882521e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179741325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2179741325
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.2657672060
Short name T24
Test name
Test status
Simulation time 477492847 ps
CPU time 8.19 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:38 PM PDT 24
Peak memory 196596 kb
Host smart-2224a4f5-fb35-44c0-ae3d-1c126f66f588
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657672060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.2657672060
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.63312845
Short name T711
Test name
Test status
Simulation time 29979923 ps
CPU time 0.77 seconds
Started Jun 22 04:24:22 PM PDT 24
Finished Jun 22 04:24:25 PM PDT 24
Peak memory 196320 kb
Host smart-0a6eff13-da69-430e-9bb4-3363b0577853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63312845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.63312845
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.150876290
Short name T591
Test name
Test status
Simulation time 273505215 ps
CPU time 1.13 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:38 PM PDT 24
Peak memory 195568 kb
Host smart-737a3fb6-fbbc-4a60-9702-e420582893ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150876290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.150876290
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3301093599
Short name T278
Test name
Test status
Simulation time 53508466 ps
CPU time 2.28 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:32 PM PDT 24
Peak memory 197920 kb
Host smart-66e4f4a9-3543-4695-8898-059446ec17e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301093599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3301093599
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.4138829425
Short name T107
Test name
Test status
Simulation time 79766391 ps
CPU time 1.62 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 196656 kb
Host smart-2212b973-aa33-471c-bf69-75a55c8f8646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138829425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.4138829425
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2720015685
Short name T13
Test name
Test status
Simulation time 144261360 ps
CPU time 1.25 seconds
Started Jun 22 04:24:26 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 196824 kb
Host smart-46a68dcf-6ec7-4915-b1e9-55988c7b61d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720015685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2720015685
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1561245024
Short name T657
Test name
Test status
Simulation time 19334854 ps
CPU time 0.71 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 194020 kb
Host smart-181fd03a-d506-4046-93a7-9fb486f800d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561245024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1561245024
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.919797654
Short name T457
Test name
Test status
Simulation time 147439902 ps
CPU time 4.35 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:30 PM PDT 24
Peak memory 197768 kb
Host smart-e64118e9-7a39-43e2-81be-3fe85079e8d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919797654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.919797654
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1943518478
Short name T307
Test name
Test status
Simulation time 74005101 ps
CPU time 1.25 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 196644 kb
Host smart-e8bc4b00-b4cc-4f35-839c-e859b82fc388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943518478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1943518478
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3229334539
Short name T340
Test name
Test status
Simulation time 59472467 ps
CPU time 1.08 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 195452 kb
Host smart-fe2bec61-40e1-4a5b-8619-43ce72e1ed02
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229334539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3229334539
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.604199831
Short name T502
Test name
Test status
Simulation time 13277998081 ps
CPU time 170.36 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:27:16 PM PDT 24
Peak memory 198292 kb
Host smart-a13a4336-18c6-4bc0-980a-2ed6eaa45072
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604199831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.604199831
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.1121197592
Short name T408
Test name
Test status
Simulation time 161928161747 ps
CPU time 1580.99 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:50:54 PM PDT 24
Peak memory 197960 kb
Host smart-823e70e3-b0e7-4245-9d7d-44bcd5b955a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1121197592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.1121197592
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.4008736081
Short name T690
Test name
Test status
Simulation time 30328570 ps
CPU time 0.64 seconds
Started Jun 22 04:24:32 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 193580 kb
Host smart-c3d9a037-41f2-4cdc-9b1a-d7b600029cc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008736081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.4008736081
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2734797862
Short name T520
Test name
Test status
Simulation time 97331869 ps
CPU time 0.72 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 193820 kb
Host smart-e08430f1-82c2-4b22-bd69-0919b147a161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734797862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2734797862
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3892034734
Short name T311
Test name
Test status
Simulation time 2486977675 ps
CPU time 17.01 seconds
Started Jun 22 04:24:34 PM PDT 24
Finished Jun 22 04:24:52 PM PDT 24
Peak memory 196724 kb
Host smart-b736c2c6-b223-457a-9590-f71519f79b3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892034734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3892034734
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3134247084
Short name T289
Test name
Test status
Simulation time 94163613 ps
CPU time 0.82 seconds
Started Jun 22 04:24:38 PM PDT 24
Finished Jun 22 04:24:39 PM PDT 24
Peak memory 195920 kb
Host smart-30b01d0f-8488-4f94-a3a1-69d6969a30db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134247084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3134247084
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1310566278
Short name T258
Test name
Test status
Simulation time 82204079 ps
CPU time 1.17 seconds
Started Jun 22 04:25:02 PM PDT 24
Finished Jun 22 04:25:03 PM PDT 24
Peak memory 195684 kb
Host smart-c246226c-1cc3-4e87-82bb-f5f8d4a37f1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310566278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1310566278
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2318292599
Short name T587
Test name
Test status
Simulation time 27302038 ps
CPU time 1.14 seconds
Started Jun 22 04:24:56 PM PDT 24
Finished Jun 22 04:24:58 PM PDT 24
Peak memory 196280 kb
Host smart-5966d210-00be-489e-ab03-0e68149952bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318292599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2318292599
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.786122851
Short name T11
Test name
Test status
Simulation time 139300519 ps
CPU time 2.81 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:42 PM PDT 24
Peak memory 197036 kb
Host smart-6e498732-acdf-4b5a-93ac-c6006bdafb1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786122851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.
786122851
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2103681750
Short name T654
Test name
Test status
Simulation time 119734975 ps
CPU time 1.14 seconds
Started Jun 22 04:24:37 PM PDT 24
Finished Jun 22 04:24:38 PM PDT 24
Peak memory 196808 kb
Host smart-a13f3c0c-59d8-4dd9-adb3-863f6570cec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103681750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2103681750
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1260057459
Short name T511
Test name
Test status
Simulation time 92265565 ps
CPU time 0.79 seconds
Started Jun 22 04:24:43 PM PDT 24
Finished Jun 22 04:24:44 PM PDT 24
Peak memory 195048 kb
Host smart-ea836c36-aa7d-4ead-a77b-fa5044e3aaf1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260057459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1260057459
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1488138080
Short name T227
Test name
Test status
Simulation time 420043883 ps
CPU time 5.31 seconds
Started Jun 22 04:24:40 PM PDT 24
Finished Jun 22 04:24:46 PM PDT 24
Peak memory 197764 kb
Host smart-013620e7-d27f-41e2-8d90-ad1bbf4c5e3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488138080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1488138080
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3498910013
Short name T267
Test name
Test status
Simulation time 163696551 ps
CPU time 0.97 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:28 PM PDT 24
Peak memory 196908 kb
Host smart-370bcd9e-f3e4-4502-b26a-e13c66ea0b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498910013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3498910013
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3810148766
Short name T179
Test name
Test status
Simulation time 66883972 ps
CPU time 1.14 seconds
Started Jun 22 04:24:52 PM PDT 24
Finished Jun 22 04:24:58 PM PDT 24
Peak memory 195576 kb
Host smart-ed13b0fa-7cb3-4d99-853c-5cf11a79950f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810148766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3810148766
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1586891952
Short name T646
Test name
Test status
Simulation time 4936467487 ps
CPU time 70.78 seconds
Started Jun 22 04:24:34 PM PDT 24
Finished Jun 22 04:25:45 PM PDT 24
Peak memory 197928 kb
Host smart-ef6f9de6-7521-4b19-a7d8-f0091d532d64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586891952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1586891952
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3833868693
Short name T689
Test name
Test status
Simulation time 13371229 ps
CPU time 0.57 seconds
Started Jun 22 04:24:33 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 193680 kb
Host smart-ce94be5f-4b56-4f7c-8933-b4aee793898d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833868693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3833868693
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.4000229851
Short name T577
Test name
Test status
Simulation time 29358469 ps
CPU time 0.88 seconds
Started Jun 22 04:24:35 PM PDT 24
Finished Jun 22 04:24:36 PM PDT 24
Peak memory 195824 kb
Host smart-5e0e75bc-e3d0-4010-a7ae-dbde3a83e713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000229851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.4000229851
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1991137487
Short name T707
Test name
Test status
Simulation time 1089547805 ps
CPU time 15.37 seconds
Started Jun 22 04:24:37 PM PDT 24
Finished Jun 22 04:24:53 PM PDT 24
Peak memory 195424 kb
Host smart-c7805cb7-e751-4523-a66b-e20ef96d6dbc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991137487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1991137487
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3946202038
Short name T341
Test name
Test status
Simulation time 293811271 ps
CPU time 0.93 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:37 PM PDT 24
Peak memory 197156 kb
Host smart-233763dd-fa74-4d00-a9e2-328114718e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946202038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3946202038
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2290992135
Short name T253
Test name
Test status
Simulation time 206839851 ps
CPU time 1.37 seconds
Started Jun 22 04:24:33 PM PDT 24
Finished Jun 22 04:24:35 PM PDT 24
Peak memory 195636 kb
Host smart-ad231ddb-36b8-4a25-a01c-23ee6e91eccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290992135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2290992135
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2572579687
Short name T407
Test name
Test status
Simulation time 75034145 ps
CPU time 1.71 seconds
Started Jun 22 04:25:02 PM PDT 24
Finished Jun 22 04:25:04 PM PDT 24
Peak memory 196788 kb
Host smart-a0cde897-6a2e-4213-9bee-05aa318ab130
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572579687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2572579687
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1250386085
Short name T17
Test name
Test status
Simulation time 689191166 ps
CPU time 3.25 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:40 PM PDT 24
Peak memory 196292 kb
Host smart-d353c7c1-e5c5-4b93-a828-b04170c5b575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250386085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1250386085
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3875150765
Short name T598
Test name
Test status
Simulation time 32663270 ps
CPU time 0.8 seconds
Started Jun 22 04:24:35 PM PDT 24
Finished Jun 22 04:24:37 PM PDT 24
Peak memory 195800 kb
Host smart-92bf97b8-1f6e-44dc-83e0-5515c977a175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875150765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3875150765
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.1662096117
Short name T713
Test name
Test status
Simulation time 140199147 ps
CPU time 1.32 seconds
Started Jun 22 04:24:32 PM PDT 24
Finished Jun 22 04:24:35 PM PDT 24
Peak memory 197836 kb
Host smart-606a64f5-a360-478f-b88c-d352d8b1fa97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662096117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.1662096117
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.872308919
Short name T536
Test name
Test status
Simulation time 231075446 ps
CPU time 5.83 seconds
Started Jun 22 04:24:32 PM PDT 24
Finished Jun 22 04:24:39 PM PDT 24
Peak memory 197780 kb
Host smart-0c131d70-7a75-4229-b83c-00935ed26202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872308919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.872308919
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.677226439
Short name T301
Test name
Test status
Simulation time 212238271 ps
CPU time 1.02 seconds
Started Jun 22 04:24:35 PM PDT 24
Finished Jun 22 04:24:36 PM PDT 24
Peak memory 195524 kb
Host smart-ba0194d7-d47b-4df4-8082-0807a46c3896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677226439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.677226439
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3661558687
Short name T138
Test name
Test status
Simulation time 183783984 ps
CPU time 0.9 seconds
Started Jun 22 04:24:30 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 196144 kb
Host smart-d1b02473-f281-42e2-a1d6-923b5228fd2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661558687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3661558687
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1968901004
Short name T392
Test name
Test status
Simulation time 8352185229 ps
CPU time 111.57 seconds
Started Jun 22 04:24:35 PM PDT 24
Finished Jun 22 04:26:27 PM PDT 24
Peak memory 197908 kb
Host smart-bebd6cb2-baf0-433f-8575-69daee817d18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968901004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1968901004
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1744831247
Short name T48
Test name
Test status
Simulation time 11802711 ps
CPU time 0.57 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 194292 kb
Host smart-df7b162e-c3cb-4193-a3d7-7b5ec3976d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744831247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1744831247
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2502306072
Short name T287
Test name
Test status
Simulation time 23327886 ps
CPU time 0.7 seconds
Started Jun 22 04:24:49 PM PDT 24
Finished Jun 22 04:24:50 PM PDT 24
Peak memory 194520 kb
Host smart-af55ea4b-1b22-4c28-b96d-6910fa9b398c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502306072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2502306072
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1947249550
Short name T546
Test name
Test status
Simulation time 554922610 ps
CPU time 18.66 seconds
Started Jun 22 04:24:53 PM PDT 24
Finished Jun 22 04:25:12 PM PDT 24
Peak memory 195324 kb
Host smart-028bfcd9-81df-435e-8159-1bbcdbd4b121
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947249550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1947249550
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1223949392
Short name T648
Test name
Test status
Simulation time 50438932 ps
CPU time 0.82 seconds
Started Jun 22 04:24:34 PM PDT 24
Finished Jun 22 04:24:35 PM PDT 24
Peak memory 196384 kb
Host smart-7999d57a-e3dc-43c9-a889-de88d99759d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223949392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1223949392
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2979875605
Short name T44
Test name
Test status
Simulation time 61778662 ps
CPU time 1.22 seconds
Started Jun 22 04:24:53 PM PDT 24
Finished Jun 22 04:24:54 PM PDT 24
Peak memory 195832 kb
Host smart-fc74135a-d42f-4dd0-bd18-309a36209207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979875605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2979875605
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1244478747
Short name T168
Test name
Test status
Simulation time 167374695 ps
CPU time 3.22 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:40 PM PDT 24
Peak memory 197824 kb
Host smart-fee83648-bb81-4440-ba31-727db66eb00d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244478747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1244478747
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1388166082
Short name T543
Test name
Test status
Simulation time 36519770 ps
CPU time 1.07 seconds
Started Jun 22 04:24:33 PM PDT 24
Finished Jun 22 04:24:35 PM PDT 24
Peak memory 195412 kb
Host smart-6ed24ae8-d24d-4e00-ad64-5f74ddf55467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388166082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1388166082
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2219526906
Short name T507
Test name
Test status
Simulation time 74655439 ps
CPU time 0.83 seconds
Started Jun 22 04:24:47 PM PDT 24
Finished Jun 22 04:24:48 PM PDT 24
Peak memory 196344 kb
Host smart-86b24546-7924-40b3-a47d-4c831c4a48ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219526906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2219526906
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2853343050
Short name T122
Test name
Test status
Simulation time 28573793 ps
CPU time 1.1 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:38 PM PDT 24
Peak memory 196352 kb
Host smart-123981c6-fef0-4c99-b463-27d1bb382124
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853343050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2853343050
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1819358919
Short name T451
Test name
Test status
Simulation time 48620261 ps
CPU time 2.41 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:39 PM PDT 24
Peak memory 197712 kb
Host smart-4424cf4f-50bd-440e-839f-0627e2fa4f75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819358919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1819358919
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.2509203067
Short name T537
Test name
Test status
Simulation time 34336767 ps
CPU time 0.81 seconds
Started Jun 22 04:24:41 PM PDT 24
Finished Jun 22 04:24:42 PM PDT 24
Peak memory 194924 kb
Host smart-e91d6408-019d-4d75-9263-60eb3edd5a56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509203067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.2509203067
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1402598811
Short name T378
Test name
Test status
Simulation time 29448292 ps
CPU time 0.89 seconds
Started Jun 22 04:24:40 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 195508 kb
Host smart-0ad6d4bb-5ee0-4afb-905f-d309fbec0a8b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402598811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1402598811
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2472793046
Short name T611
Test name
Test status
Simulation time 6701080287 ps
CPU time 182.01 seconds
Started Jun 22 04:24:55 PM PDT 24
Finished Jun 22 04:27:58 PM PDT 24
Peak memory 198000 kb
Host smart-e1680a3d-d1ea-4a6b-bef1-4ac63d9672b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472793046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2472793046
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.467679169
Short name T241
Test name
Test status
Simulation time 95308221 ps
CPU time 0.55 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:40 PM PDT 24
Peak memory 193804 kb
Host smart-0e40953a-0cb4-4a89-a99d-bdfeb2974dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467679169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.467679169
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2625353247
Short name T290
Test name
Test status
Simulation time 24038586 ps
CPU time 0.8 seconds
Started Jun 22 04:24:37 PM PDT 24
Finished Jun 22 04:24:39 PM PDT 24
Peak memory 195852 kb
Host smart-e6e0522e-6e6b-4793-84c3-1c05c64894ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625353247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2625353247
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.743407151
Short name T271
Test name
Test status
Simulation time 559427117 ps
CPU time 19.5 seconds
Started Jun 22 04:24:47 PM PDT 24
Finished Jun 22 04:25:08 PM PDT 24
Peak memory 195320 kb
Host smart-2020a4db-f1d0-4c37-8258-a07a17709771
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743407151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.743407151
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.912929261
Short name T417
Test name
Test status
Simulation time 50629852 ps
CPU time 0.66 seconds
Started Jun 22 04:25:01 PM PDT 24
Finished Jun 22 04:25:02 PM PDT 24
Peak memory 194268 kb
Host smart-40a69ffd-a125-49af-bebc-a269c134f025
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912929261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.912929261
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.3701484125
Short name T366
Test name
Test status
Simulation time 47551951 ps
CPU time 1.25 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 197040 kb
Host smart-d5a0862a-7087-4aed-b445-b6f82f063d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701484125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.3701484125
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.110590046
Short name T674
Test name
Test status
Simulation time 71976835 ps
CPU time 2.91 seconds
Started Jun 22 04:24:51 PM PDT 24
Finished Jun 22 04:24:55 PM PDT 24
Peak memory 196380 kb
Host smart-ba27b7ae-8753-4c3f-a0a6-3ee577bf0f88
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110590046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.110590046
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2651258311
Short name T121
Test name
Test status
Simulation time 164317118 ps
CPU time 3.47 seconds
Started Jun 22 04:25:02 PM PDT 24
Finished Jun 22 04:25:06 PM PDT 24
Peak memory 196956 kb
Host smart-1e33cf07-730c-4ad1-8002-9630e2386853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651258311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2651258311
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2391759034
Short name T247
Test name
Test status
Simulation time 31729185 ps
CPU time 0.9 seconds
Started Jun 22 04:24:31 PM PDT 24
Finished Jun 22 04:24:34 PM PDT 24
Peak memory 196300 kb
Host smart-44b4bc71-019e-43a6-9a0f-1f70dc44c9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391759034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2391759034
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3576576979
Short name T495
Test name
Test status
Simulation time 54623912 ps
CPU time 1.28 seconds
Started Jun 22 04:24:48 PM PDT 24
Finished Jun 22 04:24:50 PM PDT 24
Peak memory 196728 kb
Host smart-57bd6492-fc38-4221-bcd1-379d5963b796
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576576979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3576576979
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1151928528
Short name T5
Test name
Test status
Simulation time 494711124 ps
CPU time 1.96 seconds
Started Jun 22 04:24:38 PM PDT 24
Finished Jun 22 04:24:40 PM PDT 24
Peak memory 197476 kb
Host smart-dccdbf18-9cf2-418c-9d43-3d4db02649ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151928528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1151928528
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2561404327
Short name T200
Test name
Test status
Simulation time 141405924 ps
CPU time 1.17 seconds
Started Jun 22 04:24:34 PM PDT 24
Finished Jun 22 04:24:36 PM PDT 24
Peak memory 196388 kb
Host smart-db49a0b6-c03b-4299-a664-4b6ce6ff7be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561404327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2561404327
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2536400378
Short name T334
Test name
Test status
Simulation time 58874809 ps
CPU time 1.16 seconds
Started Jun 22 04:24:48 PM PDT 24
Finished Jun 22 04:24:50 PM PDT 24
Peak memory 196680 kb
Host smart-d2e4823e-d331-4997-99a2-d6573754439b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536400378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2536400378
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.397467653
Short name T10
Test name
Test status
Simulation time 8939697279 ps
CPU time 106.79 seconds
Started Jun 22 04:25:08 PM PDT 24
Finished Jun 22 04:26:55 PM PDT 24
Peak memory 197916 kb
Host smart-f867f5b1-b245-41fe-a7af-7e98e7aedc11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397467653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.397467653
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.882714267
Short name T27
Test name
Test status
Simulation time 73788782052 ps
CPU time 415.85 seconds
Started Jun 22 04:24:40 PM PDT 24
Finished Jun 22 04:31:36 PM PDT 24
Peak memory 198020 kb
Host smart-b260511e-fcc6-49fe-a113-80d61ec4ab40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=882714267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.882714267
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2412247301
Short name T327
Test name
Test status
Simulation time 16104617 ps
CPU time 0.56 seconds
Started Jun 22 04:24:57 PM PDT 24
Finished Jun 22 04:24:58 PM PDT 24
Peak memory 194496 kb
Host smart-f97a6e40-7323-49cd-8cda-5bab6166c9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412247301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2412247301
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1659173088
Short name T157
Test name
Test status
Simulation time 50920517 ps
CPU time 0.93 seconds
Started Jun 22 04:24:42 PM PDT 24
Finished Jun 22 04:24:44 PM PDT 24
Peak memory 196320 kb
Host smart-7f5ebfee-073b-4dcb-af95-5aca527bbe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659173088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1659173088
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3800619764
Short name T659
Test name
Test status
Simulation time 547243523 ps
CPU time 7.5 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:48 PM PDT 24
Peak memory 196612 kb
Host smart-63eaaa89-edf5-48a6-af23-665260755f34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800619764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3800619764
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.223987278
Short name T321
Test name
Test status
Simulation time 25288881 ps
CPU time 0.71 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 194440 kb
Host smart-f80f47a6-45db-42ea-8b45-1486de8917dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223987278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.223987278
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3954760946
Short name T545
Test name
Test status
Simulation time 110662480 ps
CPU time 1.16 seconds
Started Jun 22 04:24:59 PM PDT 24
Finished Jun 22 04:25:01 PM PDT 24
Peak memory 196508 kb
Host smart-645eef8e-2e90-4271-95d5-d711650466d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954760946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3954760946
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.2874853884
Short name T461
Test name
Test status
Simulation time 52907780 ps
CPU time 2.24 seconds
Started Jun 22 04:24:40 PM PDT 24
Finished Jun 22 04:24:43 PM PDT 24
Peak memory 196244 kb
Host smart-0422160b-2b68-45d8-8035-f3bada76b4a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874853884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.2874853884
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3659229378
Short name T99
Test name
Test status
Simulation time 127544814 ps
CPU time 1.18 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 195860 kb
Host smart-221320a4-a09e-491a-bbc2-41653cae4d19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659229378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3659229378
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2888386043
Short name T538
Test name
Test status
Simulation time 49988037 ps
CPU time 1.11 seconds
Started Jun 22 04:24:52 PM PDT 24
Finished Jun 22 04:24:54 PM PDT 24
Peak memory 196328 kb
Host smart-cb459579-7b3f-4aab-bf7e-611538e39e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888386043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2888386043
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1375918537
Short name T563
Test name
Test status
Simulation time 58244462 ps
CPU time 1.16 seconds
Started Jun 22 04:24:43 PM PDT 24
Finished Jun 22 04:24:44 PM PDT 24
Peak memory 197892 kb
Host smart-79ca477a-32b8-4dc8-a641-b8f88c69d0b8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375918537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1375918537
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.4281117707
Short name T459
Test name
Test status
Simulation time 121584207 ps
CPU time 2.19 seconds
Started Jun 22 04:24:38 PM PDT 24
Finished Jun 22 04:24:40 PM PDT 24
Peak memory 197760 kb
Host smart-4fe99609-e1fe-4074-a256-7854275d2f1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281117707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.4281117707
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.990088725
Short name T694
Test name
Test status
Simulation time 566918281 ps
CPU time 1.01 seconds
Started Jun 22 04:24:58 PM PDT 24
Finished Jun 22 04:24:59 PM PDT 24
Peak memory 195176 kb
Host smart-adc2290a-fb3f-4794-b0ed-0fdc23efd2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990088725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.990088725
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2698338848
Short name T474
Test name
Test status
Simulation time 40427625 ps
CPU time 1.14 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:40 PM PDT 24
Peak memory 195452 kb
Host smart-54873c59-0b11-4bb8-a26b-65902b9b9271
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698338848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2698338848
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2948955414
Short name T294
Test name
Test status
Simulation time 14019966145 ps
CPU time 56.96 seconds
Started Jun 22 04:25:07 PM PDT 24
Finished Jun 22 04:26:05 PM PDT 24
Peak memory 197912 kb
Host smart-3cbe54de-f658-4640-b092-ef6225e8cdbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948955414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2948955414
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.774078692
Short name T594
Test name
Test status
Simulation time 19812330 ps
CPU time 0.55 seconds
Started Jun 22 04:24:58 PM PDT 24
Finished Jun 22 04:24:58 PM PDT 24
Peak memory 193600 kb
Host smart-ce3d6c8e-4fd6-464c-b4f4-4df883a1c008
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774078692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.774078692
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1082962831
Short name T684
Test name
Test status
Simulation time 42487795 ps
CPU time 0.63 seconds
Started Jun 22 04:24:41 PM PDT 24
Finished Jun 22 04:24:42 PM PDT 24
Peak memory 193828 kb
Host smart-deba3ea8-f45d-46ad-bd4b-566f1b4aeaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082962831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1082962831
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.3844270253
Short name T688
Test name
Test status
Simulation time 246242459 ps
CPU time 13.25 seconds
Started Jun 22 04:24:36 PM PDT 24
Finished Jun 22 04:24:50 PM PDT 24
Peak memory 197800 kb
Host smart-48487785-642b-4ce4-b56d-e4499d08b1e9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844270253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.3844270253
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3780111943
Short name T322
Test name
Test status
Simulation time 145742460 ps
CPU time 0.99 seconds
Started Jun 22 04:25:12 PM PDT 24
Finished Jun 22 04:25:13 PM PDT 24
Peak memory 196968 kb
Host smart-27b30068-37bd-4c5c-be39-100a36ecd95c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780111943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3780111943
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3930179446
Short name T487
Test name
Test status
Simulation time 121376887 ps
CPU time 1.16 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 195744 kb
Host smart-2ea11e77-3729-477b-8b9e-ef8a27646456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930179446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3930179446
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3740571897
Short name T679
Test name
Test status
Simulation time 186898819 ps
CPU time 1.93 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 197928 kb
Host smart-8b44e17d-57c9-49cc-8137-ead28ed0b72d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740571897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3740571897
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2880060939
Short name T45
Test name
Test status
Simulation time 315108101 ps
CPU time 2.55 seconds
Started Jun 22 04:25:06 PM PDT 24
Finished Jun 22 04:25:09 PM PDT 24
Peak memory 195648 kb
Host smart-c4234bc7-36b8-4743-a871-e6e0d61b1fbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880060939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2880060939
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2716243348
Short name T349
Test name
Test status
Simulation time 39766798 ps
CPU time 0.93 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 196400 kb
Host smart-f318b87f-180e-484d-a2cf-137ddcd75040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716243348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2716243348
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1830960545
Short name T151
Test name
Test status
Simulation time 52141659 ps
CPU time 1.39 seconds
Started Jun 22 04:25:03 PM PDT 24
Finished Jun 22 04:25:05 PM PDT 24
Peak memory 196924 kb
Host smart-64a98fa4-329d-4759-9662-cd0e33b3c40b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830960545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1830960545
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3548324431
Short name T616
Test name
Test status
Simulation time 127486121 ps
CPU time 2.81 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:48 PM PDT 24
Peak memory 197736 kb
Host smart-ec87a25b-b375-4dee-a75a-05e011f44b2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548324431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3548324431
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3931550546
Short name T432
Test name
Test status
Simulation time 86104117 ps
CPU time 1.39 seconds
Started Jun 22 04:25:09 PM PDT 24
Finished Jun 22 04:25:11 PM PDT 24
Peak memory 197816 kb
Host smart-06d5de98-5a93-45dc-b17f-b96256e825fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931550546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3931550546
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2819687595
Short name T590
Test name
Test status
Simulation time 37694215 ps
CPU time 0.95 seconds
Started Jun 22 04:24:38 PM PDT 24
Finished Jun 22 04:24:39 PM PDT 24
Peak memory 195440 kb
Host smart-ec8b510a-f8c7-49de-ac94-d4d78ad1919a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819687595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2819687595
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2016443083
Short name T454
Test name
Test status
Simulation time 1496388002 ps
CPU time 40.91 seconds
Started Jun 22 04:24:57 PM PDT 24
Finished Jun 22 04:25:38 PM PDT 24
Peak memory 197840 kb
Host smart-3d76fdec-3a76-4d10-aa99-dee493257daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016443083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2016443083
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.452247672
Short name T53
Test name
Test status
Simulation time 17521017879 ps
CPU time 390.52 seconds
Started Jun 22 04:24:48 PM PDT 24
Finished Jun 22 04:31:20 PM PDT 24
Peak memory 198064 kb
Host smart-ca889914-1f2e-4e65-ac45-5d34b6aca314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=452247672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.452247672
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.1425432419
Short name T582
Test name
Test status
Simulation time 14657888 ps
CPU time 0.6 seconds
Started Jun 22 04:25:05 PM PDT 24
Finished Jun 22 04:25:06 PM PDT 24
Peak memory 194284 kb
Host smart-d3553993-4003-4e39-b635-51aa01444721
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425432419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.1425432419
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1085590158
Short name T314
Test name
Test status
Simulation time 34190762 ps
CPU time 0.77 seconds
Started Jun 22 04:24:47 PM PDT 24
Finished Jun 22 04:24:49 PM PDT 24
Peak memory 195072 kb
Host smart-9e322c80-eef0-46d4-99d6-6e77da495495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085590158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1085590158
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.2731419531
Short name T651
Test name
Test status
Simulation time 1017311737 ps
CPU time 26.77 seconds
Started Jun 22 04:24:40 PM PDT 24
Finished Jun 22 04:25:07 PM PDT 24
Peak memory 196716 kb
Host smart-98e88a1f-81d2-4cff-a461-1e36468b8bfd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731419531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.2731419531
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2168138503
Short name T489
Test name
Test status
Simulation time 119309757 ps
CPU time 0.7 seconds
Started Jun 22 04:25:09 PM PDT 24
Finished Jun 22 04:25:10 PM PDT 24
Peak memory 195016 kb
Host smart-86eba7ff-869a-4205-a506-a1a7addb3811
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168138503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2168138503
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.3739054928
Short name T351
Test name
Test status
Simulation time 49362010 ps
CPU time 1.27 seconds
Started Jun 22 04:24:40 PM PDT 24
Finished Jun 22 04:24:42 PM PDT 24
Peak memory 196508 kb
Host smart-b944b9d8-e30b-46e5-a108-a3eee3bd8df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739054928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.3739054928
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3512246389
Short name T328
Test name
Test status
Simulation time 142659589 ps
CPU time 2.75 seconds
Started Jun 22 04:25:04 PM PDT 24
Finished Jun 22 04:25:08 PM PDT 24
Peak memory 196304 kb
Host smart-f1a0a243-84a6-4f11-a9fb-00d1b2ab41e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512246389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3512246389
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.2226984393
Short name T352
Test name
Test status
Simulation time 215710801 ps
CPU time 2.46 seconds
Started Jun 22 04:24:39 PM PDT 24
Finished Jun 22 04:24:41 PM PDT 24
Peak memory 196984 kb
Host smart-ca1505cf-a09b-4254-b976-fc6ceb64dceb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226984393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.2226984393
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2481850671
Short name T414
Test name
Test status
Simulation time 69222805 ps
CPU time 1.19 seconds
Started Jun 22 04:24:41 PM PDT 24
Finished Jun 22 04:24:43 PM PDT 24
Peak memory 196808 kb
Host smart-e69985c9-2aa0-4483-be4f-1bd684f1bd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481850671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2481850671
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2378079051
Short name T207
Test name
Test status
Simulation time 110927025 ps
CPU time 1.18 seconds
Started Jun 22 04:24:59 PM PDT 24
Finished Jun 22 04:25:01 PM PDT 24
Peak memory 196764 kb
Host smart-db964bec-a777-45cf-89fa-335335340902
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378079051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2378079051
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2124318131
Short name T318
Test name
Test status
Simulation time 440802076 ps
CPU time 1.67 seconds
Started Jun 22 04:24:40 PM PDT 24
Finished Jun 22 04:24:42 PM PDT 24
Peak memory 197664 kb
Host smart-8eaaaa7c-7e21-41eb-8560-f67ee46f70c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124318131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2124318131
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3320320428
Short name T14
Test name
Test status
Simulation time 141064288 ps
CPU time 0.98 seconds
Started Jun 22 04:24:51 PM PDT 24
Finished Jun 22 04:24:52 PM PDT 24
Peak memory 196732 kb
Host smart-a7282afb-35d1-451c-8e6d-35803728c058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320320428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3320320428
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4087765585
Short name T354
Test name
Test status
Simulation time 107770121 ps
CPU time 0.85 seconds
Started Jun 22 04:24:38 PM PDT 24
Finished Jun 22 04:24:39 PM PDT 24
Peak memory 195116 kb
Host smart-50d2fd78-9b95-4a2a-9660-268edc86e767
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087765585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4087765585
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2842926111
Short name T667
Test name
Test status
Simulation time 45549732498 ps
CPU time 247.48 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:29:25 PM PDT 24
Peak memory 197940 kb
Host smart-9da7c84a-b1d8-42de-a315-3e106a235242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842926111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2842926111
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1455452870
Short name T47
Test name
Test status
Simulation time 13491387 ps
CPU time 0.61 seconds
Started Jun 22 04:24:07 PM PDT 24
Finished Jun 22 04:24:09 PM PDT 24
Peak memory 193760 kb
Host smart-f0bc5424-9d11-434b-9362-4baf7a4cedad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455452870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1455452870
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3240058406
Short name T519
Test name
Test status
Simulation time 21482343 ps
CPU time 0.66 seconds
Started Jun 22 04:24:27 PM PDT 24
Finished Jun 22 04:24:31 PM PDT 24
Peak memory 193856 kb
Host smart-e427390b-ae79-4772-9f60-ca1c149f7945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240058406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3240058406
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.354118165
Short name T152
Test name
Test status
Simulation time 10602058094 ps
CPU time 18.36 seconds
Started Jun 22 04:24:06 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 196604 kb
Host smart-7a6eb6d9-b536-461a-909c-8c96e7f45e7a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354118165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.354118165
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.424257584
Short name T644
Test name
Test status
Simulation time 135152421 ps
CPU time 0.92 seconds
Started Jun 22 04:23:43 PM PDT 24
Finished Jun 22 04:23:44 PM PDT 24
Peak memory 195316 kb
Host smart-add6a22f-c23a-44de-961e-694f21788dba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424257584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.424257584
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3914971106
Short name T445
Test name
Test status
Simulation time 143655606 ps
CPU time 0.94 seconds
Started Jun 22 04:24:03 PM PDT 24
Finished Jun 22 04:24:05 PM PDT 24
Peak memory 196632 kb
Host smart-08369abe-1c28-492a-9943-cf541f864a86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914971106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3914971106
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3864319038
Short name T323
Test name
Test status
Simulation time 116508232 ps
CPU time 3.66 seconds
Started Jun 22 04:24:06 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 196648 kb
Host smart-87ae1fce-6943-41b0-be3c-ea800d3122e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864319038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3864319038
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3327727381
Short name T139
Test name
Test status
Simulation time 176968320 ps
CPU time 2.49 seconds
Started Jun 22 04:23:41 PM PDT 24
Finished Jun 22 04:23:49 PM PDT 24
Peak memory 196852 kb
Host smart-71725cc3-d024-48de-817b-dd77e486f5a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327727381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3327727381
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1135534477
Short name T98
Test name
Test status
Simulation time 395911987 ps
CPU time 1.14 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 197900 kb
Host smart-0f2a1825-4262-4f20-b3c5-d1e3e2a13c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135534477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1135534477
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1056533760
Short name T462
Test name
Test status
Simulation time 59797619 ps
CPU time 1.25 seconds
Started Jun 22 04:23:40 PM PDT 24
Finished Jun 22 04:23:41 PM PDT 24
Peak memory 196916 kb
Host smart-e611afa1-026d-4fe3-9f5c-dadde9674dfd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056533760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1056533760
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.689591419
Short name T496
Test name
Test status
Simulation time 85320495 ps
CPU time 1.33 seconds
Started Jun 22 04:24:58 PM PDT 24
Finished Jun 22 04:25:00 PM PDT 24
Peak memory 197736 kb
Host smart-3e0f34f4-96dd-478a-8fdb-6c7fff81f38d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689591419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand
om_long_reg_writes_reg_reads.689591419
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1025568807
Short name T33
Test name
Test status
Simulation time 154641509 ps
CPU time 0.99 seconds
Started Jun 22 04:23:49 PM PDT 24
Finished Jun 22 04:23:50 PM PDT 24
Peak memory 214512 kb
Host smart-876ff725-87af-4515-9a6d-d410248b9f83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025568807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1025568807
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1925038152
Short name T431
Test name
Test status
Simulation time 179288898 ps
CPU time 1.21 seconds
Started Jun 22 04:23:52 PM PDT 24
Finished Jun 22 04:23:54 PM PDT 24
Peak memory 196620 kb
Host smart-0e630473-ea7c-4fb1-add8-da7159ef9295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925038152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1925038152
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3006714473
Short name T622
Test name
Test status
Simulation time 365838282 ps
CPU time 1.4 seconds
Started Jun 22 04:23:46 PM PDT 24
Finished Jun 22 04:23:47 PM PDT 24
Peak memory 196228 kb
Host smart-cfda4aa2-c4eb-41b8-980d-dcc914e3ed6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006714473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3006714473
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.1634792457
Short name T9
Test name
Test status
Simulation time 11383012993 ps
CPU time 125.57 seconds
Started Jun 22 04:23:50 PM PDT 24
Finished Jun 22 04:25:56 PM PDT 24
Peak memory 197992 kb
Host smart-f8cc5d84-ac31-49b6-a9ad-66e0b06f12c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634792457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.1634792457
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2386753761
Short name T593
Test name
Test status
Simulation time 81976805 ps
CPU time 0.6 seconds
Started Jun 22 04:24:55 PM PDT 24
Finished Jun 22 04:24:56 PM PDT 24
Peak memory 193800 kb
Host smart-e297d16b-baa8-4d53-b477-468ef17b8071
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386753761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2386753761
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.618611536
Short name T660
Test name
Test status
Simulation time 79509608 ps
CPU time 0.79 seconds
Started Jun 22 04:24:55 PM PDT 24
Finished Jun 22 04:24:56 PM PDT 24
Peak memory 195680 kb
Host smart-75cc18ed-1791-44bd-82b4-4c947ac3ef77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618611536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.618611536
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.4085777695
Short name T172
Test name
Test status
Simulation time 3243903748 ps
CPU time 18.78 seconds
Started Jun 22 04:24:55 PM PDT 24
Finished Jun 22 04:25:14 PM PDT 24
Peak memory 196576 kb
Host smart-afbb0deb-6287-4ebb-ac01-9a40cdc488f8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085777695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.4085777695
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3922382450
Short name T656
Test name
Test status
Simulation time 154609906 ps
CPU time 0.92 seconds
Started Jun 22 04:24:58 PM PDT 24
Finished Jun 22 04:24:59 PM PDT 24
Peak memory 196828 kb
Host smart-f706569d-e5e2-4797-bd50-a8f2eb45e0cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922382450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3922382450
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.412912567
Short name T131
Test name
Test status
Simulation time 56421624 ps
CPU time 1.04 seconds
Started Jun 22 04:25:07 PM PDT 24
Finished Jun 22 04:25:09 PM PDT 24
Peak memory 195808 kb
Host smart-3e4090d3-0985-4ffb-b9b4-39f37b96e82e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412912567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.412912567
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3516385705
Short name T142
Test name
Test status
Simulation time 211416542 ps
CPU time 2.51 seconds
Started Jun 22 04:24:59 PM PDT 24
Finished Jun 22 04:25:01 PM PDT 24
Peak memory 197928 kb
Host smart-b71d702d-ab22-441a-9c99-56ec8f806783
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516385705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3516385705
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3050009748
Short name T170
Test name
Test status
Simulation time 33527655 ps
CPU time 1.42 seconds
Started Jun 22 04:25:00 PM PDT 24
Finished Jun 22 04:25:02 PM PDT 24
Peak memory 197772 kb
Host smart-421822bc-b7d5-4973-9a32-a75c99fe8346
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050009748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3050009748
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.724276621
Short name T167
Test name
Test status
Simulation time 19962781 ps
CPU time 0.69 seconds
Started Jun 22 04:25:01 PM PDT 24
Finished Jun 22 04:25:02 PM PDT 24
Peak memory 194088 kb
Host smart-17cb06c7-ba84-45c1-97ee-ae15ad7fdde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724276621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.724276621
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.679011141
Short name T369
Test name
Test status
Simulation time 26129580 ps
CPU time 1.03 seconds
Started Jun 22 04:25:06 PM PDT 24
Finished Jun 22 04:25:08 PM PDT 24
Peak memory 195736 kb
Host smart-a96ec169-2fbf-44c4-9329-c04797729fce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679011141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.679011141
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.762238631
Short name T607
Test name
Test status
Simulation time 278482552 ps
CPU time 2.69 seconds
Started Jun 22 04:25:04 PM PDT 24
Finished Jun 22 04:25:07 PM PDT 24
Peak memory 197804 kb
Host smart-872f8cbb-8718-41b2-a696-3abad48544cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762238631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.762238631
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.3053785942
Short name T634
Test name
Test status
Simulation time 70403615 ps
CPU time 0.7 seconds
Started Jun 22 04:24:58 PM PDT 24
Finished Jun 22 04:24:59 PM PDT 24
Peak memory 193960 kb
Host smart-28c6bcde-38e8-4027-9812-58d0eb249586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053785942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.3053785942
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2171718959
Short name T589
Test name
Test status
Simulation time 68016056 ps
CPU time 1.17 seconds
Started Jun 22 04:24:59 PM PDT 24
Finished Jun 22 04:25:01 PM PDT 24
Peak memory 196232 kb
Host smart-39db566e-8ec7-49d1-ae22-755f8b563446
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171718959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2171718959
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1580124344
Short name T129
Test name
Test status
Simulation time 27724956404 ps
CPU time 187.21 seconds
Started Jun 22 04:25:01 PM PDT 24
Finished Jun 22 04:28:09 PM PDT 24
Peak memory 197904 kb
Host smart-1b7c3b82-24f0-4f76-9cf6-511123ee29e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580124344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1580124344
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.3368493172
Short name T57
Test name
Test status
Simulation time 1156490274923 ps
CPU time 1427.62 seconds
Started Jun 22 04:24:53 PM PDT 24
Finished Jun 22 04:48:41 PM PDT 24
Peak memory 198020 kb
Host smart-0fd20f23-9b0b-4b15-af39-7f19d1b10020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3368493172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.3368493172
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.118516826
Short name T437
Test name
Test status
Simulation time 21631054 ps
CPU time 0.61 seconds
Started Jun 22 04:25:06 PM PDT 24
Finished Jun 22 04:25:08 PM PDT 24
Peak memory 194068 kb
Host smart-6245bfc8-eca4-48c4-8632-fd2fca785fe1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118516826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.118516826
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1710461980
Short name T298
Test name
Test status
Simulation time 63019928 ps
CPU time 0.73 seconds
Started Jun 22 04:24:48 PM PDT 24
Finished Jun 22 04:24:50 PM PDT 24
Peak memory 195020 kb
Host smart-e7a5a683-5a4e-4ab6-8418-4cdc54558091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710461980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1710461980
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1372819716
Short name T681
Test name
Test status
Simulation time 1366082821 ps
CPU time 9.4 seconds
Started Jun 22 04:25:10 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 195324 kb
Host smart-81cf399f-adde-4f16-8f24-3c2a693993a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372819716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1372819716
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2055935185
Short name T224
Test name
Test status
Simulation time 76406805 ps
CPU time 0.77 seconds
Started Jun 22 04:24:59 PM PDT 24
Finished Jun 22 04:25:00 PM PDT 24
Peak memory 195680 kb
Host smart-7527be4f-5a85-4e84-83ad-744ff943aa8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055935185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2055935185
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2231526266
Short name T516
Test name
Test status
Simulation time 146766441 ps
CPU time 1.38 seconds
Started Jun 22 04:24:56 PM PDT 24
Finished Jun 22 04:24:58 PM PDT 24
Peak memory 196928 kb
Host smart-81a5e3c2-e29d-4d8b-871a-c6999c0f44de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231526266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2231526266
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.3265495552
Short name T710
Test name
Test status
Simulation time 70031596 ps
CPU time 1.02 seconds
Started Jun 22 04:25:05 PM PDT 24
Finished Jun 22 04:25:07 PM PDT 24
Peak memory 195784 kb
Host smart-514e0104-1d7b-44fb-87e4-b3b1ef854218
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265495552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.3265495552
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.698951253
Short name T625
Test name
Test status
Simulation time 78057873 ps
CPU time 1.92 seconds
Started Jun 22 04:24:57 PM PDT 24
Finished Jun 22 04:25:00 PM PDT 24
Peak memory 195932 kb
Host smart-13f28c31-cfd3-4087-a561-35af91db12ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698951253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
698951253
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3592958456
Short name T535
Test name
Test status
Simulation time 24215239 ps
CPU time 0.81 seconds
Started Jun 22 04:25:13 PM PDT 24
Finished Jun 22 04:25:14 PM PDT 24
Peak memory 197160 kb
Host smart-430d2aa3-694f-4b70-8fd9-7e35da21c915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592958456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3592958456
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2974480397
Short name T374
Test name
Test status
Simulation time 46239309 ps
CPU time 0.94 seconds
Started Jun 22 04:24:57 PM PDT 24
Finished Jun 22 04:24:58 PM PDT 24
Peak memory 195832 kb
Host smart-7be95a49-1bf0-4832-a8e6-a848700702d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974480397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2974480397
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.464320380
Short name T7
Test name
Test status
Simulation time 183936526 ps
CPU time 2.59 seconds
Started Jun 22 04:25:04 PM PDT 24
Finished Jun 22 04:25:07 PM PDT 24
Peak memory 197744 kb
Host smart-94e09d33-50a3-44ff-a63a-31b3b742d92b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464320380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.464320380
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3480398892
Short name T280
Test name
Test status
Simulation time 142628204 ps
CPU time 0.86 seconds
Started Jun 22 04:25:04 PM PDT 24
Finished Jun 22 04:25:06 PM PDT 24
Peak memory 194932 kb
Host smart-34f73148-bd5e-4929-bd9b-6c38566edd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480398892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3480398892
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2845210311
Short name T381
Test name
Test status
Simulation time 325867489 ps
CPU time 1.41 seconds
Started Jun 22 04:24:58 PM PDT 24
Finished Jun 22 04:25:00 PM PDT 24
Peak memory 196544 kb
Host smart-32131170-7b34-4817-a4ff-5719cce1161d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845210311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2845210311
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2030931314
Short name T615
Test name
Test status
Simulation time 58088644964 ps
CPU time 179.76 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:28:16 PM PDT 24
Peak memory 197580 kb
Host smart-edaa2f65-1626-4879-8056-c1f943595e16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030931314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2030931314
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.3034236551
Short name T296
Test name
Test status
Simulation time 39376809 ps
CPU time 0.58 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:16 PM PDT 24
Peak memory 194532 kb
Host smart-c24634a5-bb3f-4b60-9af6-61bc297e66de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034236551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.3034236551
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2255409873
Short name T212
Test name
Test status
Simulation time 203817195 ps
CPU time 0.75 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 194680 kb
Host smart-c3ea2dd4-4bc4-44a7-8ae9-2bef11549c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255409873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2255409873
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.4168920498
Short name T264
Test name
Test status
Simulation time 908441303 ps
CPU time 12.88 seconds
Started Jun 22 04:25:08 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 196768 kb
Host smart-4c3954c2-cc45-482e-9c33-43bba5f5feb9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168920498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.4168920498
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2581054850
Short name T252
Test name
Test status
Simulation time 88082582 ps
CPU time 0.65 seconds
Started Jun 22 04:25:02 PM PDT 24
Finished Jun 22 04:25:03 PM PDT 24
Peak memory 194404 kb
Host smart-e176a670-f4a6-46d5-8f82-9e8d31c5561a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581054850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2581054850
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3145048426
Short name T433
Test name
Test status
Simulation time 189487857 ps
CPU time 1.02 seconds
Started Jun 22 04:24:52 PM PDT 24
Finished Jun 22 04:24:53 PM PDT 24
Peak memory 196456 kb
Host smart-d7f7b12c-37cb-4e33-8872-9920df9b1358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145048426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3145048426
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2173172449
Short name T136
Test name
Test status
Simulation time 94505390 ps
CPU time 1.16 seconds
Started Jun 22 04:25:08 PM PDT 24
Finished Jun 22 04:25:10 PM PDT 24
Peak memory 197340 kb
Host smart-beda996b-fa09-4b82-916a-40e5290eb202
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173172449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2173172449
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2206174961
Short name T353
Test name
Test status
Simulation time 560791502 ps
CPU time 2.86 seconds
Started Jun 22 04:25:04 PM PDT 24
Finished Jun 22 04:25:07 PM PDT 24
Peak memory 196808 kb
Host smart-3f6d8fc1-e71c-4c66-9b0c-a0be22ebf403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206174961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2206174961
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2633910366
Short name T452
Test name
Test status
Simulation time 47413992 ps
CPU time 0.72 seconds
Started Jun 22 04:25:02 PM PDT 24
Finished Jun 22 04:25:04 PM PDT 24
Peak memory 195136 kb
Host smart-0a0ebdb4-352a-4858-a24d-3ffdbb7fe4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633910366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2633910366
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2771584787
Short name T161
Test name
Test status
Simulation time 27095501 ps
CPU time 1.09 seconds
Started Jun 22 04:24:46 PM PDT 24
Finished Jun 22 04:24:48 PM PDT 24
Peak memory 195616 kb
Host smart-5d81b35e-d4ac-4744-8d6d-286aacaec0e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771584787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2771584787
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.2644339645
Short name T189
Test name
Test status
Simulation time 551295581 ps
CPU time 3.26 seconds
Started Jun 22 04:24:52 PM PDT 24
Finished Jun 22 04:24:55 PM PDT 24
Peak memory 197756 kb
Host smart-736e33a2-de86-44c5-8e86-4a26f19c7db6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644339645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.2644339645
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.480580433
Short name T382
Test name
Test status
Simulation time 408859719 ps
CPU time 1.28 seconds
Started Jun 22 04:25:03 PM PDT 24
Finished Jun 22 04:25:05 PM PDT 24
Peak memory 196052 kb
Host smart-247fcb4b-bd5a-44b7-b4a0-cc9ed3a816f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480580433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.480580433
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.4130238240
Short name T377
Test name
Test status
Simulation time 214855141 ps
CPU time 1.04 seconds
Started Jun 22 04:24:59 PM PDT 24
Finished Jun 22 04:25:00 PM PDT 24
Peak memory 196264 kb
Host smart-110ed575-01e8-4772-82b2-9fae774366d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130238240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.4130238240
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.2514441375
Short name T402
Test name
Test status
Simulation time 14501791611 ps
CPU time 199.02 seconds
Started Jun 22 04:24:51 PM PDT 24
Finished Jun 22 04:28:11 PM PDT 24
Peak memory 197928 kb
Host smart-e9d6f392-5bd8-4693-ad04-d8b95b6fab20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514441375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.2514441375
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1276698115
Short name T26
Test name
Test status
Simulation time 72178828520 ps
CPU time 1380.35 seconds
Started Jun 22 04:25:00 PM PDT 24
Finished Jun 22 04:48:01 PM PDT 24
Peak memory 198036 kb
Host smart-20225262-75c1-4e75-a8ae-0ffaf77523a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1276698115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1276698115
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3170038031
Short name T568
Test name
Test status
Simulation time 19813942 ps
CPU time 0.55 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 193596 kb
Host smart-e3532ac0-c558-4f85-adef-d96f8283f2d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170038031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3170038031
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1085829360
Short name T206
Test name
Test status
Simulation time 136291047 ps
CPU time 0.85 seconds
Started Jun 22 04:25:12 PM PDT 24
Finished Jun 22 04:25:14 PM PDT 24
Peak memory 196716 kb
Host smart-c225b7bc-2de8-4d58-8daf-63f2133be298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085829360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1085829360
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2291024388
Short name T695
Test name
Test status
Simulation time 835389931 ps
CPU time 10.03 seconds
Started Jun 22 04:25:12 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 195320 kb
Host smart-f586496b-87a1-4895-87a2-42c667c8eb9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291024388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2291024388
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3826506472
Short name T541
Test name
Test status
Simulation time 62871704 ps
CPU time 0.95 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 196320 kb
Host smart-4b387b99-9889-4ba7-9d1b-a1caca5d1a53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826506472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3826506472
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1385128983
Short name T401
Test name
Test status
Simulation time 18784306 ps
CPU time 0.69 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 194088 kb
Host smart-1f542863-a2df-4be6-a373-3cc6facc9f6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385128983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1385128983
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2989917012
Short name T299
Test name
Test status
Simulation time 258886987 ps
CPU time 2.5 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:18 PM PDT 24
Peak memory 196404 kb
Host smart-af7cd5e3-a446-47e1-b623-df5bf6008bb8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989917012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2989917012
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3789276250
Short name T116
Test name
Test status
Simulation time 361645513 ps
CPU time 2.15 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 196732 kb
Host smart-c83d32fb-b878-455f-b03f-6d52d80c24c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789276250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3789276250
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1736246446
Short name T635
Test name
Test status
Simulation time 139512277 ps
CPU time 0.91 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 196316 kb
Host smart-94b6fb26-2aad-4e9f-b3f3-a6ffaa0b057c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736246446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1736246446
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1909332876
Short name T166
Test name
Test status
Simulation time 28304797 ps
CPU time 0.69 seconds
Started Jun 22 04:25:06 PM PDT 24
Finished Jun 22 04:25:07 PM PDT 24
Peak memory 194108 kb
Host smart-2f52759a-a8b7-498f-80ba-fa76ca33b5bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909332876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1909332876
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.4147611195
Short name T4
Test name
Test status
Simulation time 1000966010 ps
CPU time 3.43 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 197740 kb
Host smart-254c3385-27e5-48e1-845b-59d7c9703c55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147611195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.4147611195
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.2163946113
Short name T283
Test name
Test status
Simulation time 42204175 ps
CPU time 0.84 seconds
Started Jun 22 04:25:12 PM PDT 24
Finished Jun 22 04:25:14 PM PDT 24
Peak memory 194924 kb
Host smart-40e51637-f554-4cce-9d97-1cd625eba88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163946113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.2163946113
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2975341002
Short name T263
Test name
Test status
Simulation time 61287906 ps
CPU time 1.01 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 195336 kb
Host smart-8290ff5c-787c-443e-a866-c9dee5ea1911
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975341002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2975341002
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.3570930199
Short name T319
Test name
Test status
Simulation time 5462989742 ps
CPU time 71.61 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:26:37 PM PDT 24
Peak memory 197960 kb
Host smart-7ae93d00-241c-43ad-997e-e23dffb6ad01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570930199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.3570930199
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1795010545
Short name T387
Test name
Test status
Simulation time 22434961 ps
CPU time 0.58 seconds
Started Jun 22 04:25:12 PM PDT 24
Finished Jun 22 04:25:14 PM PDT 24
Peak memory 193596 kb
Host smart-079a4f73-4e4f-41f2-96aa-8a9d85846074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795010545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1795010545
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.3133062834
Short name T605
Test name
Test status
Simulation time 73850904 ps
CPU time 0.87 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 196136 kb
Host smart-ed5df5e4-22f2-489e-aecf-ee5c375d0497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133062834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.3133062834
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2437546980
Short name T375
Test name
Test status
Simulation time 389062982 ps
CPU time 10.96 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:35 PM PDT 24
Peak memory 197796 kb
Host smart-b52a65af-f061-4549-b372-3bdb4c331af6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437546980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2437546980
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.480604241
Short name T569
Test name
Test status
Simulation time 224036596 ps
CPU time 0.73 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:16 PM PDT 24
Peak memory 194528 kb
Host smart-44e66f95-58a0-4f1e-90ef-ff7c363751ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480604241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.480604241
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.248472781
Short name T117
Test name
Test status
Simulation time 61758504 ps
CPU time 0.64 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 194704 kb
Host smart-88df47b8-be50-44f0-a846-c986e005b556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248472781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.248472781
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.268153189
Short name T427
Test name
Test status
Simulation time 51125786 ps
CPU time 1.95 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 196144 kb
Host smart-f4713ebd-8acd-4355-b3c6-7698a820cfde
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268153189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.268153189
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.3114133418
Short name T236
Test name
Test status
Simulation time 134739270 ps
CPU time 3.43 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 196956 kb
Host smart-1a844e98-c456-416e-930d-1237e5554fa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114133418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.3114133418
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1074868999
Short name T291
Test name
Test status
Simulation time 216057465 ps
CPU time 1.11 seconds
Started Jun 22 04:25:09 PM PDT 24
Finished Jun 22 04:25:11 PM PDT 24
Peak memory 195608 kb
Host smart-f9057fa5-0981-4d5e-9c0b-aa0b9c8851cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074868999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1074868999
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.429650883
Short name T155
Test name
Test status
Simulation time 70847106 ps
CPU time 0.97 seconds
Started Jun 22 04:25:11 PM PDT 24
Finished Jun 22 04:25:12 PM PDT 24
Peak memory 195864 kb
Host smart-e1eeb998-37e1-4903-b5ac-678816afbd05
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429650883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.429650883
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.1285764035
Short name T188
Test name
Test status
Simulation time 828595281 ps
CPU time 3.54 seconds
Started Jun 22 04:25:13 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 197764 kb
Host smart-01fd25df-86be-4e9f-a2fc-fbe54666eb5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285764035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.1285764035
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.701606314
Short name T602
Test name
Test status
Simulation time 158388024 ps
CPU time 1.31 seconds
Started Jun 22 04:25:32 PM PDT 24
Finished Jun 22 04:25:33 PM PDT 24
Peak memory 195648 kb
Host smart-d2f4a154-9d9e-466f-b622-2ed16d922eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701606314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.701606314
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1080696403
Short name T597
Test name
Test status
Simulation time 136215300 ps
CPU time 1.14 seconds
Started Jun 22 04:25:09 PM PDT 24
Finished Jun 22 04:25:11 PM PDT 24
Peak memory 196236 kb
Host smart-cbab44f6-70b7-4a4b-bd9f-62e8c2a094b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080696403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1080696403
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3551967867
Short name T106
Test name
Test status
Simulation time 12524305149 ps
CPU time 80.61 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:26:37 PM PDT 24
Peak memory 197908 kb
Host smart-da3eed46-d469-47ff-ba5d-3658c24e8970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551967867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3551967867
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.1963212610
Short name T312
Test name
Test status
Simulation time 26979924 ps
CPU time 0.57 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 193792 kb
Host smart-251a2f38-3e8a-4002-9729-de448f52dad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963212610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.1963212610
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2249540301
Short name T100
Test name
Test status
Simulation time 62603964 ps
CPU time 0.65 seconds
Started Jun 22 04:25:09 PM PDT 24
Finished Jun 22 04:25:10 PM PDT 24
Peak memory 193900 kb
Host smart-57fe6550-9c00-45a2-9c29-deeb0d1fbeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249540301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2249540301
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1977813914
Short name T337
Test name
Test status
Simulation time 394632775 ps
CPU time 12.33 seconds
Started Jun 22 04:25:36 PM PDT 24
Finished Jun 22 04:25:48 PM PDT 24
Peak memory 197796 kb
Host smart-ee91ddcd-46eb-4143-8fd3-6eedbf677704
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977813914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1977813914
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3316023971
Short name T192
Test name
Test status
Simulation time 67898072 ps
CPU time 0.83 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:21 PM PDT 24
Peak memory 196664 kb
Host smart-d3339257-404f-4a34-b1b0-582e586f3eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316023971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3316023971
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.239675673
Short name T712
Test name
Test status
Simulation time 152986835 ps
CPU time 1.13 seconds
Started Jun 22 04:25:06 PM PDT 24
Finished Jun 22 04:25:08 PM PDT 24
Peak memory 195776 kb
Host smart-8ea56c1c-31cc-42d6-a0db-fd4ed84576b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239675673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.239675673
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3021840205
Short name T553
Test name
Test status
Simulation time 316651781 ps
CPU time 3.13 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 197808 kb
Host smart-3666df18-14a9-456e-ac12-7a3190ba7441
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021840205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3021840205
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3434346506
Short name T640
Test name
Test status
Simulation time 89809692 ps
CPU time 1.99 seconds
Started Jun 22 04:25:07 PM PDT 24
Finished Jun 22 04:25:10 PM PDT 24
Peak memory 196016 kb
Host smart-9a38d19c-e254-4fcf-9dfc-8ccddcdf6971
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434346506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3434346506
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.4203200951
Short name T705
Test name
Test status
Simulation time 69954960 ps
CPU time 0.94 seconds
Started Jun 22 04:25:14 PM PDT 24
Finished Jun 22 04:25:15 PM PDT 24
Peak memory 195608 kb
Host smart-90c6dafc-5e0f-41b5-9873-cc93544f4619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203200951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.4203200951
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3098946766
Short name T600
Test name
Test status
Simulation time 136045833 ps
CPU time 1.13 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 195760 kb
Host smart-56e66b64-c0ed-480a-bf0f-f470551cdd63
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098946766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3098946766
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2114534386
Short name T539
Test name
Test status
Simulation time 765302480 ps
CPU time 2.82 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 197892 kb
Host smart-ef075a02-7728-4529-8701-fdbda12fa66f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114534386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2114534386
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3604495838
Short name T626
Test name
Test status
Simulation time 118368495 ps
CPU time 0.76 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:18 PM PDT 24
Peak memory 195080 kb
Host smart-65fd226e-8fdc-4c34-886d-7c603e1f8c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604495838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3604495838
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3244344522
Short name T285
Test name
Test status
Simulation time 108551853 ps
CPU time 1.13 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 196488 kb
Host smart-960bb7bf-5062-4c7a-9262-9115f23bcda0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244344522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3244344522
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2241428555
Short name T395
Test name
Test status
Simulation time 17042439944 ps
CPU time 178.78 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:28:25 PM PDT 24
Peak memory 197852 kb
Host smart-91998d1f-31f3-47d0-9700-eb348306a942
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241428555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2241428555
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1609048341
Short name T203
Test name
Test status
Simulation time 23415247 ps
CPU time 0.61 seconds
Started Jun 22 04:25:14 PM PDT 24
Finished Jun 22 04:25:15 PM PDT 24
Peak memory 194496 kb
Host smart-c8cd367c-eb1a-4171-b969-c08e43d45cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609048341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1609048341
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2004936228
Short name T514
Test name
Test status
Simulation time 66431169 ps
CPU time 0.71 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 194948 kb
Host smart-ed1a879a-e6a8-4bf3-a8aa-c8d05acd66ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004936228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2004936228
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2598046249
Short name T428
Test name
Test status
Simulation time 1313795711 ps
CPU time 11.7 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:31 PM PDT 24
Peak memory 195324 kb
Host smart-1aa0c1ad-1c1d-4ff5-a968-eb8d57408ad7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598046249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2598046249
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.961680928
Short name T704
Test name
Test status
Simulation time 36317913 ps
CPU time 0.69 seconds
Started Jun 22 04:25:07 PM PDT 24
Finished Jun 22 04:25:09 PM PDT 24
Peak memory 194344 kb
Host smart-cc547749-f301-482f-99c4-fd586e595872
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961680928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.961680928
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1102698528
Short name T532
Test name
Test status
Simulation time 28890723 ps
CPU time 0.8 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 195364 kb
Host smart-4d0470d6-3041-4a1c-966e-ee8998d1a71d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102698528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1102698528
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2314827057
Short name T551
Test name
Test status
Simulation time 19199812 ps
CPU time 0.88 seconds
Started Jun 22 04:25:06 PM PDT 24
Finished Jun 22 04:25:07 PM PDT 24
Peak memory 195704 kb
Host smart-4614fe5b-01bf-46a1-81b5-893d33d0bc93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314827057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2314827057
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.1620783920
Short name T339
Test name
Test status
Simulation time 332881678 ps
CPU time 1.99 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:18 PM PDT 24
Peak memory 196044 kb
Host smart-1b6d79c2-40e1-43b2-a84d-fe4a1af2f9bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620783920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.1620783920
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2953706940
Short name T177
Test name
Test status
Simulation time 135315790 ps
CPU time 0.92 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 196688 kb
Host smart-ce1fb1ae-e390-4185-b9a0-37ec38222397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953706940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2953706940
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2377206503
Short name T325
Test name
Test status
Simulation time 49892185 ps
CPU time 1.12 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:21 PM PDT 24
Peak memory 195864 kb
Host smart-1ab77e8b-7dee-4f9c-9b50-814820bac50a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377206503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2377206503
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.4072885405
Short name T406
Test name
Test status
Simulation time 838003626 ps
CPU time 4.21 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 197784 kb
Host smart-92cc4e2d-ba5e-4664-998f-27887d68c07a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072885405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.4072885405
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1474813247
Short name T225
Test name
Test status
Simulation time 66184394 ps
CPU time 1.23 seconds
Started Jun 22 04:25:13 PM PDT 24
Finished Jun 22 04:25:15 PM PDT 24
Peak memory 197840 kb
Host smart-d25c8a06-ce5b-405a-8c59-902918564d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474813247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1474813247
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3537523097
Short name T346
Test name
Test status
Simulation time 43614541 ps
CPU time 0.93 seconds
Started Jun 22 04:25:10 PM PDT 24
Finished Jun 22 04:25:12 PM PDT 24
Peak memory 195588 kb
Host smart-72225a67-2663-481b-8daf-8031b5a2d0c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537523097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3537523097
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1699022767
Short name T676
Test name
Test status
Simulation time 34058964042 ps
CPU time 114.83 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:27:20 PM PDT 24
Peak memory 191556 kb
Host smart-b9aa1244-6d2e-429e-8ad1-b02d8c30950e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699022767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1699022767
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2882618807
Short name T21
Test name
Test status
Simulation time 24294354 ps
CPU time 0.55 seconds
Started Jun 22 04:25:08 PM PDT 24
Finished Jun 22 04:25:10 PM PDT 24
Peak memory 193596 kb
Host smart-dfee0090-41fe-48ae-a6de-0c301baed5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882618807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2882618807
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3444579682
Short name T425
Test name
Test status
Simulation time 33675147 ps
CPU time 0.77 seconds
Started Jun 22 04:25:13 PM PDT 24
Finished Jun 22 04:25:15 PM PDT 24
Peak memory 195020 kb
Host smart-bc571efe-2ea5-4d07-bf71-05ab3dad8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444579682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3444579682
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.174164163
Short name T447
Test name
Test status
Simulation time 2107867872 ps
CPU time 25.02 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:48 PM PDT 24
Peak memory 197800 kb
Host smart-9e118221-97d5-49ed-8fd2-88e0cefcee9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174164163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.174164163
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.4200175069
Short name T8
Test name
Test status
Simulation time 219320320 ps
CPU time 1.01 seconds
Started Jun 22 04:25:10 PM PDT 24
Finished Jun 22 04:25:11 PM PDT 24
Peak memory 196076 kb
Host smart-c1246a8c-dd32-41f4-9116-7734eaf1317f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200175069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.4200175069
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3430609388
Short name T512
Test name
Test status
Simulation time 99706969 ps
CPU time 0.66 seconds
Started Jun 22 04:25:05 PM PDT 24
Finished Jun 22 04:25:06 PM PDT 24
Peak memory 193984 kb
Host smart-6b3a225e-c368-4bd8-a711-853a2fae7cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430609388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3430609388
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.1735749459
Short name T436
Test name
Test status
Simulation time 79548742 ps
CPU time 2.93 seconds
Started Jun 22 04:25:11 PM PDT 24
Finished Jun 22 04:25:14 PM PDT 24
Peak memory 197764 kb
Host smart-7d1ab176-4920-4246-bf90-b72bbf351317
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735749459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.1735749459
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.624057007
Short name T64
Test name
Test status
Simulation time 138381334 ps
CPU time 2.95 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 197888 kb
Host smart-5f2df427-e70d-442c-89cb-6044dc3434ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624057007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
624057007
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.498124318
Short name T413
Test name
Test status
Simulation time 35150177 ps
CPU time 0.72 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 195216 kb
Host smart-02666b4e-91fb-4170-9d7e-e03533f53e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498124318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.498124318
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1569063684
Short name T523
Test name
Test status
Simulation time 61835276 ps
CPU time 1.16 seconds
Started Jun 22 04:25:13 PM PDT 24
Finished Jun 22 04:25:14 PM PDT 24
Peak memory 197896 kb
Host smart-3f88a267-1dc9-4ad9-a97f-86ac8db6dd36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569063684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1569063684
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1544142401
Short name T606
Test name
Test status
Simulation time 476164617 ps
CPU time 4.97 seconds
Started Jun 22 04:25:14 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 197748 kb
Host smart-9d2a3dc4-02d7-45c4-8adc-abd0ba19a315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544142401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1544142401
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2629050992
Short name T620
Test name
Test status
Simulation time 71031879 ps
CPU time 1.01 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 195580 kb
Host smart-153cacd9-c4d6-42aa-bde8-0ddeed9b5e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629050992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2629050992
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.368099705
Short name T112
Test name
Test status
Simulation time 336728763 ps
CPU time 0.92 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 196244 kb
Host smart-662f0b3a-f5a5-4610-b25e-fd6a9cfd8e93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368099705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.368099705
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3285417129
Short name T649
Test name
Test status
Simulation time 3843039852 ps
CPU time 44.38 seconds
Started Jun 22 04:25:10 PM PDT 24
Finished Jun 22 04:25:55 PM PDT 24
Peak memory 197872 kb
Host smart-9eaf9d8a-29f2-4e45-9820-ee8b723fe03e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285417129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3285417129
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1575376303
Short name T22
Test name
Test status
Simulation time 36965359 ps
CPU time 0.64 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 193892 kb
Host smart-f4484490-916f-4589-94dc-4a78f1a40fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575376303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1575376303
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4018288760
Short name T482
Test name
Test status
Simulation time 16094919 ps
CPU time 0.6 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 193904 kb
Host smart-6a308a8c-a11f-4a4b-a4c4-840765e097eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018288760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4018288760
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.4077509893
Short name T485
Test name
Test status
Simulation time 229332888 ps
CPU time 5.64 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 195288 kb
Host smart-d187870c-6383-46b1-a1d0-c81a82426267
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077509893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.4077509893
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3185585001
Short name T309
Test name
Test status
Simulation time 22370378 ps
CPU time 0.62 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 194328 kb
Host smart-665cfa13-5b4f-4e3a-8f4e-3a66ee184df6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185585001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3185585001
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1947134786
Short name T210
Test name
Test status
Simulation time 237171526 ps
CPU time 0.92 seconds
Started Jun 22 04:25:11 PM PDT 24
Finished Jun 22 04:25:13 PM PDT 24
Peak memory 195584 kb
Host smart-5876ba26-dca1-43ab-a29a-8827a558bfda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947134786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1947134786
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1133816170
Short name T570
Test name
Test status
Simulation time 75356896 ps
CPU time 2.87 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 196100 kb
Host smart-fef68b8c-fedb-4755-a5b2-6c7f40e8a7c5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133816170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1133816170
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.324308148
Short name T370
Test name
Test status
Simulation time 614948697 ps
CPU time 3.07 seconds
Started Jun 22 04:25:13 PM PDT 24
Finished Jun 22 04:25:17 PM PDT 24
Peak memory 196760 kb
Host smart-f15027d0-dbc1-4c98-b76c-3809a4b011b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324308148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
324308148
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3188311798
Short name T250
Test name
Test status
Simulation time 93981878 ps
CPU time 1.01 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 195932 kb
Host smart-39a4e278-14b2-4f65-9aa4-ca01affc33dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188311798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3188311798
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.612227602
Short name T562
Test name
Test status
Simulation time 272460948 ps
CPU time 1.22 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 196344 kb
Host smart-1ff67ac7-fa36-46e5-a12f-a04123bb064d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612227602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.612227602
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_smoke.95780843
Short name T154
Test name
Test status
Simulation time 226081603 ps
CPU time 1.16 seconds
Started Jun 22 04:25:13 PM PDT 24
Finished Jun 22 04:25:15 PM PDT 24
Peak memory 196012 kb
Host smart-5da56b3b-a916-4511-b675-b0532e1cdcce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95780843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.95780843
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2773492023
Short name T197
Test name
Test status
Simulation time 44920978 ps
CPU time 1.08 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 195452 kb
Host smart-60e49d7a-2169-4c75-a784-885de2e4a30a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773492023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2773492023
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.4033163323
Short name T268
Test name
Test status
Simulation time 2475871096 ps
CPU time 67.54 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:26:30 PM PDT 24
Peak memory 197968 kb
Host smart-8d9d13c1-e87d-46ad-a32e-764ff4e47b88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033163323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.4033163323
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.4250224885
Short name T572
Test name
Test status
Simulation time 37201945665 ps
CPU time 529.2 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:34:12 PM PDT 24
Peak memory 197972 kb
Host smart-db0b3ef5-5391-42cc-b619-bb84473652a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4250224885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.4250224885
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2636909827
Short name T34
Test name
Test status
Simulation time 45340618 ps
CPU time 0.58 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 193876 kb
Host smart-55fe9d56-92c5-4453-93f6-c1ad99749f01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636909827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2636909827
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3409813889
Short name T702
Test name
Test status
Simulation time 71554695 ps
CPU time 0.82 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 196296 kb
Host smart-cceba51d-7892-4938-8f03-90b915a29c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409813889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3409813889
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1202799809
Short name T156
Test name
Test status
Simulation time 319667579 ps
CPU time 10.25 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 196684 kb
Host smart-671c0fc4-ed65-4327-872e-4a6827a84610
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202799809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1202799809
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.3171087745
Short name T617
Test name
Test status
Simulation time 62265469 ps
CPU time 0.93 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 195708 kb
Host smart-db177c78-c2fa-4307-9243-fe1b5b37862f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171087745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.3171087745
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.987729668
Short name T108
Test name
Test status
Simulation time 423402698 ps
CPU time 1.22 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:30 PM PDT 24
Peak memory 195836 kb
Host smart-6252d5d6-03f4-41e7-b2da-01a707e3dd16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987729668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.987729668
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.425239080
Short name T409
Test name
Test status
Simulation time 227065795 ps
CPU time 2.17 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:21 PM PDT 24
Peak memory 197824 kb
Host smart-d869d6a8-c932-4be9-84b4-e55fc03e95f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425239080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.425239080
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1578778417
Short name T540
Test name
Test status
Simulation time 236928772 ps
CPU time 3.66 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 196960 kb
Host smart-cc0079ab-2715-4e12-9dde-9d7e388915a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578778417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1578778417
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.2300944031
Short name T146
Test name
Test status
Simulation time 40492395 ps
CPU time 1.09 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 196308 kb
Host smart-c93a010a-f110-4250-8839-5f6dbe3025ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300944031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.2300944031
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2703510044
Short name T335
Test name
Test status
Simulation time 73684580 ps
CPU time 0.69 seconds
Started Jun 22 04:25:31 PM PDT 24
Finished Jun 22 04:25:32 PM PDT 24
Peak memory 195180 kb
Host smart-fcc1c624-6d4f-4492-8be6-66b78cdcf7e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703510044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2703510044
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.32954088
Short name T163
Test name
Test status
Simulation time 271653613 ps
CPU time 1.1 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 196340 kb
Host smart-6bcb7638-54f8-46d9-a2ab-98819e8cea42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32954088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand
om_long_reg_writes_reg_reads.32954088
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.875921807
Short name T286
Test name
Test status
Simulation time 62044600 ps
CPU time 1.31 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 197800 kb
Host smart-7165ce02-0052-402f-8c4e-4060a04163a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875921807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.875921807
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.13939671
Short name T573
Test name
Test status
Simulation time 134897709 ps
CPU time 1.23 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 195336 kb
Host smart-bc5faa51-1c85-41da-9076-3d804fbbe738
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13939671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.13939671
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1890376745
Short name T554
Test name
Test status
Simulation time 68100681870 ps
CPU time 160.62 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:27:58 PM PDT 24
Peak memory 197888 kb
Host smart-a5427564-7ab4-4c9d-9f5d-aa8fe2974246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890376745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1890376745
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2795883454
Short name T450
Test name
Test status
Simulation time 64007426 ps
CPU time 0.58 seconds
Started Jun 22 04:24:14 PM PDT 24
Finished Jun 22 04:24:15 PM PDT 24
Peak memory 194252 kb
Host smart-8ab51ce6-bf91-4ab6-b90c-bcb1a943d508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795883454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2795883454
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3403185223
Short name T274
Test name
Test status
Simulation time 116806162 ps
CPU time 0.78 seconds
Started Jun 22 04:23:50 PM PDT 24
Finished Jun 22 04:23:51 PM PDT 24
Peak memory 194872 kb
Host smart-15765b67-295d-444b-a0fb-077d74c2469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403185223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3403185223
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.409108480
Short name T23
Test name
Test status
Simulation time 2004172835 ps
CPU time 23.87 seconds
Started Jun 22 04:24:25 PM PDT 24
Finished Jun 22 04:24:51 PM PDT 24
Peak memory 196620 kb
Host smart-de659cba-3669-419f-90eb-d6d361bd327e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409108480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress
.409108480
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2835306055
Short name T665
Test name
Test status
Simulation time 68124716 ps
CPU time 1.02 seconds
Started Jun 22 04:23:42 PM PDT 24
Finished Jun 22 04:23:44 PM PDT 24
Peak memory 195300 kb
Host smart-405e2a4b-ec1b-4366-ac07-805b80ada677
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835306055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2835306055
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3461076302
Short name T198
Test name
Test status
Simulation time 22441153 ps
CPU time 0.72 seconds
Started Jun 22 04:23:56 PM PDT 24
Finished Jun 22 04:23:58 PM PDT 24
Peak memory 193232 kb
Host smart-5f5d449e-cbec-43b2-a659-c6c41999c84a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461076302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3461076302
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2884483210
Short name T92
Test name
Test status
Simulation time 63113090 ps
CPU time 1.34 seconds
Started Jun 22 04:23:50 PM PDT 24
Finished Jun 22 04:23:52 PM PDT 24
Peak memory 195576 kb
Host smart-bdbe70dc-d49e-453b-b778-1b0022a1ac98
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884483210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2884483210
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.2131188354
Short name T601
Test name
Test status
Simulation time 353842849 ps
CPU time 1.26 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:12 PM PDT 24
Peak memory 196292 kb
Host smart-a1cc77e3-1659-4670-997d-166b0902b804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131188354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
2131188354
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3097876470
Short name T509
Test name
Test status
Simulation time 179118499 ps
CPU time 1.15 seconds
Started Jun 22 04:23:39 PM PDT 24
Finished Jun 22 04:23:41 PM PDT 24
Peak memory 196904 kb
Host smart-f1d31f1c-34e3-45d8-b906-045ebe2e2b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097876470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3097876470
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.3825955715
Short name T470
Test name
Test status
Simulation time 56648011 ps
CPU time 1.3 seconds
Started Jun 22 04:24:07 PM PDT 24
Finished Jun 22 04:24:10 PM PDT 24
Peak memory 195728 kb
Host smart-58fc1757-825d-47b3-9081-fb48a34d03ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825955715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.3825955715
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3146392672
Short name T216
Test name
Test status
Simulation time 4133457510 ps
CPU time 6.03 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:16 PM PDT 24
Peak memory 197828 kb
Host smart-e042ccc3-227f-4b9a-a252-83866a45499b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146392672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3146392672
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.826467132
Short name T43
Test name
Test status
Simulation time 114788019 ps
CPU time 0.77 seconds
Started Jun 22 04:24:24 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 213372 kb
Host smart-3ae24584-e3f7-4310-85e0-544e64f47c13
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826467132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.826467132
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4156512946
Short name T246
Test name
Test status
Simulation time 37135326 ps
CPU time 1.06 seconds
Started Jun 22 04:23:57 PM PDT 24
Finished Jun 22 04:23:58 PM PDT 24
Peak memory 195564 kb
Host smart-3eab7f67-d3ce-4020-8d8d-c8725a19eb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156512946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4156512946
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2886234682
Short name T147
Test name
Test status
Simulation time 146779343 ps
CPU time 0.87 seconds
Started Jun 22 04:23:39 PM PDT 24
Finished Jun 22 04:23:40 PM PDT 24
Peak memory 195476 kb
Host smart-ef90806f-903b-4545-bba5-80515f4b7709
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886234682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2886234682
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3093173296
Short name T308
Test name
Test status
Simulation time 9346062390 ps
CPU time 110.38 seconds
Started Jun 22 04:24:04 PM PDT 24
Finished Jun 22 04:25:55 PM PDT 24
Peak memory 197912 kb
Host smart-0cb1ee50-5d63-419a-9999-ee69f4fc8ed7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093173296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3093173296
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.478237642
Short name T279
Test name
Test status
Simulation time 12870999 ps
CPU time 0.6 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 193592 kb
Host smart-0b16affb-ff95-4d4f-95ae-6e7e477af515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478237642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.478237642
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2393006053
Short name T557
Test name
Test status
Simulation time 57874003 ps
CPU time 0.61 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:16 PM PDT 24
Peak memory 194308 kb
Host smart-246b1174-f406-46bd-bdf9-82bde58a2b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393006053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2393006053
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.2451009580
Short name T504
Test name
Test status
Simulation time 3157016837 ps
CPU time 27.1 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:50 PM PDT 24
Peak memory 197916 kb
Host smart-7fa55025-9a7b-4895-865d-aa18f006756e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451009580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.2451009580
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.115737753
Short name T303
Test name
Test status
Simulation time 32892857 ps
CPU time 0.73 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 194504 kb
Host smart-9e16b2b2-c794-43f5-b8f2-ffc2f9f5cb4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115737753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.115737753
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1950131873
Short name T637
Test name
Test status
Simulation time 41720694 ps
CPU time 0.83 seconds
Started Jun 22 04:25:41 PM PDT 24
Finished Jun 22 04:25:42 PM PDT 24
Peak memory 195284 kb
Host smart-bd8f0f92-8952-4a53-bca1-c68a73ef7a07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950131873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1950131873
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3627546256
Short name T580
Test name
Test status
Simulation time 78484860 ps
CPU time 2.98 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:20 PM PDT 24
Peak memory 197968 kb
Host smart-b7b178a3-4541-4d00-b212-af6ba96d025d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627546256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3627546256
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2308208900
Short name T701
Test name
Test status
Simulation time 223433313 ps
CPU time 2.53 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 196824 kb
Host smart-d5a75246-8fb7-42ae-96c2-ec8ff8333a84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308208900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2308208900
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2313048826
Short name T499
Test name
Test status
Simulation time 69814030 ps
CPU time 0.91 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195608 kb
Host smart-34f44f6b-c2e9-42e8-ba9d-690cfb7bf2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313048826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2313048826
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2059816416
Short name T564
Test name
Test status
Simulation time 71593562 ps
CPU time 0.94 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:21 PM PDT 24
Peak memory 196344 kb
Host smart-163108c7-72c9-4393-84b5-515b471cde88
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059816416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2059816416
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3382775830
Short name T691
Test name
Test status
Simulation time 864388793 ps
CPU time 2.71 seconds
Started Jun 22 04:25:49 PM PDT 24
Finished Jun 22 04:25:53 PM PDT 24
Peak memory 197712 kb
Host smart-23c9b031-8792-49cc-8562-dc04c9bb4ec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382775830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3382775830
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.333367437
Short name T610
Test name
Test status
Simulation time 22615557 ps
CPU time 0.79 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 196172 kb
Host smart-e12e352b-362b-42df-8633-979f78c164ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333367437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.333367437
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.61645238
Short name T565
Test name
Test status
Simulation time 220632540 ps
CPU time 1.15 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 196280 kb
Host smart-bc93e9c6-58ec-4561-9227-c7f9fbcf6619
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61645238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.61645238
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3381283972
Short name T143
Test name
Test status
Simulation time 50353947248 ps
CPU time 65.62 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:26:25 PM PDT 24
Peak memory 197944 kb
Host smart-9332bfbc-f64c-4bc1-a811-7a09196ba508
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381283972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3381283972
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.4131418564
Short name T571
Test name
Test status
Simulation time 249603878905 ps
CPU time 1795.5 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:55:23 PM PDT 24
Peak memory 197980 kb
Host smart-cddd9b63-f01b-47db-826c-f21c39211c25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4131418564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.4131418564
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2369670237
Short name T621
Test name
Test status
Simulation time 13049740 ps
CPU time 0.57 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 193760 kb
Host smart-a40a903b-d9a7-487d-8396-7a434ae575f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369670237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2369670237
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1753547758
Short name T266
Test name
Test status
Simulation time 50885103 ps
CPU time 0.83 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 195784 kb
Host smart-fd517a71-1659-48d1-a260-e2ad3b420a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753547758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1753547758
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.469094344
Short name T265
Test name
Test status
Simulation time 295575078 ps
CPU time 15.34 seconds
Started Jun 22 04:25:33 PM PDT 24
Finished Jun 22 04:25:48 PM PDT 24
Peak memory 197928 kb
Host smart-b145c478-184d-44d0-b580-e615d622801c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469094344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.469094344
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.948289856
Short name T548
Test name
Test status
Simulation time 826015341 ps
CPU time 1.02 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 196364 kb
Host smart-bcb1e1b5-8afa-467c-bbf2-a085b3db982b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948289856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.948289856
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1188044003
Short name T612
Test name
Test status
Simulation time 60748829 ps
CPU time 0.66 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 194136 kb
Host smart-63ef39d0-1fae-42a3-be4a-f0848a2be305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188044003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1188044003
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1922837735
Short name T199
Test name
Test status
Simulation time 270314992 ps
CPU time 2.72 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 197904 kb
Host smart-534a58b2-1048-4ea8-861d-833b346404ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922837735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1922837735
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3982725758
Short name T647
Test name
Test status
Simulation time 71076258 ps
CPU time 2.1 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 197812 kb
Host smart-85324c98-0bfa-47c1-ba4e-53ff32f0bc2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982725758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3982725758
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3238338992
Short name T120
Test name
Test status
Simulation time 79115586 ps
CPU time 1.28 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 196784 kb
Host smart-407cf3b9-14ab-4d20-b6f0-d1c15ccf0b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238338992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3238338992
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2736182276
Short name T531
Test name
Test status
Simulation time 59284658 ps
CPU time 1.25 seconds
Started Jun 22 04:25:31 PM PDT 24
Finished Jun 22 04:25:33 PM PDT 24
Peak memory 197852 kb
Host smart-d33f101a-8632-4029-a75b-e41c08797f3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736182276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2736182276
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.2618141583
Short name T186
Test name
Test status
Simulation time 261676834 ps
CPU time 5.6 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:32 PM PDT 24
Peak memory 197788 kb
Host smart-cc69fd49-d90e-469c-a485-b3b15ad7f64d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618141583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.2618141583
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2514981013
Short name T693
Test name
Test status
Simulation time 78618721 ps
CPU time 0.84 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195812 kb
Host smart-35d3ba48-446c-466d-9a6e-a744a453e4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514981013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2514981013
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2159079851
Short name T579
Test name
Test status
Simulation time 564716961 ps
CPU time 1.06 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 195304 kb
Host smart-5b2a7155-bd3d-4c8b-9e25-1ba86142e101
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159079851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2159079851
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2906170479
Short name T493
Test name
Test status
Simulation time 7205770201 ps
CPU time 189.01 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:28:35 PM PDT 24
Peak memory 197868 kb
Host smart-a86aec2d-80a5-41a8-8fc0-b3051b877542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906170479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2906170479
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3342265234
Short name T119
Test name
Test status
Simulation time 23807333 ps
CPU time 0.54 seconds
Started Jun 22 04:25:14 PM PDT 24
Finished Jun 22 04:25:15 PM PDT 24
Peak memory 193640 kb
Host smart-b7805893-144a-48ee-b5ac-88dd3b571938
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342265234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3342265234
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.4091053470
Short name T411
Test name
Test status
Simulation time 60975608 ps
CPU time 0.77 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 192460 kb
Host smart-88796242-0723-4c6c-8ea8-b62abefec0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091053470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.4091053470
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2867190976
Short name T388
Test name
Test status
Simulation time 759431027 ps
CPU time 23.98 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:48 PM PDT 24
Peak memory 196952 kb
Host smart-7062d6e4-c99f-4a2c-8904-911c4cdf61fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867190976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2867190976
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.660342798
Short name T397
Test name
Test status
Simulation time 328192842 ps
CPU time 1.04 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 195136 kb
Host smart-9348f51b-df42-4faa-9e39-c5fcc9ea95fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660342798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.660342798
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1330873465
Short name T552
Test name
Test status
Simulation time 350531773 ps
CPU time 1.18 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 195836 kb
Host smart-073c1311-0529-4983-8f63-8b15069d8254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330873465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1330873465
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.273085416
Short name T115
Test name
Test status
Simulation time 223321068 ps
CPU time 2.32 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:30 PM PDT 24
Peak memory 197460 kb
Host smart-8ce0cc37-c0d3-46c6-b377-90f63b55c3f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273085416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.273085416
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.163344545
Short name T488
Test name
Test status
Simulation time 151423744 ps
CPU time 1.03 seconds
Started Jun 22 04:25:24 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 196152 kb
Host smart-eef22bf8-421a-40f0-8ea0-29de9d1f85e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163344545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
163344545
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.610681148
Short name T528
Test name
Test status
Simulation time 50798581 ps
CPU time 1.1 seconds
Started Jun 22 04:25:30 PM PDT 24
Finished Jun 22 04:25:32 PM PDT 24
Peak memory 196448 kb
Host smart-80b6d8bc-628c-4767-bced-37b406453633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610681148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.610681148
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.4042973192
Short name T195
Test name
Test status
Simulation time 128979878 ps
CPU time 1.23 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 196436 kb
Host smart-8a7d4304-e892-47ac-9baf-85566208da7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042973192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.4042973192
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1184692751
Short name T666
Test name
Test status
Simulation time 1529177445 ps
CPU time 5.56 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:30 PM PDT 24
Peak memory 197804 kb
Host smart-58aed79d-fc77-4602-a1af-775e7707886c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184692751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1184692751
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.645497260
Short name T310
Test name
Test status
Simulation time 32369310 ps
CPU time 0.91 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 194988 kb
Host smart-12bbcfec-f05a-457c-8e3e-9685763656b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645497260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.645497260
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3678320806
Short name T383
Test name
Test status
Simulation time 36707785 ps
CPU time 0.88 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 195752 kb
Host smart-faa764b3-1204-4ab9-b075-8af896b036a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678320806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3678320806
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1317244362
Short name T596
Test name
Test status
Simulation time 25398091436 ps
CPU time 73.27 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:26:40 PM PDT 24
Peak memory 197952 kb
Host smart-f2c7a9b5-d64c-477a-bb69-3b704ad1e6ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317244362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1317244362
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2123663860
Short name T67
Test name
Test status
Simulation time 925408978859 ps
CPU time 2284.92 seconds
Started Jun 22 04:25:49 PM PDT 24
Finished Jun 22 05:03:55 PM PDT 24
Peak memory 197984 kb
Host smart-b48f38c7-37ad-4f9f-b380-f3d94a7fbf98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2123663860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2123663860
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2564679589
Short name T672
Test name
Test status
Simulation time 12798041 ps
CPU time 0.56 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 193788 kb
Host smart-d0c1df99-de90-4b53-9557-13f622a4e931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564679589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2564679589
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.719063168
Short name T471
Test name
Test status
Simulation time 43072904 ps
CPU time 0.73 seconds
Started Jun 22 04:25:11 PM PDT 24
Finished Jun 22 04:25:12 PM PDT 24
Peak memory 194912 kb
Host smart-28c0d16f-8a24-4351-9842-d3ef3cc9755c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719063168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.719063168
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1825351379
Short name T350
Test name
Test status
Simulation time 350509842 ps
CPU time 18.03 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:45 PM PDT 24
Peak memory 197764 kb
Host smart-7b3dcb96-198d-49bf-b4be-8d97c1cd4311
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825351379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1825351379
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1851376447
Short name T521
Test name
Test status
Simulation time 18158020 ps
CPU time 0.62 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 194968 kb
Host smart-d7c21a2e-32ab-44e8-8aa8-45ba6eabf749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851376447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1851376447
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2893266746
Short name T220
Test name
Test status
Simulation time 46490698 ps
CPU time 1.16 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 196956 kb
Host smart-ae20a278-42ca-474a-9fe8-943d43d060db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893266746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2893266746
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4034340472
Short name T675
Test name
Test status
Simulation time 145796397 ps
CPU time 2.85 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 197848 kb
Host smart-04ca9c45-4ba8-4c17-9dd0-566c4471e7f0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034340472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4034340472
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.3760575301
Short name T305
Test name
Test status
Simulation time 90214785 ps
CPU time 1.57 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 196732 kb
Host smart-e39f13e1-158e-4622-8474-776a4629bd0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760575301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.3760575301
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1680652067
Short name T262
Test name
Test status
Simulation time 60054983 ps
CPU time 1.26 seconds
Started Jun 22 04:26:14 PM PDT 24
Finished Jun 22 04:26:20 PM PDT 24
Peak memory 195700 kb
Host smart-7647d2d1-282d-459e-b454-d84083beb4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680652067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1680652067
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1442958981
Short name T288
Test name
Test status
Simulation time 35358804 ps
CPU time 0.88 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:21 PM PDT 24
Peak memory 196352 kb
Host smart-6aba6480-9f0d-432d-af7a-d600fe41074a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442958981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1442958981
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3695703712
Short name T326
Test name
Test status
Simulation time 284610217 ps
CPU time 1.36 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 197768 kb
Host smart-747ae871-18fb-4ff2-a12e-cac5d9e7b5c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695703712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3695703712
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1300207893
Short name T478
Test name
Test status
Simulation time 137192055 ps
CPU time 1.29 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 197844 kb
Host smart-48044f16-9361-4b51-b8d3-c907f80822d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300207893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1300207893
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.304224603
Short name T226
Test name
Test status
Simulation time 41080028 ps
CPU time 1.08 seconds
Started Jun 22 04:25:14 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 196324 kb
Host smart-9810cb17-61e9-41f1-a90f-ebe8589fc6f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304224603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.304224603
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1447731784
Short name T588
Test name
Test status
Simulation time 13395763763 ps
CPU time 171.25 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:28:15 PM PDT 24
Peak memory 197924 kb
Host smart-62451292-64b8-4ac6-91bd-2e5548f3ca3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447731784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1447731784
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.831326885
Short name T669
Test name
Test status
Simulation time 25374598 ps
CPU time 0.56 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 193668 kb
Host smart-8ab75e24-1b52-47d7-b4fc-c21638756c7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831326885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.831326885
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.3621107941
Short name T586
Test name
Test status
Simulation time 30052929 ps
CPU time 0.74 seconds
Started Jun 22 04:25:12 PM PDT 24
Finished Jun 22 04:25:13 PM PDT 24
Peak memory 195108 kb
Host smart-4a3e6891-6763-48e5-8c9d-434177d37200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621107941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.3621107941
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2043172335
Short name T544
Test name
Test status
Simulation time 3907011670 ps
CPU time 29 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:51 PM PDT 24
Peak memory 196452 kb
Host smart-1c4f8653-d5b1-4007-b013-5c3b04a18990
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043172335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2043172335
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.991614755
Short name T361
Test name
Test status
Simulation time 60360229 ps
CPU time 0.96 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 196756 kb
Host smart-180eba4b-8c44-4512-b333-f000e79f3545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991614755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.991614755
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3389936460
Short name T171
Test name
Test status
Simulation time 39304098 ps
CPU time 0.81 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195724 kb
Host smart-04688b35-4b40-4c8a-9950-86bf79532753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389936460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3389936460
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.141482598
Short name T714
Test name
Test status
Simulation time 117730129 ps
CPU time 1.03 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 197156 kb
Host smart-b36edb75-6e58-4da6-92d8-2c956cbe00c8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141482598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.141482598
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4002599947
Short name T363
Test name
Test status
Simulation time 533709668 ps
CPU time 2.48 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 194908 kb
Host smart-b98b5e3e-6731-4961-bd13-a2cdad7bb08c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002599947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4002599947
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1328658794
Short name T190
Test name
Test status
Simulation time 117390769 ps
CPU time 0.83 seconds
Started Jun 22 04:25:50 PM PDT 24
Finished Jun 22 04:25:51 PM PDT 24
Peak memory 195900 kb
Host smart-b76abe18-60fd-4804-bf6b-1542be09ac91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328658794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1328658794
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1834477065
Short name T342
Test name
Test status
Simulation time 32033887 ps
CPU time 1.21 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 196328 kb
Host smart-63dd4b52-9d20-46dd-ab52-6db30f2bcb40
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834477065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1834477065
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1543909109
Short name T183
Test name
Test status
Simulation time 796713134 ps
CPU time 4.16 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 197804 kb
Host smart-f116d971-d792-45ab-a33c-544474c96782
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543909109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1543909109
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1465977647
Short name T480
Test name
Test status
Simulation time 27574493 ps
CPU time 0.81 seconds
Started Jun 22 04:25:54 PM PDT 24
Finished Jun 22 04:25:55 PM PDT 24
Peak memory 194936 kb
Host smart-9cd2a47c-ba85-4d9e-aec3-2388b603ec95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465977647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1465977647
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2798773266
Short name T313
Test name
Test status
Simulation time 47755035 ps
CPU time 1.28 seconds
Started Jun 22 04:25:14 PM PDT 24
Finished Jun 22 04:25:16 PM PDT 24
Peak memory 195380 kb
Host smart-b01b407e-a685-4e90-a9fc-e49aba0c2c96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798773266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2798773266
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2291633921
Short name T700
Test name
Test status
Simulation time 16485977691 ps
CPU time 85.05 seconds
Started Jun 22 04:25:37 PM PDT 24
Finished Jun 22 04:27:03 PM PDT 24
Peak memory 197800 kb
Host smart-c778c184-5c6c-41a9-8b99-bae493351fc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291633921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2291633921
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1846278163
Short name T680
Test name
Test status
Simulation time 164995420116 ps
CPU time 995.26 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:42:02 PM PDT 24
Peak memory 197960 kb
Host smart-1df2b55e-0c17-4252-a715-59f8ef0a98c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1846278163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1846278163
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2504495187
Short name T165
Test name
Test status
Simulation time 53532690 ps
CPU time 0.58 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:24 PM PDT 24
Peak memory 193808 kb
Host smart-29d8cb10-bb38-447b-a846-cbe0b0314971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504495187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2504495187
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.4138952399
Short name T132
Test name
Test status
Simulation time 192693132 ps
CPU time 0.91 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 195692 kb
Host smart-25b6f79c-dbac-4f1e-9722-342bf4878964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138952399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.4138952399
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2827657140
Short name T585
Test name
Test status
Simulation time 839371755 ps
CPU time 6.15 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 196668 kb
Host smart-dcde42e3-ffa0-4353-9773-80a2d45ce5ea
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827657140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2827657140
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2162108222
Short name T284
Test name
Test status
Simulation time 149584917 ps
CPU time 0.74 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195572 kb
Host smart-15be5a6c-f3ce-41eb-a69a-06237a323050
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162108222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2162108222
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3258974424
Short name T104
Test name
Test status
Simulation time 51872941 ps
CPU time 1.36 seconds
Started Jun 22 04:25:23 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 196772 kb
Host smart-df7c883b-f271-40dd-9406-e6c73d0daeaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258974424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3258974424
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2615949711
Short name T663
Test name
Test status
Simulation time 77963462 ps
CPU time 2.27 seconds
Started Jun 22 04:25:58 PM PDT 24
Finished Jun 22 04:26:01 PM PDT 24
Peak memory 197912 kb
Host smart-7f00c2cf-e163-48a3-a47d-ce847eaef249
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615949711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2615949711
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.4186665163
Short name T645
Test name
Test status
Simulation time 245861659 ps
CPU time 1.65 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 195928 kb
Host smart-711a166f-444c-44ab-acdc-b524fe67a7ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186665163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.4186665163
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.2941657262
Short name T178
Test name
Test status
Simulation time 22233771 ps
CPU time 0.77 seconds
Started Jun 22 04:25:15 PM PDT 24
Finished Jun 22 04:25:16 PM PDT 24
Peak memory 195276 kb
Host smart-e58734c8-2bc2-468c-af80-30575ef83bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941657262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.2941657262
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.2994131341
Short name T476
Test name
Test status
Simulation time 25205836 ps
CPU time 0.75 seconds
Started Jun 22 04:25:24 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 195812 kb
Host smart-a5213468-1b8c-435b-b984-4e0f884b2080
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994131341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.2994131341
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1393244415
Short name T692
Test name
Test status
Simulation time 207100911 ps
CPU time 1.41 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 197692 kb
Host smart-e35cfb03-dbba-4b4f-b9ac-b86bfc7a506c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393244415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1393244415
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2578050757
Short name T125
Test name
Test status
Simulation time 252914172 ps
CPU time 0.87 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 196268 kb
Host smart-cfe749eb-4a95-41e9-80ca-9217c1f80a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578050757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2578050757
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2816164626
Short name T443
Test name
Test status
Simulation time 49393642 ps
CPU time 0.99 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 195316 kb
Host smart-6c9cbbb9-5b07-41df-951d-b6a8e9cad0e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816164626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2816164626
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.2632154915
Short name T479
Test name
Test status
Simulation time 64597119305 ps
CPU time 191.79 seconds
Started Jun 22 04:25:23 PM PDT 24
Finished Jun 22 04:28:40 PM PDT 24
Peak memory 197912 kb
Host smart-2a78a54c-0565-45cf-bb58-e5e539aa58fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632154915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.2632154915
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.3553638510
Short name T673
Test name
Test status
Simulation time 15191351 ps
CPU time 0.55 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 194396 kb
Host smart-0aadcaa7-6f39-435c-81c6-01d5b0c5d280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553638510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.3553638510
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.357400747
Short name T446
Test name
Test status
Simulation time 312287565 ps
CPU time 0.93 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:22 PM PDT 24
Peak memory 195776 kb
Host smart-75335c29-cf60-4dca-b867-1a758dae8a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357400747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.357400747
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2941356458
Short name T52
Test name
Test status
Simulation time 397047563 ps
CPU time 13.89 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:40 PM PDT 24
Peak memory 196636 kb
Host smart-c99e668b-3d33-4206-b67a-316fd2e472c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941356458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2941356458
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3485195503
Short name T633
Test name
Test status
Simulation time 40620958 ps
CPU time 0.64 seconds
Started Jun 22 04:25:17 PM PDT 24
Finished Jun 22 04:25:21 PM PDT 24
Peak memory 194260 kb
Host smart-c7d93863-525b-4f13-a491-c92e7ecf8424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485195503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3485195503
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.353381735
Short name T219
Test name
Test status
Simulation time 89060340 ps
CPU time 1.16 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 195576 kb
Host smart-202392ad-0266-41c6-a595-1d99ad84950a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353381735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.353381735
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3267479936
Short name T330
Test name
Test status
Simulation time 89483981 ps
CPU time 3.91 seconds
Started Jun 22 04:25:54 PM PDT 24
Finished Jun 22 04:25:58 PM PDT 24
Peak memory 197932 kb
Host smart-2bc635c2-26fc-44bc-b6e8-ae9271717b76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267479936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3267479936
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3012520692
Short name T464
Test name
Test status
Simulation time 94556309 ps
CPU time 1.85 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195708 kb
Host smart-688f66b9-9a8c-40ed-86cf-2ea3072b82a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012520692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3012520692
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1157290647
Short name T218
Test name
Test status
Simulation time 119285769 ps
CPU time 0.83 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 196208 kb
Host smart-974b5621-6e38-4064-8891-f876c66f1c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157290647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1157290647
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3762777580
Short name T254
Test name
Test status
Simulation time 58962448 ps
CPU time 1.15 seconds
Started Jun 22 04:25:23 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 196340 kb
Host smart-16ffbb90-7f52-4dd2-8baa-1726e52f3002
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762777580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3762777580
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1207622663
Short name T686
Test name
Test status
Simulation time 93726360 ps
CPU time 2.01 seconds
Started Jun 22 04:25:47 PM PDT 24
Finished Jun 22 04:25:50 PM PDT 24
Peak memory 197328 kb
Host smart-34429204-00e9-41f2-8506-63b00521083f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207622663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1207622663
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3288785206
Short name T698
Test name
Test status
Simulation time 103529191 ps
CPU time 0.93 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195468 kb
Host smart-710d8794-7294-4a47-8e98-b662f4fa4f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288785206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3288785206
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2202953267
Short name T373
Test name
Test status
Simulation time 180068985 ps
CPU time 1.13 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 195468 kb
Host smart-7ad45658-f7f5-481a-b21a-db6a94693e80
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202953267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2202953267
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2139979375
Short name T706
Test name
Test status
Simulation time 10127681904 ps
CPU time 140.87 seconds
Started Jun 22 04:25:46 PM PDT 24
Finished Jun 22 04:28:08 PM PDT 24
Peak memory 197880 kb
Host smart-5574a035-a752-4f96-904b-6905534971c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139979375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2139979375
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.893440627
Short name T58
Test name
Test status
Simulation time 77763133935 ps
CPU time 552.94 seconds
Started Jun 22 04:25:26 PM PDT 24
Finished Jun 22 04:34:42 PM PDT 24
Peak memory 206544 kb
Host smart-357c47e9-ce62-4286-b1c2-fe62bac3a86d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=893440627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.893440627
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1979704353
Short name T208
Test name
Test status
Simulation time 15779859 ps
CPU time 0.55 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 194300 kb
Host smart-bb212608-42d7-4596-a079-9d563e81bb63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979704353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1979704353
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1468916293
Short name T180
Test name
Test status
Simulation time 24128863 ps
CPU time 0.66 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 194012 kb
Host smart-6c9ab8ec-784c-4a98-8e79-f6be8f6d0fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468916293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1468916293
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.271059316
Short name T123
Test name
Test status
Simulation time 1691312352 ps
CPU time 13 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:36 PM PDT 24
Peak memory 198276 kb
Host smart-03957af6-3c97-48d2-b748-205d1b668667
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271059316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.271059316
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.811313254
Short name T466
Test name
Test status
Simulation time 84987692 ps
CPU time 0.88 seconds
Started Jun 22 04:25:50 PM PDT 24
Finished Jun 22 04:25:52 PM PDT 24
Peak memory 197620 kb
Host smart-e838def1-8a3b-4c6c-a77a-b5cb803ca850
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811313254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.811313254
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2313187214
Short name T629
Test name
Test status
Simulation time 49223351 ps
CPU time 0.69 seconds
Started Jun 22 04:25:49 PM PDT 24
Finished Jun 22 04:25:51 PM PDT 24
Peak memory 194548 kb
Host smart-9d6712b4-bbc7-42ca-b207-9a6d8ba48e84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313187214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2313187214
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.674813472
Short name T699
Test name
Test status
Simulation time 174523750 ps
CPU time 1.89 seconds
Started Jun 22 04:25:48 PM PDT 24
Finished Jun 22 04:25:51 PM PDT 24
Peak memory 198292 kb
Host smart-d71044fc-30db-4f87-9147-eccb63c8e464
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674813472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.674813472
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.466152453
Short name T201
Test name
Test status
Simulation time 312685665 ps
CPU time 1.85 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 196624 kb
Host smart-e3cf6306-e293-4594-b9ac-d9d4a62fef3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466152453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
466152453
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.738598690
Short name T242
Test name
Test status
Simulation time 34240978 ps
CPU time 1.14 seconds
Started Jun 22 04:25:37 PM PDT 24
Finished Jun 22 04:25:38 PM PDT 24
Peak memory 196884 kb
Host smart-8a008637-ee1d-4c33-9c59-55bc70de0255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738598690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.738598690
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1192758317
Short name T592
Test name
Test status
Simulation time 98567206 ps
CPU time 0.7 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 195820 kb
Host smart-eb9ad27b-191b-4fc0-a7d8-ee26ec7c0233
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192758317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1192758317
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.1696565254
Short name T576
Test name
Test status
Simulation time 297778133 ps
CPU time 3.78 seconds
Started Jun 22 04:25:37 PM PDT 24
Finished Jun 22 04:25:41 PM PDT 24
Peak memory 198268 kb
Host smart-676e1a82-8b30-49e5-8aca-25b32b7619d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696565254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.1696565254
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2538555712
Short name T559
Test name
Test status
Simulation time 69389906 ps
CPU time 1.06 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195508 kb
Host smart-3eda27e3-eebb-4152-af02-c05230897887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538555712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2538555712
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.2437101345
Short name T372
Test name
Test status
Simulation time 114313973 ps
CPU time 1 seconds
Started Jun 22 04:25:23 PM PDT 24
Finished Jun 22 04:25:29 PM PDT 24
Peak memory 196140 kb
Host smart-3ff1cd41-ff97-48e9-bb7a-f78b7558efd8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437101345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.2437101345
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.2969137087
Short name T483
Test name
Test status
Simulation time 10390520851 ps
CPU time 128.33 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:27:36 PM PDT 24
Peak memory 198052 kb
Host smart-f060009c-2e19-4466-b103-ddceb255225a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969137087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.2969137087
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.580395830
Short name T421
Test name
Test status
Simulation time 391587657990 ps
CPU time 985.91 seconds
Started Jun 22 04:25:50 PM PDT 24
Finished Jun 22 04:42:17 PM PDT 24
Peak memory 197980 kb
Host smart-fde529c6-1ad1-4026-ba09-6b6c2b056bf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=580395830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.580395830
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.977415797
Short name T484
Test name
Test status
Simulation time 136924074 ps
CPU time 0.57 seconds
Started Jun 22 04:25:35 PM PDT 24
Finished Jun 22 04:25:36 PM PDT 24
Peak memory 194060 kb
Host smart-01b078ca-d7c7-4e21-b1e9-026bc4a00c6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977415797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.977415797
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.830640610
Short name T164
Test name
Test status
Simulation time 38772436 ps
CPU time 0.69 seconds
Started Jun 22 04:25:22 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 194620 kb
Host smart-a8d4e166-5075-4e95-a473-0df11bc00bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830640610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.830640610
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.913929366
Short name T609
Test name
Test status
Simulation time 703032410 ps
CPU time 18.03 seconds
Started Jun 22 04:25:50 PM PDT 24
Finished Jun 22 04:26:09 PM PDT 24
Peak memory 195084 kb
Host smart-0d110c62-6d02-4b35-8ebb-c66ee00d079a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913929366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stres
s.913929366
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3280398404
Short name T458
Test name
Test status
Simulation time 53715868 ps
CPU time 0.86 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 196360 kb
Host smart-6d4e2bb3-8b80-4489-a6a2-690d9337fbeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280398404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3280398404
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.1461919059
Short name T385
Test name
Test status
Simulation time 121203955 ps
CPU time 1.04 seconds
Started Jun 22 04:25:18 PM PDT 24
Finished Jun 22 04:25:25 PM PDT 24
Peak memory 195796 kb
Host smart-cf8cf0c3-151d-4c2a-bd29-cabc2bdd6022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461919059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.1461919059
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3963059947
Short name T211
Test name
Test status
Simulation time 98786223 ps
CPU time 2.88 seconds
Started Jun 22 04:25:37 PM PDT 24
Finished Jun 22 04:25:40 PM PDT 24
Peak memory 197908 kb
Host smart-fd559c7a-75da-42b1-a230-d402261b0cdf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963059947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3963059947
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2235965670
Short name T191
Test name
Test status
Simulation time 242283209 ps
CPU time 2.35 seconds
Started Jun 22 04:25:43 PM PDT 24
Finished Jun 22 04:25:46 PM PDT 24
Peak memory 196712 kb
Host smart-1b267e64-6e55-47f5-a1b8-44d2b6320d68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235965670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2235965670
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.498381193
Short name T110
Test name
Test status
Simulation time 48618674 ps
CPU time 1.09 seconds
Started Jun 22 04:25:47 PM PDT 24
Finished Jun 22 04:25:49 PM PDT 24
Peak memory 195696 kb
Host smart-44bbc44b-fe6e-4a3c-93af-342fa2154d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498381193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.498381193
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.519288332
Short name T345
Test name
Test status
Simulation time 86876683 ps
CPU time 0.76 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 195828 kb
Host smart-3c33aff0-b053-41d3-a738-da1fef8aa881
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519288332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.519288332
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.161607193
Short name T574
Test name
Test status
Simulation time 1780112203 ps
CPU time 5.05 seconds
Started Jun 22 04:25:23 PM PDT 24
Finished Jun 22 04:25:33 PM PDT 24
Peak memory 197784 kb
Host smart-3011ff96-3d2a-4cff-ab28-8448b2e8484d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161607193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.161607193
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.4124994173
Short name T320
Test name
Test status
Simulation time 97380407 ps
CPU time 0.95 seconds
Started Jun 22 04:25:35 PM PDT 24
Finished Jun 22 04:25:36 PM PDT 24
Peak memory 195612 kb
Host smart-b9470baa-255b-4b6e-bbcb-6b4706af6529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124994173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.4124994173
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3609129765
Short name T420
Test name
Test status
Simulation time 59457518 ps
CPU time 1.08 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:26 PM PDT 24
Peak memory 196212 kb
Host smart-36b27cb7-93fc-4993-847b-7fb60dcdba5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609129765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3609129765
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.276965420
Short name T118
Test name
Test status
Simulation time 39742518669 ps
CPU time 137.62 seconds
Started Jun 22 04:25:24 PM PDT 24
Finished Jun 22 04:27:46 PM PDT 24
Peak memory 197932 kb
Host smart-c4410b5b-4386-49d7-b111-30985434938f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276965420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.276965420
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2306409325
Short name T449
Test name
Test status
Simulation time 64626166949 ps
CPU time 1688.78 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:53:36 PM PDT 24
Peak memory 198344 kb
Host smart-7f116fb8-35db-4ac7-9f0b-eabb1ba7eab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2306409325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2306409325
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3997100799
Short name T243
Test name
Test status
Simulation time 21202304 ps
CPU time 0.55 seconds
Started Jun 22 04:25:38 PM PDT 24
Finished Jun 22 04:25:39 PM PDT 24
Peak memory 194284 kb
Host smart-d929251d-0df1-49f5-acf4-cf3e9b2951b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997100799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3997100799
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1398710575
Short name T632
Test name
Test status
Simulation time 23957264 ps
CPU time 0.86 seconds
Started Jun 22 04:25:21 PM PDT 24
Finished Jun 22 04:25:28 PM PDT 24
Peak memory 195344 kb
Host smart-7660264b-246f-4622-b7d7-dbbc9bfc7658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398710575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1398710575
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.4285403526
Short name T235
Test name
Test status
Simulation time 3266888381 ps
CPU time 27.27 seconds
Started Jun 22 04:25:48 PM PDT 24
Finished Jun 22 04:26:16 PM PDT 24
Peak memory 196372 kb
Host smart-fe98e1c3-5fee-4efc-9158-cb71294db47e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285403526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.4285403526
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2387666234
Short name T19
Test name
Test status
Simulation time 85251281 ps
CPU time 0.99 seconds
Started Jun 22 04:25:26 PM PDT 24
Finished Jun 22 04:25:30 PM PDT 24
Peak memory 196268 kb
Host smart-0e349df1-395f-4fc0-842f-e75837fb0aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387666234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2387666234
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.3052519828
Short name T245
Test name
Test status
Simulation time 418534466 ps
CPU time 1.11 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 195568 kb
Host smart-8def088d-bcba-4f8b-9427-c94ac41831ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052519828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.3052519828
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3858065996
Short name T505
Test name
Test status
Simulation time 49837370 ps
CPU time 1.93 seconds
Started Jun 22 04:25:43 PM PDT 24
Finished Jun 22 04:25:46 PM PDT 24
Peak memory 197968 kb
Host smart-b2e4d3a2-e09e-4a8a-a142-c8895b936b94
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858065996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3858065996
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.996534112
Short name T661
Test name
Test status
Simulation time 165212807 ps
CPU time 1.4 seconds
Started Jun 22 04:25:29 PM PDT 24
Finished Jun 22 04:25:31 PM PDT 24
Peak memory 195708 kb
Host smart-5e662a1f-c683-421c-9959-c5b17ae03c80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996534112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
996534112
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.19133780
Short name T530
Test name
Test status
Simulation time 135510347 ps
CPU time 1.31 seconds
Started Jun 22 04:25:16 PM PDT 24
Finished Jun 22 04:25:19 PM PDT 24
Peak memory 197920 kb
Host smart-d7f4da32-ff52-43a1-b1d6-0e23af4aa154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19133780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.19133780
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.4141518589
Short name T304
Test name
Test status
Simulation time 55466898 ps
CPU time 0.73 seconds
Started Jun 22 04:25:20 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 196020 kb
Host smart-67e01a44-8a89-4faa-b1e2-704944443964
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141518589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.4141518589
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2129706020
Short name T240
Test name
Test status
Simulation time 169174859 ps
CPU time 3.49 seconds
Started Jun 22 04:25:19 PM PDT 24
Finished Jun 22 04:25:27 PM PDT 24
Peak memory 197728 kb
Host smart-fe6480bc-d12e-4d94-ae61-a87a8334aa7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129706020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2129706020
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1736516331
Short name T639
Test name
Test status
Simulation time 81329351 ps
CPU time 1.37 seconds
Started Jun 22 04:25:25 PM PDT 24
Finished Jun 22 04:25:30 PM PDT 24
Peak memory 196660 kb
Host smart-fad7da54-035c-4020-8c00-cab588b39e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736516331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1736516331
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.1490501108
Short name T160
Test name
Test status
Simulation time 136073764 ps
CPU time 1.05 seconds
Started Jun 22 04:25:32 PM PDT 24
Finished Jun 22 04:25:34 PM PDT 24
Peak memory 195628 kb
Host smart-b4fadda7-1fab-4e27-bf0d-881683fc9e47
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490501108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.1490501108
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.1355847120
Short name T249
Test name
Test status
Simulation time 46697325859 ps
CPU time 144.56 seconds
Started Jun 22 04:25:25 PM PDT 24
Finished Jun 22 04:27:53 PM PDT 24
Peak memory 197908 kb
Host smart-041d8e63-141e-478b-a21a-c96890dde1fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355847120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.1355847120
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.577745567
Short name T491
Test name
Test status
Simulation time 391007445673 ps
CPU time 2291.18 seconds
Started Jun 22 04:25:50 PM PDT 24
Finished Jun 22 05:04:02 PM PDT 24
Peak memory 197836 kb
Host smart-e3e2f797-357a-440b-a0a4-b7e92ab01e9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=577745567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.577745567
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.615901819
Short name T678
Test name
Test status
Simulation time 70794842 ps
CPU time 0.58 seconds
Started Jun 22 04:24:04 PM PDT 24
Finished Jun 22 04:24:05 PM PDT 24
Peak memory 193820 kb
Host smart-bb3b7464-d78b-4b1a-af5e-7b8a9ebd2eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615901819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.615901819
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.4168358473
Short name T671
Test name
Test status
Simulation time 57211738 ps
CPU time 0.87 seconds
Started Jun 22 04:23:52 PM PDT 24
Finished Jun 22 04:23:53 PM PDT 24
Peak memory 196188 kb
Host smart-a9bffa69-c81f-4947-9f30-be9d2c32ed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168358473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.4168358473
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3013739040
Short name T518
Test name
Test status
Simulation time 74742049 ps
CPU time 3.58 seconds
Started Jun 22 04:23:51 PM PDT 24
Finished Jun 22 04:23:55 PM PDT 24
Peak memory 195180 kb
Host smart-d4359323-56e2-4bdd-9901-cd0e76c0eca5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013739040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3013739040
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2735956413
Short name T641
Test name
Test status
Simulation time 22249240 ps
CPU time 0.69 seconds
Started Jun 22 04:24:04 PM PDT 24
Finished Jun 22 04:24:06 PM PDT 24
Peak memory 194324 kb
Host smart-8cc44445-ce1e-4ef8-9436-5fd9bd865bee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735956413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2735956413
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1546343142
Short name T400
Test name
Test status
Simulation time 25435562 ps
CPU time 0.79 seconds
Started Jun 22 04:23:50 PM PDT 24
Finished Jun 22 04:23:51 PM PDT 24
Peak memory 195340 kb
Host smart-79947e8c-f59e-4090-9afc-6f020d5a5c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546343142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1546343142
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3258571649
Short name T404
Test name
Test status
Simulation time 94711029 ps
CPU time 1.93 seconds
Started Jun 22 04:24:01 PM PDT 24
Finished Jun 22 04:24:04 PM PDT 24
Peak memory 196820 kb
Host smart-3b465c5b-eb76-4bf0-8139-b747695e59b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258571649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3258571649
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.122620210
Short name T331
Test name
Test status
Simulation time 469387763 ps
CPU time 3.51 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 195652 kb
Host smart-36e36b20-33f3-4c5e-917b-c9d3eabc8f5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122620210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.122620210
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1705302441
Short name T338
Test name
Test status
Simulation time 66366185 ps
CPU time 0.77 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:23 PM PDT 24
Peak memory 195268 kb
Host smart-9a6bf163-a834-4c88-a68d-9d4e0e9f9bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705302441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1705302441
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1896510613
Short name T182
Test name
Test status
Simulation time 104209333 ps
CPU time 0.77 seconds
Started Jun 22 04:24:06 PM PDT 24
Finished Jun 22 04:24:08 PM PDT 24
Peak memory 195124 kb
Host smart-acc402e9-3ad5-4224-934a-64b0ad980e66
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896510613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1896510613
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3337350574
Short name T429
Test name
Test status
Simulation time 210104198 ps
CPU time 4.59 seconds
Started Jun 22 04:24:02 PM PDT 24
Finished Jun 22 04:24:07 PM PDT 24
Peak memory 196836 kb
Host smart-87338af6-743e-4f53-a9f4-ae74ae44d529
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337350574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3337350574
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3094831656
Short name T560
Test name
Test status
Simulation time 163376929 ps
CPU time 0.92 seconds
Started Jun 22 04:23:51 PM PDT 24
Finished Jun 22 04:23:52 PM PDT 24
Peak memory 195572 kb
Host smart-9ec5e219-fa0e-426b-b47f-b3f929a466e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094831656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3094831656
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3877910345
Short name T315
Test name
Test status
Simulation time 241084562 ps
CPU time 1.1 seconds
Started Jun 22 04:24:02 PM PDT 24
Finished Jun 22 04:24:04 PM PDT 24
Peak memory 195572 kb
Host smart-ddc29523-151a-4af6-b4df-39388b62ed13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877910345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3877910345
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.17489789
Short name T526
Test name
Test status
Simulation time 15390631988 ps
CPU time 105.52 seconds
Started Jun 22 04:24:01 PM PDT 24
Finished Jun 22 04:25:47 PM PDT 24
Peak memory 197916 kb
Host smart-40cf05e1-9814-4ba1-884e-7c72c8d02046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17489789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpi
o_stress_all.17489789
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.3036726012
Short name T465
Test name
Test status
Simulation time 316991461132 ps
CPU time 1689.47 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:52:22 PM PDT 24
Peak memory 197976 kb
Host smart-725a1b21-a1ac-4902-9f14-decc84b43ea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3036726012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.3036726012
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.226929215
Short name T396
Test name
Test status
Simulation time 13261361 ps
CPU time 0.59 seconds
Started Jun 22 04:23:58 PM PDT 24
Finished Jun 22 04:23:59 PM PDT 24
Peak memory 193584 kb
Host smart-93c5dca4-2932-4e7d-99f1-f032015c02b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226929215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.226929215
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2189254387
Short name T150
Test name
Test status
Simulation time 43123276 ps
CPU time 0.72 seconds
Started Jun 22 04:24:06 PM PDT 24
Finished Jun 22 04:24:08 PM PDT 24
Peak memory 194388 kb
Host smart-1335e181-94a3-463b-9421-57c96bed358c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189254387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2189254387
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.4048830163
Short name T205
Test name
Test status
Simulation time 1044332028 ps
CPU time 7.48 seconds
Started Jun 22 04:24:12 PM PDT 24
Finished Jun 22 04:24:21 PM PDT 24
Peak memory 196228 kb
Host smart-89a3e412-8ed7-4d66-82bf-e6ef558ebd61
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048830163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.4048830163
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.557415019
Short name T422
Test name
Test status
Simulation time 58084985 ps
CPU time 0.94 seconds
Started Jun 22 04:24:05 PM PDT 24
Finished Jun 22 04:24:07 PM PDT 24
Peak memory 197620 kb
Host smart-d06983f4-9edd-462d-9d2e-277c8926c112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557415019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.557415019
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1920270184
Short name T95
Test name
Test status
Simulation time 136221973 ps
CPU time 1.09 seconds
Started Jun 22 04:23:56 PM PDT 24
Finished Jun 22 04:23:58 PM PDT 24
Peak memory 195864 kb
Host smart-cdf012c5-91c2-48c8-8ba2-1d7c80456050
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920270184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1920270184
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.4111761617
Short name T515
Test name
Test status
Simulation time 29068566 ps
CPU time 1.2 seconds
Started Jun 22 04:24:10 PM PDT 24
Finished Jun 22 04:24:12 PM PDT 24
Peak memory 196120 kb
Host smart-b360ebe8-87e9-4771-87f5-fe91bb52a8ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111761617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.4111761617
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2354899533
Short name T394
Test name
Test status
Simulation time 24911264 ps
CPU time 0.93 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 195468 kb
Host smart-f4b479e8-4384-456a-ba0e-fa4c81aed094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354899533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2354899533
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3073068810
Short name T522
Test name
Test status
Simulation time 139732179 ps
CPU time 0.86 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 196584 kb
Host smart-827b72cf-9d1a-4a0e-b9f6-3b1a3126bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073068810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3073068810
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2203683498
Short name T613
Test name
Test status
Simulation time 103029206 ps
CPU time 1.02 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 195952 kb
Host smart-c1c767d6-1725-4e26-b029-742589cf84fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203683498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2203683498
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.803150461
Short name T176
Test name
Test status
Simulation time 332840346 ps
CPU time 3.75 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 197764 kb
Host smart-021259a3-0bf2-490d-b1da-19760fc3cb0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803150461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.803150461
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3170314019
Short name T248
Test name
Test status
Simulation time 297121033 ps
CPU time 0.95 seconds
Started Jun 22 04:24:05 PM PDT 24
Finished Jun 22 04:24:06 PM PDT 24
Peak memory 196744 kb
Host smart-46f61adf-09e4-47fa-b74f-f6e1e8ee587e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170314019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3170314019
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.417586652
Short name T46
Test name
Test status
Simulation time 24195273 ps
CPU time 0.77 seconds
Started Jun 22 04:24:16 PM PDT 24
Finished Jun 22 04:24:17 PM PDT 24
Peak memory 195068 kb
Host smart-c5779300-eca0-4116-b731-b3f9890f5148
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417586652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.417586652
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2415377178
Short name T423
Test name
Test status
Simulation time 17077580079 ps
CPU time 104.82 seconds
Started Jun 22 04:23:56 PM PDT 24
Finished Jun 22 04:25:42 PM PDT 24
Peak memory 197140 kb
Host smart-6b8721cd-1838-4b59-a5fe-d108e5a9c10f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415377178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2415377178
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.707444946
Short name T56
Test name
Test status
Simulation time 229505219926 ps
CPU time 1272.06 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:45:22 PM PDT 24
Peak memory 197160 kb
Host smart-6583168a-2be4-40af-abd7-f083f6df6c87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=707444946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.707444946
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3769176004
Short name T357
Test name
Test status
Simulation time 31532967 ps
CPU time 0.55 seconds
Started Jun 22 04:24:16 PM PDT 24
Finished Jun 22 04:24:17 PM PDT 24
Peak memory 193600 kb
Host smart-488fdf92-284b-4a22-ad44-3068f02c8a4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769176004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3769176004
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3727289464
Short name T133
Test name
Test status
Simulation time 57600551 ps
CPU time 0.86 seconds
Started Jun 22 04:23:58 PM PDT 24
Finished Jun 22 04:23:59 PM PDT 24
Peak memory 195756 kb
Host smart-3fdb0ca3-2eef-414c-807c-4e3d6a55e58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727289464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3727289464
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1554135576
Short name T534
Test name
Test status
Simulation time 254787164 ps
CPU time 12.71 seconds
Started Jun 22 04:24:01 PM PDT 24
Finished Jun 22 04:24:15 PM PDT 24
Peak memory 195228 kb
Host smart-132ad43c-020e-4eb6-b304-02249f51431b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554135576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1554135576
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2257869202
Short name T293
Test name
Test status
Simulation time 97606465 ps
CPU time 1.24 seconds
Started Jun 22 04:24:01 PM PDT 24
Finished Jun 22 04:24:03 PM PDT 24
Peak memory 196392 kb
Host smart-06d87fa3-e91d-49d4-9d8e-f73dbd31dc05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257869202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2257869202
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.3791464512
Short name T652
Test name
Test status
Simulation time 44901513 ps
CPU time 1.1 seconds
Started Jun 22 04:24:13 PM PDT 24
Finished Jun 22 04:24:15 PM PDT 24
Peak memory 196368 kb
Host smart-d65cf557-e751-47e0-83b5-3a2e6ad7e22d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791464512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.3791464512
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.170439154
Short name T25
Test name
Test status
Simulation time 94325246 ps
CPU time 1.89 seconds
Started Jun 22 04:24:21 PM PDT 24
Finished Jun 22 04:24:23 PM PDT 24
Peak memory 197848 kb
Host smart-a26de8de-2f4d-4ed0-a752-c55274f8e5ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170439154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.170439154
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2024426400
Short name T619
Test name
Test status
Simulation time 539111086 ps
CPU time 2.15 seconds
Started Jun 22 04:23:56 PM PDT 24
Finished Jun 22 04:23:58 PM PDT 24
Peak memory 196992 kb
Host smart-69f7cac7-61bb-46d8-b2b4-db02a3d7c7e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024426400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2024426400
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.782318122
Short name T468
Test name
Test status
Simulation time 23122712 ps
CPU time 0.89 seconds
Started Jun 22 04:24:23 PM PDT 24
Finished Jun 22 04:24:26 PM PDT 24
Peak memory 197116 kb
Host smart-cf259c2e-237f-4f45-807a-b15885d08fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782318122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.782318122
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3691923167
Short name T105
Test name
Test status
Simulation time 60631574 ps
CPU time 0.76 seconds
Started Jun 22 04:24:01 PM PDT 24
Finished Jun 22 04:24:02 PM PDT 24
Peak memory 194160 kb
Host smart-bf0da792-0c37-4107-9605-5d2787c849b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691923167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3691923167
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3260783807
Short name T415
Test name
Test status
Simulation time 487357053 ps
CPU time 5.49 seconds
Started Jun 22 04:24:13 PM PDT 24
Finished Jun 22 04:24:19 PM PDT 24
Peak memory 198232 kb
Host smart-237725a7-8513-48d6-adc7-a522491fea0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260783807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3260783807
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1490937241
Short name T503
Test name
Test status
Simulation time 65215243 ps
CPU time 1.05 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:24:16 PM PDT 24
Peak memory 196240 kb
Host smart-21b96d0c-322f-4829-9145-bdd62d8517c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490937241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1490937241
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3462855175
Short name T583
Test name
Test status
Simulation time 376140670 ps
CPU time 1.53 seconds
Started Jun 22 04:23:59 PM PDT 24
Finished Jun 22 04:24:01 PM PDT 24
Peak memory 195668 kb
Host smart-4411571e-8a76-4d4f-95fc-eaed7f56e7f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462855175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3462855175
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.914898660
Short name T442
Test name
Test status
Simulation time 5850454496 ps
CPU time 76.83 seconds
Started Jun 22 04:24:05 PM PDT 24
Finished Jun 22 04:25:23 PM PDT 24
Peak memory 197916 kb
Host smart-78075166-afb6-4012-aae8-9b42c395a255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914898660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.914898660
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1841534309
Short name T229
Test name
Test status
Simulation time 43776713 ps
CPU time 0.55 seconds
Started Jun 22 04:24:10 PM PDT 24
Finished Jun 22 04:24:12 PM PDT 24
Peak memory 193600 kb
Host smart-8004e8c4-d6b7-4c33-9965-a11624df03d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841534309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1841534309
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3697361754
Short name T497
Test name
Test status
Simulation time 129911108 ps
CPU time 0.9 seconds
Started Jun 22 04:24:00 PM PDT 24
Finished Jun 22 04:24:02 PM PDT 24
Peak memory 196764 kb
Host smart-a6177fb6-6634-4f3d-8ab0-3e52b44e022d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697361754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3697361754
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2733665045
Short name T204
Test name
Test status
Simulation time 1112019151 ps
CPU time 20.27 seconds
Started Jun 22 04:23:57 PM PDT 24
Finished Jun 22 04:24:17 PM PDT 24
Peak memory 196708 kb
Host smart-a051c507-6651-4f18-91b1-1f713b14b2f5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733665045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2733665045
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3718416215
Short name T643
Test name
Test status
Simulation time 62503468 ps
CPU time 0.76 seconds
Started Jun 22 04:24:06 PM PDT 24
Finished Jun 22 04:24:07 PM PDT 24
Peak memory 195640 kb
Host smart-151fbe0f-1d2b-4d47-b781-13b969dfa04b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718416215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3718416215
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1692157644
Short name T444
Test name
Test status
Simulation time 54527392 ps
CPU time 0.92 seconds
Started Jun 22 04:24:10 PM PDT 24
Finished Jun 22 04:24:12 PM PDT 24
Peak memory 195624 kb
Host smart-bfd7bf93-c727-4db5-8981-443a48fa65a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692157644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1692157644
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.3994281598
Short name T273
Test name
Test status
Simulation time 41961787 ps
CPU time 1.82 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 196492 kb
Host smart-a1be752a-c7b5-4cd0-9f8f-947921071b07
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994281598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.3994281598
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1899128732
Short name T575
Test name
Test status
Simulation time 61539208 ps
CPU time 1.48 seconds
Started Jun 22 04:24:08 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 195004 kb
Host smart-35f94d9a-208c-4a31-b7f2-2ecc86dae48f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899128732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1899128732
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2755163077
Short name T550
Test name
Test status
Simulation time 94411326 ps
CPU time 0.98 seconds
Started Jun 22 04:24:00 PM PDT 24
Finished Jun 22 04:24:01 PM PDT 24
Peak memory 194992 kb
Host smart-68833704-bef0-4114-b795-684dbc64b2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755163077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2755163077
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1527841207
Short name T668
Test name
Test status
Simulation time 42205922 ps
CPU time 1.01 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 195896 kb
Host smart-9f74ff47-f090-4bb7-b781-6ca47aa612e1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527841207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1527841207
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.4261785207
Short name T103
Test name
Test status
Simulation time 1989606322 ps
CPU time 4.2 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:15 PM PDT 24
Peak memory 197768 kb
Host smart-18813249-afc2-429b-a81b-fa873ab944fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261785207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.4261785207
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3227740184
Short name T472
Test name
Test status
Simulation time 68216081 ps
CPU time 1.04 seconds
Started Jun 22 04:24:18 PM PDT 24
Finished Jun 22 04:24:20 PM PDT 24
Peak memory 195324 kb
Host smart-71b84d12-22c8-4e2c-a631-7d63300db2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227740184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3227740184
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3667227317
Short name T259
Test name
Test status
Simulation time 109457312 ps
CPU time 1.5 seconds
Started Jun 22 04:24:29 PM PDT 24
Finished Jun 22 04:24:33 PM PDT 24
Peak memory 196028 kb
Host smart-ff70669c-658d-4515-a8fd-3248b8f92b14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667227317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3667227317
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.389189694
Short name T434
Test name
Test status
Simulation time 4968693377 ps
CPU time 148.75 seconds
Started Jun 22 04:24:03 PM PDT 24
Finished Jun 22 04:26:33 PM PDT 24
Peak memory 197884 kb
Host smart-4d72b077-e224-4af7-86bf-2f11b60416d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389189694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.389189694
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2826170189
Short name T498
Test name
Test status
Simulation time 37649662 ps
CPU time 0.57 seconds
Started Jun 22 04:24:12 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 193600 kb
Host smart-cb3d2f48-bb31-47ef-87ac-6a8aade79d1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826170189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2826170189
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2242624548
Short name T295
Test name
Test status
Simulation time 40240742 ps
CPU time 0.61 seconds
Started Jun 22 04:24:12 PM PDT 24
Finished Jun 22 04:24:14 PM PDT 24
Peak memory 193816 kb
Host smart-bd15dfa6-4d29-4d37-b5cf-7460e0e18f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242624548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2242624548
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1577059526
Short name T233
Test name
Test status
Simulation time 866737934 ps
CPU time 11.93 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:22 PM PDT 24
Peak memory 196716 kb
Host smart-df9776a3-0a2c-4c0c-96d1-439dbd35cb87
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577059526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1577059526
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.4022126876
Short name T682
Test name
Test status
Simulation time 57522935 ps
CPU time 0.9 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 04:24:13 PM PDT 24
Peak memory 195696 kb
Host smart-7825346e-d1a1-4ecc-90a4-5313c4c15514
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022126876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.4022126876
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3791242849
Short name T61
Test name
Test status
Simulation time 54391701 ps
CPU time 1 seconds
Started Jun 22 04:24:03 PM PDT 24
Finished Jun 22 04:24:05 PM PDT 24
Peak memory 194784 kb
Host smart-0aeb4cc7-dc0a-4b80-9a72-07cc1ce5c106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791242849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3791242849
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1632314016
Short name T272
Test name
Test status
Simulation time 341644674 ps
CPU time 3.14 seconds
Started Jun 22 04:23:59 PM PDT 24
Finished Jun 22 04:24:02 PM PDT 24
Peak memory 198012 kb
Host smart-991128ba-3cad-412b-8f5c-290b193f1a06
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632314016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1632314016
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3071724097
Short name T549
Test name
Test status
Simulation time 234642237 ps
CPU time 1.74 seconds
Started Jun 22 04:24:12 PM PDT 24
Finished Jun 22 04:24:14 PM PDT 24
Peak memory 195940 kb
Host smart-095bad85-d1ee-4db1-b11f-cf1d1a2b515a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071724097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3071724097
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.387905321
Short name T96
Test name
Test status
Simulation time 19114166 ps
CPU time 0.79 seconds
Started Jun 22 04:24:05 PM PDT 24
Finished Jun 22 04:24:07 PM PDT 24
Peak memory 194968 kb
Host smart-6a4a37b5-142b-4301-afd1-8e25745c7d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387905321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.387905321
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.125725903
Short name T194
Test name
Test status
Simulation time 138121663 ps
CPU time 1.23 seconds
Started Jun 22 04:24:12 PM PDT 24
Finished Jun 22 04:24:14 PM PDT 24
Peak memory 196716 kb
Host smart-5d7364a4-f0ee-453d-a71f-4edbd1cc86e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125725903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.125725903
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.423778419
Short name T324
Test name
Test status
Simulation time 305901094 ps
CPU time 1.99 seconds
Started Jun 22 04:24:15 PM PDT 24
Finished Jun 22 04:24:18 PM PDT 24
Peak memory 197740 kb
Host smart-a61d1924-5794-4318-9023-2ff8eb08cd04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423778419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.423778419
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.484601947
Short name T490
Test name
Test status
Simulation time 52590079 ps
CPU time 1.1 seconds
Started Jun 22 04:24:01 PM PDT 24
Finished Jun 22 04:24:03 PM PDT 24
Peak memory 195852 kb
Host smart-5c732dc5-f6d6-489e-9d8a-26022e4cfecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484601947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.484601947
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3972764824
Short name T140
Test name
Test status
Simulation time 212893763 ps
CPU time 0.97 seconds
Started Jun 22 04:24:09 PM PDT 24
Finished Jun 22 04:24:11 PM PDT 24
Peak memory 196040 kb
Host smart-9e3528b7-eac6-4b2c-999c-67780377066e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972764824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3972764824
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.1906580178
Short name T94
Test name
Test status
Simulation time 21509687494 ps
CPU time 181.97 seconds
Started Jun 22 04:24:18 PM PDT 24
Finished Jun 22 04:27:21 PM PDT 24
Peak memory 197944 kb
Host smart-770a2963-0591-4d12-8a1e-8f561de0d1ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906580178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.1906580178
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3676931885
Short name T662
Test name
Test status
Simulation time 265312902365 ps
CPU time 2257.52 seconds
Started Jun 22 04:24:11 PM PDT 24
Finished Jun 22 05:01:50 PM PDT 24
Peak memory 197152 kb
Host smart-f4f15f02-fcd0-4a5c-b06c-3f33173886ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3676931885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3676931885
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1958302253
Short name T903
Test name
Test status
Simulation time 167607304 ps
CPU time 1.04 seconds
Started Jun 22 04:35:23 PM PDT 24
Finished Jun 22 04:35:25 PM PDT 24
Peak memory 196272 kb
Host smart-393e19ca-f413-45b7-8a7b-dfb9c48d5260
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1958302253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1958302253
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237838161
Short name T850
Test name
Test status
Simulation time 47495087 ps
CPU time 0.99 seconds
Started Jun 22 04:35:32 PM PDT 24
Finished Jun 22 04:35:33 PM PDT 24
Peak memory 197736 kb
Host smart-86ff53da-e922-42b9-a73a-d4124cd49d28
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237838161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2237838161
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1564672043
Short name T874
Test name
Test status
Simulation time 40816775 ps
CPU time 1.07 seconds
Started Jun 22 04:35:45 PM PDT 24
Finished Jun 22 04:35:47 PM PDT 24
Peak memory 195592 kb
Host smart-58d588ed-f930-456d-814a-b355c6031cb0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1564672043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1564672043
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.961380202
Short name T851
Test name
Test status
Simulation time 40182765 ps
CPU time 1.14 seconds
Started Jun 22 04:35:43 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 196124 kb
Host smart-bb70dd2f-bacd-462e-959b-3b70d7b216bc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961380202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.961380202
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3021088209
Short name T894
Test name
Test status
Simulation time 500251701 ps
CPU time 1.24 seconds
Started Jun 22 04:35:23 PM PDT 24
Finished Jun 22 04:35:25 PM PDT 24
Peak memory 196512 kb
Host smart-5614d1a8-5323-433b-8dc3-80a3ab659993
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3021088209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3021088209
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1389625147
Short name T923
Test name
Test status
Simulation time 558490927 ps
CPU time 1.11 seconds
Started Jun 22 04:35:34 PM PDT 24
Finished Jun 22 04:35:36 PM PDT 24
Peak memory 195556 kb
Host smart-7ccb4bb4-05ae-43f9-90d6-2d27f51be6e5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389625147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1389625147
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.4039118122
Short name T854
Test name
Test status
Simulation time 76753963 ps
CPU time 1.02 seconds
Started Jun 22 04:35:46 PM PDT 24
Finished Jun 22 04:35:47 PM PDT 24
Peak memory 196276 kb
Host smart-2a2653bc-99b9-4034-90ee-8de538c3c1b6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4039118122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.4039118122
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1431143193
Short name T880
Test name
Test status
Simulation time 86953576 ps
CPU time 1.4 seconds
Started Jun 22 04:35:31 PM PDT 24
Finished Jun 22 04:35:33 PM PDT 24
Peak memory 197636 kb
Host smart-47735ced-5d69-4bfc-9ce4-c92a5bfaa0e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431143193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1431143193
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1403475124
Short name T873
Test name
Test status
Simulation time 156912660 ps
CPU time 1.42 seconds
Started Jun 22 04:35:46 PM PDT 24
Finished Jun 22 04:35:47 PM PDT 24
Peak memory 197736 kb
Host smart-4bfa174b-804d-45f7-a6c9-2dfb9f8d73d2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1403475124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1403475124
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1172896086
Short name T857
Test name
Test status
Simulation time 59340441 ps
CPU time 1.23 seconds
Started Jun 22 04:35:46 PM PDT 24
Finished Jun 22 04:35:48 PM PDT 24
Peak memory 195504 kb
Host smart-d022f690-3da4-4385-a6a5-c854242e395b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172896086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1172896086
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1913585445
Short name T885
Test name
Test status
Simulation time 45490248 ps
CPU time 0.78 seconds
Started Jun 22 04:35:41 PM PDT 24
Finished Jun 22 04:35:42 PM PDT 24
Peak memory 195248 kb
Host smart-0db70ea0-8000-40d0-88e4-31d23359dbef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1913585445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1913585445
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1153141157
Short name T863
Test name
Test status
Simulation time 145600129 ps
CPU time 0.94 seconds
Started Jun 22 04:35:38 PM PDT 24
Finished Jun 22 04:35:39 PM PDT 24
Peak memory 196360 kb
Host smart-fade592b-8fed-48b3-bb4c-16d3da75012e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153141157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1153141157
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1631914745
Short name T944
Test name
Test status
Simulation time 171108217 ps
CPU time 1.16 seconds
Started Jun 22 04:35:48 PM PDT 24
Finished Jun 22 04:35:49 PM PDT 24
Peak memory 197800 kb
Host smart-3e753180-99f2-44df-ac8b-ab52123375b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1631914745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1631914745
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3133024837
Short name T882
Test name
Test status
Simulation time 55946814 ps
CPU time 1.06 seconds
Started Jun 22 04:35:45 PM PDT 24
Finished Jun 22 04:35:47 PM PDT 24
Peak memory 196192 kb
Host smart-e8d45424-c474-4d6b-985b-af5a3b663d6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133024837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3133024837
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3591773402
Short name T919
Test name
Test status
Simulation time 31635090 ps
CPU time 0.82 seconds
Started Jun 22 04:35:48 PM PDT 24
Finished Jun 22 04:35:50 PM PDT 24
Peak memory 196376 kb
Host smart-6cf6550c-c9d7-4ddf-b836-b41c7507baaf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3591773402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3591773402
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1781499661
Short name T878
Test name
Test status
Simulation time 146066546 ps
CPU time 1.36 seconds
Started Jun 22 04:35:49 PM PDT 24
Finished Jun 22 04:35:50 PM PDT 24
Peak memory 196372 kb
Host smart-4bc25b49-61a2-471c-974d-1e7d556a69b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781499661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1781499661
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2203221014
Short name T921
Test name
Test status
Simulation time 113794221 ps
CPU time 1.07 seconds
Started Jun 22 04:35:46 PM PDT 24
Finished Jun 22 04:35:48 PM PDT 24
Peak memory 195708 kb
Host smart-7b6fedd7-50bd-4f8b-a5b9-52ff35a5a1c6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2203221014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2203221014
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3134130934
Short name T897
Test name
Test status
Simulation time 140453022 ps
CPU time 1.12 seconds
Started Jun 22 04:35:39 PM PDT 24
Finished Jun 22 04:35:41 PM PDT 24
Peak memory 195596 kb
Host smart-2da13015-c02c-4e79-89b3-d75e9f3cc147
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134130934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3134130934
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.155674855
Short name T877
Test name
Test status
Simulation time 105771164 ps
CPU time 0.9 seconds
Started Jun 22 04:35:52 PM PDT 24
Finished Jun 22 04:35:53 PM PDT 24
Peak memory 196188 kb
Host smart-5327d667-bc37-4f71-9eaf-684ac4ed82aa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=155674855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.155674855
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2537420500
Short name T858
Test name
Test status
Simulation time 84671067 ps
CPU time 1.39 seconds
Started Jun 22 04:35:54 PM PDT 24
Finished Jun 22 04:35:56 PM PDT 24
Peak memory 196428 kb
Host smart-54e377dd-d821-4717-b37f-04901f813e58
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537420500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2537420500
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.522068904
Short name T889
Test name
Test status
Simulation time 323224348 ps
CPU time 1.49 seconds
Started Jun 22 04:35:45 PM PDT 24
Finished Jun 22 04:35:47 PM PDT 24
Peak memory 197760 kb
Host smart-00b65361-42ed-4d2e-a480-9f03c9d8c37b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=522068904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.522068904
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1101497171
Short name T883
Test name
Test status
Simulation time 234691680 ps
CPU time 1.22 seconds
Started Jun 22 04:35:42 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 196448 kb
Host smart-7d98216b-6e20-45d5-b462-489ecf0927f9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101497171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1101497171
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4210018444
Short name T941
Test name
Test status
Simulation time 85280226 ps
CPU time 0.71 seconds
Started Jun 22 04:35:37 PM PDT 24
Finished Jun 22 04:35:38 PM PDT 24
Peak memory 194916 kb
Host smart-5760cea3-d7ba-4488-b1a2-2a8166d79902
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4210018444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4210018444
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.382814551
Short name T898
Test name
Test status
Simulation time 52052410 ps
CPU time 1.1 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:52 PM PDT 24
Peak memory 196360 kb
Host smart-38cfe89b-ab76-4849-a903-da22d26daf62
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382814551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.382814551
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3986951276
Short name T914
Test name
Test status
Simulation time 237659384 ps
CPU time 1.2 seconds
Started Jun 22 04:35:37 PM PDT 24
Finished Jun 22 04:35:38 PM PDT 24
Peak memory 195396 kb
Host smart-8e500aa1-8f0d-4dcd-8891-297f8264da57
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3986951276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3986951276
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.17747119
Short name T901
Test name
Test status
Simulation time 495416368 ps
CPU time 0.82 seconds
Started Jun 22 04:35:23 PM PDT 24
Finished Jun 22 04:35:25 PM PDT 24
Peak memory 195064 kb
Host smart-a3b11f22-90f4-4402-8101-66b247c534ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17747119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.17747119
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1500157136
Short name T861
Test name
Test status
Simulation time 155305144 ps
CPU time 1.29 seconds
Started Jun 22 04:35:55 PM PDT 24
Finished Jun 22 04:35:58 PM PDT 24
Peak memory 196232 kb
Host smart-eac908a7-1103-45d5-8d0e-e3f5c48e8430
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1500157136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1500157136
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4144040876
Short name T866
Test name
Test status
Simulation time 53919538 ps
CPU time 1.31 seconds
Started Jun 22 04:35:45 PM PDT 24
Finished Jun 22 04:35:46 PM PDT 24
Peak memory 196424 kb
Host smart-1ffdd10d-798f-4216-aaf6-a30619ff691a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144040876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4144040876
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2835619807
Short name T862
Test name
Test status
Simulation time 82888005 ps
CPU time 1.3 seconds
Started Jun 22 04:35:54 PM PDT 24
Finished Jun 22 04:35:57 PM PDT 24
Peak memory 196384 kb
Host smart-81d18a6c-fbda-4aa9-a934-6e738f332c81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2835619807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2835619807
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3663383874
Short name T871
Test name
Test status
Simulation time 38084254 ps
CPU time 0.77 seconds
Started Jun 22 04:35:43 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 195960 kb
Host smart-3470e519-94ae-4662-8b7d-5aa9b075de04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663383874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3663383874
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.15951646
Short name T937
Test name
Test status
Simulation time 52373141 ps
CPU time 0.99 seconds
Started Jun 22 04:35:42 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 196196 kb
Host smart-025f8230-f688-472a-b988-14a1bd6e4bca
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=15951646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.15951646
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3805201066
Short name T931
Test name
Test status
Simulation time 464394433 ps
CPU time 0.9 seconds
Started Jun 22 04:35:37 PM PDT 24
Finished Jun 22 04:35:39 PM PDT 24
Peak memory 195816 kb
Host smart-eacbb99d-0a3e-46b8-b5ec-055682a3fe29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805201066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3805201066
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.2549781457
Short name T915
Test name
Test status
Simulation time 34645237 ps
CPU time 0.73 seconds
Started Jun 22 04:35:42 PM PDT 24
Finished Jun 22 04:35:43 PM PDT 24
Peak memory 194196 kb
Host smart-cd56bdc3-c8ee-42e4-af48-cfe97a8439ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2549781457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.2549781457
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3938089168
Short name T932
Test name
Test status
Simulation time 47260411 ps
CPU time 1.35 seconds
Started Jun 22 04:35:51 PM PDT 24
Finished Jun 22 04:35:53 PM PDT 24
Peak memory 197748 kb
Host smart-1c5e22a5-25c4-46c8-acc0-a1f81d461f67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938089168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3938089168
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1064007322
Short name T876
Test name
Test status
Simulation time 209128902 ps
CPU time 1.07 seconds
Started Jun 22 04:35:42 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 198080 kb
Host smart-72a14a77-fffd-4b64-bd99-1bd9b8e5c4dc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1064007322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1064007322
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1210187090
Short name T918
Test name
Test status
Simulation time 117430788 ps
CPU time 0.8 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:51 PM PDT 24
Peak memory 195328 kb
Host smart-116088e0-1aa3-431a-a6aa-19ffc349a816
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210187090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1210187090
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1192283537
Short name T935
Test name
Test status
Simulation time 287703616 ps
CPU time 0.77 seconds
Started Jun 22 04:35:46 PM PDT 24
Finished Jun 22 04:35:47 PM PDT 24
Peak memory 195956 kb
Host smart-e374c2c3-7700-4ec2-90d6-3e6c6891f356
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1192283537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1192283537
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3697755918
Short name T860
Test name
Test status
Simulation time 131999605 ps
CPU time 1.27 seconds
Started Jun 22 04:35:37 PM PDT 24
Finished Jun 22 04:35:39 PM PDT 24
Peak memory 196584 kb
Host smart-e835aff8-bb4a-43e1-baae-68df12d145b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697755918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3697755918
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.561480595
Short name T879
Test name
Test status
Simulation time 29279234 ps
CPU time 0.79 seconds
Started Jun 22 04:35:42 PM PDT 24
Finished Jun 22 04:35:43 PM PDT 24
Peak memory 195108 kb
Host smart-1821c10d-ed59-4a17-9dce-118f7e75126d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=561480595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.561480595
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.900842759
Short name T946
Test name
Test status
Simulation time 98907739 ps
CPU time 1.37 seconds
Started Jun 22 04:35:39 PM PDT 24
Finished Jun 22 04:35:41 PM PDT 24
Peak memory 196572 kb
Host smart-93fc4981-f58d-4311-b198-181ece3bbb62
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900842759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.900842759
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.196593414
Short name T904
Test name
Test status
Simulation time 169567944 ps
CPU time 0.8 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:51 PM PDT 24
Peak memory 197664 kb
Host smart-762197cd-8fcb-4cc3-8af0-a5e379b4908c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=196593414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.196593414
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.39068396
Short name T916
Test name
Test status
Simulation time 77144525 ps
CPU time 1.27 seconds
Started Jun 22 04:35:45 PM PDT 24
Finished Jun 22 04:35:47 PM PDT 24
Peak memory 196696 kb
Host smart-addca039-f8fd-43fc-aaa3-14ddef4babed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39068396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.39068396
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.564761096
Short name T920
Test name
Test status
Simulation time 40738922 ps
CPU time 1.13 seconds
Started Jun 22 04:35:49 PM PDT 24
Finished Jun 22 04:35:51 PM PDT 24
Peak memory 195376 kb
Host smart-43f4335c-f139-4638-810a-a3481059fc06
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=564761096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.564761096
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.650812631
Short name T922
Test name
Test status
Simulation time 127292393 ps
CPU time 1.1 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:52 PM PDT 24
Peak memory 196308 kb
Host smart-24e38509-a436-4403-9a62-881cd7f036b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650812631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.650812631
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.808563437
Short name T865
Test name
Test status
Simulation time 264701675 ps
CPU time 1.25 seconds
Started Jun 22 04:35:53 PM PDT 24
Finished Jun 22 04:35:55 PM PDT 24
Peak memory 196964 kb
Host smart-1943a25a-6865-4819-b857-201816e29fff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=808563437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.808563437
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2958946151
Short name T848
Test name
Test status
Simulation time 134440919 ps
CPU time 1.06 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:51 PM PDT 24
Peak memory 195664 kb
Host smart-44ffeb76-a18d-420a-8e6b-c0cb49deb7a5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958946151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2958946151
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1239440112
Short name T869
Test name
Test status
Simulation time 118889296 ps
CPU time 1.22 seconds
Started Jun 22 04:35:25 PM PDT 24
Finished Jun 22 04:35:27 PM PDT 24
Peak memory 196104 kb
Host smart-809d2092-2669-40e0-99ff-5272e25f9f32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1239440112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1239440112
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2909025326
Short name T886
Test name
Test status
Simulation time 182922842 ps
CPU time 0.92 seconds
Started Jun 22 04:35:40 PM PDT 24
Finished Jun 22 04:35:42 PM PDT 24
Peak memory 196248 kb
Host smart-d86d2b6d-3c59-45a5-b3a5-2c26f7a7e752
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909025326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2909025326
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3775521250
Short name T943
Test name
Test status
Simulation time 33501381 ps
CPU time 1.09 seconds
Started Jun 22 04:35:51 PM PDT 24
Finished Jun 22 04:35:53 PM PDT 24
Peak memory 196184 kb
Host smart-0b15cf20-6ae9-4792-9ab8-0fa00cafea59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3775521250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3775521250
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2789822110
Short name T938
Test name
Test status
Simulation time 139991871 ps
CPU time 1.05 seconds
Started Jun 22 04:35:49 PM PDT 24
Finished Jun 22 04:35:50 PM PDT 24
Peak memory 196336 kb
Host smart-d9553b0b-ec4a-43c9-954b-b286b9b15da6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789822110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2789822110
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1174821514
Short name T896
Test name
Test status
Simulation time 42253583 ps
CPU time 1.21 seconds
Started Jun 22 04:35:48 PM PDT 24
Finished Jun 22 04:35:55 PM PDT 24
Peak memory 195744 kb
Host smart-1bc9d108-9ee6-47ec-80b5-1268864c414e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1174821514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1174821514
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1707866903
Short name T900
Test name
Test status
Simulation time 41003393 ps
CPU time 1.02 seconds
Started Jun 22 04:35:48 PM PDT 24
Finished Jun 22 04:35:49 PM PDT 24
Peak memory 195648 kb
Host smart-8a7c0c4e-93e9-4360-ab1f-823a4d12d307
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707866903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1707866903
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.667381014
Short name T905
Test name
Test status
Simulation time 283753347 ps
CPU time 1.31 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:51 PM PDT 24
Peak memory 196644 kb
Host smart-22d24746-0660-4815-9f0c-a8f8fd4827da
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=667381014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.667381014
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1986523569
Short name T852
Test name
Test status
Simulation time 49225353 ps
CPU time 0.91 seconds
Started Jun 22 04:35:52 PM PDT 24
Finished Jun 22 04:35:54 PM PDT 24
Peak memory 197068 kb
Host smart-72142d93-4f29-45e0-96e4-1fc6db886d29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986523569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1986523569
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.660571308
Short name T881
Test name
Test status
Simulation time 58765928 ps
CPU time 1.03 seconds
Started Jun 22 04:35:54 PM PDT 24
Finished Jun 22 04:35:56 PM PDT 24
Peak memory 196368 kb
Host smart-c33d8690-fead-41fc-a390-f620817a547b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=660571308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.660571308
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3946250292
Short name T917
Test name
Test status
Simulation time 103585712 ps
CPU time 0.94 seconds
Started Jun 22 04:35:37 PM PDT 24
Finished Jun 22 04:35:38 PM PDT 24
Peak memory 195428 kb
Host smart-4b3328b5-aa64-4497-b8ef-c829258cfbb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946250292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3946250292
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1697159139
Short name T945
Test name
Test status
Simulation time 41353826 ps
CPU time 1.02 seconds
Started Jun 22 04:35:52 PM PDT 24
Finished Jun 22 04:35:54 PM PDT 24
Peak memory 196376 kb
Host smart-68d412c7-a114-4f89-b444-4d65d07fefa0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1697159139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1697159139
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2421557590
Short name T884
Test name
Test status
Simulation time 71199536 ps
CPU time 0.95 seconds
Started Jun 22 04:35:56 PM PDT 24
Finished Jun 22 04:35:59 PM PDT 24
Peak memory 196392 kb
Host smart-2ec51a40-1295-4270-878c-12d3581bb543
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421557590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2421557590
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2137619761
Short name T853
Test name
Test status
Simulation time 231781879 ps
CPU time 1.22 seconds
Started Jun 22 04:35:56 PM PDT 24
Finished Jun 22 04:35:59 PM PDT 24
Peak memory 197076 kb
Host smart-8f0b475a-81f4-40f4-8e19-50946a17a325
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2137619761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2137619761
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2160948519
Short name T933
Test name
Test status
Simulation time 55908081 ps
CPU time 1.11 seconds
Started Jun 22 04:35:51 PM PDT 24
Finished Jun 22 04:35:53 PM PDT 24
Peak memory 197664 kb
Host smart-3b04ac9d-62b0-46da-9aec-257528e9caf3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160948519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2160948519
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.138635182
Short name T942
Test name
Test status
Simulation time 90859909 ps
CPU time 0.9 seconds
Started Jun 22 04:36:03 PM PDT 24
Finished Jun 22 04:36:04 PM PDT 24
Peak memory 196336 kb
Host smart-91641206-2432-4d1b-afd6-770d0bf24a00
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=138635182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.138635182
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.863693711
Short name T890
Test name
Test status
Simulation time 43373424 ps
CPU time 0.97 seconds
Started Jun 22 04:35:57 PM PDT 24
Finished Jun 22 04:36:00 PM PDT 24
Peak memory 196252 kb
Host smart-0ca91f8b-4cfc-431e-ab6b-5fe413110631
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863693711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.863693711
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3815914586
Short name T870
Test name
Test status
Simulation time 219525199 ps
CPU time 1.26 seconds
Started Jun 22 04:36:03 PM PDT 24
Finished Jun 22 04:36:05 PM PDT 24
Peak memory 195952 kb
Host smart-864a6395-df0f-425c-a69f-0d35b8af2759
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3815914586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3815914586
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1664527839
Short name T910
Test name
Test status
Simulation time 49943833 ps
CPU time 0.91 seconds
Started Jun 22 04:35:52 PM PDT 24
Finished Jun 22 04:35:54 PM PDT 24
Peak memory 195272 kb
Host smart-55ae39fa-869b-4c15-a637-c92e66edd5e0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664527839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1664527839
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.495463999
Short name T887
Test name
Test status
Simulation time 75193329 ps
CPU time 0.94 seconds
Started Jun 22 04:36:08 PM PDT 24
Finished Jun 22 04:36:09 PM PDT 24
Peak memory 196288 kb
Host smart-710ad404-ad7a-4bd5-93e6-f2fb1cd4654d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=495463999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.495463999
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3331876560
Short name T895
Test name
Test status
Simulation time 102524697 ps
CPU time 0.94 seconds
Started Jun 22 04:35:57 PM PDT 24
Finished Jun 22 04:36:01 PM PDT 24
Peak memory 197700 kb
Host smart-8ab43d84-059c-4517-9fb1-f4a66d4ed632
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331876560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3331876560
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3034693936
Short name T928
Test name
Test status
Simulation time 197055665 ps
CPU time 1 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:34 PM PDT 24
Peak memory 195388 kb
Host smart-61612472-3206-42bc-9b89-ef26b1c67f54
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3034693936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3034693936
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.375325213
Short name T859
Test name
Test status
Simulation time 189117259 ps
CPU time 1.01 seconds
Started Jun 22 04:35:59 PM PDT 24
Finished Jun 22 04:36:02 PM PDT 24
Peak memory 196124 kb
Host smart-003f517f-c787-41ce-a894-8e2f8c4b9965
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375325213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.375325213
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.2235863486
Short name T907
Test name
Test status
Simulation time 101347909 ps
CPU time 1 seconds
Started Jun 22 04:35:44 PM PDT 24
Finished Jun 22 04:35:46 PM PDT 24
Peak memory 196340 kb
Host smart-47e55fc6-94d2-4b62-bd5a-0b57c7934d40
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2235863486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.2235863486
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3755977513
Short name T906
Test name
Test status
Simulation time 99641864 ps
CPU time 1.21 seconds
Started Jun 22 04:35:35 PM PDT 24
Finished Jun 22 04:35:37 PM PDT 24
Peak memory 196528 kb
Host smart-46eeec93-d908-4690-a78c-e24f0eae948a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755977513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3755977513
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.757297725
Short name T925
Test name
Test status
Simulation time 287279864 ps
CPU time 1.01 seconds
Started Jun 22 04:36:02 PM PDT 24
Finished Jun 22 04:36:04 PM PDT 24
Peak memory 195664 kb
Host smart-3ca5a2f0-02e2-4092-908c-84571eede4fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=757297725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.757297725
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2418783762
Short name T893
Test name
Test status
Simulation time 125715892 ps
CPU time 0.99 seconds
Started Jun 22 04:36:18 PM PDT 24
Finished Jun 22 04:36:20 PM PDT 24
Peak memory 197716 kb
Host smart-71522d96-e170-4ea3-9bc0-5d1da53a26c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418783762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2418783762
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.1328872698
Short name T927
Test name
Test status
Simulation time 46562527 ps
CPU time 1.29 seconds
Started Jun 22 04:35:58 PM PDT 24
Finished Jun 22 04:36:02 PM PDT 24
Peak memory 198096 kb
Host smart-d4266109-14c9-4872-b0ad-8ec863152303
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1328872698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.1328872698
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4151386110
Short name T847
Test name
Test status
Simulation time 66105963 ps
CPU time 1.15 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:52 PM PDT 24
Peak memory 195444 kb
Host smart-38ba0acf-46ec-4c94-ac9c-0ae0fe894916
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151386110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4151386110
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3396882309
Short name T912
Test name
Test status
Simulation time 639671346 ps
CPU time 0.98 seconds
Started Jun 22 04:35:57 PM PDT 24
Finished Jun 22 04:36:01 PM PDT 24
Peak memory 195552 kb
Host smart-2b464a54-4387-4196-a48b-46c5857915ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3396882309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3396882309
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2960339969
Short name T924
Test name
Test status
Simulation time 29598059 ps
CPU time 0.96 seconds
Started Jun 22 04:35:55 PM PDT 24
Finished Jun 22 04:35:57 PM PDT 24
Peak memory 196228 kb
Host smart-28d2436d-0f3d-4397-8f0a-691cbd6dd3f4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960339969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2960339969
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1661342453
Short name T875
Test name
Test status
Simulation time 84422468 ps
CPU time 1.29 seconds
Started Jun 22 04:35:54 PM PDT 24
Finished Jun 22 04:35:56 PM PDT 24
Peak memory 196524 kb
Host smart-a38234e2-8fad-4960-a65d-c67ab72bc189
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1661342453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1661342453
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1161146171
Short name T849
Test name
Test status
Simulation time 120982246 ps
CPU time 0.81 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:51 PM PDT 24
Peak memory 195260 kb
Host smart-4e5c5020-3c47-4e79-a8c2-6718ec0b8f6d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161146171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1161146171
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3922748821
Short name T908
Test name
Test status
Simulation time 59112542 ps
CPU time 1.16 seconds
Started Jun 22 04:35:54 PM PDT 24
Finished Jun 22 04:36:01 PM PDT 24
Peak memory 197312 kb
Host smart-d4bf1bba-dbd8-44c7-8f66-ccc0c7b51f35
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3922748821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3922748821
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1219111544
Short name T864
Test name
Test status
Simulation time 232859980 ps
CPU time 1.22 seconds
Started Jun 22 04:35:59 PM PDT 24
Finished Jun 22 04:36:02 PM PDT 24
Peak memory 195592 kb
Host smart-6ec8cb1c-31c0-48db-adff-62122fb2412c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219111544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1219111544
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.453337094
Short name T872
Test name
Test status
Simulation time 137097411 ps
CPU time 0.72 seconds
Started Jun 22 04:35:55 PM PDT 24
Finished Jun 22 04:35:58 PM PDT 24
Peak memory 195132 kb
Host smart-9f52c661-47e7-4240-a764-0b0f9f7ed679
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=453337094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.453337094
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2237556837
Short name T929
Test name
Test status
Simulation time 125162480 ps
CPU time 0.87 seconds
Started Jun 22 04:35:56 PM PDT 24
Finished Jun 22 04:35:59 PM PDT 24
Peak memory 195352 kb
Host smart-4c762826-52c3-4619-9fc2-f49e5b85a4c1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237556837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2237556837
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2213754752
Short name T888
Test name
Test status
Simulation time 69096089 ps
CPU time 1.35 seconds
Started Jun 22 04:36:11 PM PDT 24
Finished Jun 22 04:36:13 PM PDT 24
Peak memory 196456 kb
Host smart-53bd95d9-6dfd-49b6-a7f5-5fbb705f3677
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2213754752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2213754752
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1077271701
Short name T940
Test name
Test status
Simulation time 135554261 ps
CPU time 0.87 seconds
Started Jun 22 04:35:53 PM PDT 24
Finished Jun 22 04:35:55 PM PDT 24
Peak memory 195700 kb
Host smart-dbd7f6a2-0971-4d01-9aba-b7b299f837ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077271701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1077271701
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.435764969
Short name T856
Test name
Test status
Simulation time 562464964 ps
CPU time 1.33 seconds
Started Jun 22 04:35:52 PM PDT 24
Finished Jun 22 04:35:54 PM PDT 24
Peak memory 196172 kb
Host smart-252f02c0-51bd-4d55-9c91-6026b4d0897e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=435764969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.435764969
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1550671607
Short name T902
Test name
Test status
Simulation time 267254071 ps
CPU time 1.3 seconds
Started Jun 22 04:35:56 PM PDT 24
Finished Jun 22 04:35:59 PM PDT 24
Peak memory 197768 kb
Host smart-dc6e0606-e1bb-41f4-af70-47577d3b9e45
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550671607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1550671607
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1167791660
Short name T868
Test name
Test status
Simulation time 75670026 ps
CPU time 1.07 seconds
Started Jun 22 04:35:48 PM PDT 24
Finished Jun 22 04:35:49 PM PDT 24
Peak memory 196508 kb
Host smart-42eee2c5-d653-4758-82b3-e90d55b2db68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1167791660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1167791660
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1167575865
Short name T909
Test name
Test status
Simulation time 35220396 ps
CPU time 1.05 seconds
Started Jun 22 04:35:55 PM PDT 24
Finished Jun 22 04:35:58 PM PDT 24
Peak memory 196412 kb
Host smart-0996f660-93ba-4fce-9c09-dd2560301cc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167575865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1167575865
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.4005336341
Short name T867
Test name
Test status
Simulation time 42918538 ps
CPU time 1.19 seconds
Started Jun 22 04:35:58 PM PDT 24
Finished Jun 22 04:36:01 PM PDT 24
Peak memory 196312 kb
Host smart-29402b9b-55ae-41db-81e1-51dde89d4b5b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4005336341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.4005336341
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3219174193
Short name T899
Test name
Test status
Simulation time 100106310 ps
CPU time 0.78 seconds
Started Jun 22 04:35:58 PM PDT 24
Finished Jun 22 04:36:01 PM PDT 24
Peak memory 195328 kb
Host smart-d82a2490-b699-4040-b65a-40d2a012cf04
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219174193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3219174193
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1920969031
Short name T911
Test name
Test status
Simulation time 114903592 ps
CPU time 1.44 seconds
Started Jun 22 04:35:42 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 197796 kb
Host smart-347be01c-fd8c-4acf-8cac-649fe0e39a7f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1920969031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1920969031
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4260422469
Short name T934
Test name
Test status
Simulation time 34375636 ps
CPU time 0.96 seconds
Started Jun 22 04:35:34 PM PDT 24
Finished Jun 22 04:35:36 PM PDT 24
Peak memory 196316 kb
Host smart-a7d6a5de-25f9-4077-9d02-d080c1c4894f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260422469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4260422469
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.239408267
Short name T891
Test name
Test status
Simulation time 162120318 ps
CPU time 1.12 seconds
Started Jun 22 04:36:33 PM PDT 24
Finished Jun 22 04:36:35 PM PDT 24
Peak memory 196248 kb
Host smart-fd6aedc8-1eda-4017-8c96-cbbd1b45c626
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=239408267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.239408267
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2786652834
Short name T892
Test name
Test status
Simulation time 240776511 ps
CPU time 1.17 seconds
Started Jun 22 04:35:50 PM PDT 24
Finished Jun 22 04:35:52 PM PDT 24
Peak memory 196624 kb
Host smart-c3b7bc5f-df6d-4390-b679-9ff5b4dfc36c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786652834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2786652834
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3796971413
Short name T939
Test name
Test status
Simulation time 143888535 ps
CPU time 0.8 seconds
Started Jun 22 04:35:43 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 195212 kb
Host smart-78b8a184-890d-4619-8d1e-8cf4e84f4d4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3796971413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3796971413
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2263230324
Short name T855
Test name
Test status
Simulation time 221993024 ps
CPU time 1.04 seconds
Started Jun 22 04:35:44 PM PDT 24
Finished Jun 22 04:35:45 PM PDT 24
Peak memory 195672 kb
Host smart-461b703d-f20b-4bb8-80a0-23c167b5797e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263230324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2263230324
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3595234793
Short name T936
Test name
Test status
Simulation time 142681271 ps
CPU time 1.18 seconds
Started Jun 22 04:35:26 PM PDT 24
Finished Jun 22 04:35:27 PM PDT 24
Peak memory 196348 kb
Host smart-6623c2ac-0b21-498d-8530-e7b21fd86e62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3595234793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3595234793
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.813925306
Short name T913
Test name
Test status
Simulation time 94264114 ps
CPU time 1.24 seconds
Started Jun 22 04:35:42 PM PDT 24
Finished Jun 22 04:35:44 PM PDT 24
Peak memory 196616 kb
Host smart-85033cba-95d1-484b-8714-988b7e391480
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813925306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.813925306
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.4089831409
Short name T930
Test name
Test status
Simulation time 205146233 ps
CPU time 0.9 seconds
Started Jun 22 04:35:34 PM PDT 24
Finished Jun 22 04:35:35 PM PDT 24
Peak memory 195328 kb
Host smart-2616c8e5-9061-4609-8401-cf0143a85ee9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4089831409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.4089831409
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1980392173
Short name T926
Test name
Test status
Simulation time 94745046 ps
CPU time 1.41 seconds
Started Jun 22 04:35:39 PM PDT 24
Finished Jun 22 04:35:40 PM PDT 24
Peak memory 197748 kb
Host smart-02209459-c159-498c-ad7a-e505c6685820
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980392173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1980392173
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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