Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12766972	1			T23	24726		T24	416		T25	204
all_values[1]	12766972	1			T23	24726		T24	416		T25	204
all_values[2]	12766972	1			T23	24726		T24	416		T25	204
all_values[3]	12766972	1			T23	24726		T24	416		T25	204
all_values[4]	12766972	1			T23	24726		T24	416		T25	204
all_values[5]	12766972	1			T23	24726		T24	416		T25	204
all_values[6]	12766972	1			T23	24726		T24	416		T25	204
all_values[7]	12766972	1			T23	24726		T24	416		T25	204
all_values[8]	12766972	1			T23	24726		T24	416		T25	204
all_values[9]	12766972	1			T23	24726		T24	416		T25	204
all_values[10]	12766972	1			T23	24726		T24	416		T25	204
all_values[11]	12766972	1			T23	24726		T24	416		T25	204
all_values[12]	12766972	1			T23	24726		T24	416		T25	204
all_values[13]	12766972	1			T23	24726		T24	416		T25	204
all_values[14]	12766972	1			T23	24726		T24	416		T25	204
all_values[15]	12766972	1			T23	24726		T24	416		T25	204
all_values[16]	12766972	1			T23	24726		T24	416		T25	204
all_values[17]	12766972	1			T23	24726		T24	416		T25	204
all_values[18]	12766972	1			T23	24726		T24	416		T25	204
all_values[19]	12766972	1			T23	24726		T24	416		T25	204
all_values[20]	12766972	1			T23	24726		T24	416		T25	204
all_values[21]	12766972	1			T23	24726		T24	416		T25	204
all_values[22]	12766972	1			T23	24726		T24	416		T25	204
all_values[23]	12766972	1			T23	24726		T24	416		T25	204
all_values[24]	12766972	1			T23	24726		T24	416		T25	204
all_values[25]	12766972	1			T23	24726		T24	416		T25	204
all_values[26]	12766972	1			T23	24726		T24	416		T25	204
all_values[27]	12766972	1			T23	24726		T24	416		T25	204
all_values[28]	12766972	1			T23	24726		T24	416		T25	204
all_values[29]	12766972	1			T23	24726		T24	416		T25	204
all_values[30]	12766972	1			T23	24726		T24	416		T25	204
all_values[31]	12766972	1			T23	24726		T24	416		T25	204

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238064079

1

T23

791232

T24

13312

T25

6528

auto[1]

170479025

1

T26

1461

T27

4266

T1

4847

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100179847

1

T23

791232

T24

13312

T25

6528

auto[1]

308363257

1

T26

2296

T27

7331

T1

10206

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2617267	1			T23	24726		T24	416		T25	204
all_values[0]	auto[0]	auto[1]	4808536	1			T26	54		T27	170		T1	176
all_values[0]	auto[1]	auto[0]	512281	1			T26	2		T27	5		T13	51
all_values[0]	auto[1]	auto[1]	4828888	1			T26	22		T27	72		T1	151
all_values[1]	auto[0]	auto[0]	2615382	1			T23	24726		T24	416		T25	204
all_values[1]	auto[0]	auto[1]	4836314	1			T26	38		T27	106		T1	170
all_values[1]	auto[1]	auto[0]	510401	1			T26	16		T27	14		T1	10
all_values[1]	auto[1]	auto[1]	4804875	1			T26	11		T27	130		T1	122
all_values[2]	auto[0]	auto[0]	2617755	1			T23	24726		T24	416		T25	204
all_values[2]	auto[0]	auto[1]	4814261	1			T26	61		T27	99		T1	114
all_values[2]	auto[1]	auto[0]	518186	1			T26	2		T27	9		T1	6
all_values[2]	auto[1]	auto[1]	4816770	1			T26	30		T27	148		T1	213
all_values[3]	auto[0]	auto[0]	2613801	1			T23	24726		T24	416		T25	204
all_values[3]	auto[0]	auto[1]	4798396	1			T26	27		T27	98		T1	166
all_values[3]	auto[1]	auto[0]	516213	1			T26	5		T27	27		T1	12
all_values[3]	auto[1]	auto[1]	4838562	1			T26	37		T27	122		T1	138
all_values[4]	auto[0]	auto[0]	2616962	1			T23	24726		T24	416		T25	204
all_values[4]	auto[0]	auto[1]	4824354	1			T26	39		T27	141		T1	150
all_values[4]	auto[1]	auto[0]	510873	1			T26	9		T27	13		T1	9
all_values[4]	auto[1]	auto[1]	4814783	1			T26	46		T27	82		T1	161
all_values[5]	auto[0]	auto[0]	2614133	1			T23	24726		T24	416		T25	204
all_values[5]	auto[0]	auto[1]	4819123	1			T26	29		T27	93		T1	277
all_values[5]	auto[1]	auto[0]	514852	1			T26	21		T27	15		T13	44
all_values[5]	auto[1]	auto[1]	4818864	1			T26	28		T27	148		T1	58
all_values[6]	auto[0]	auto[0]	2613748	1			T23	24726		T24	416		T25	204
all_values[6]	auto[0]	auto[1]	4810975	1			T26	42		T27	88		T1	164
all_values[6]	auto[1]	auto[0]	519399	1			T26	9		T27	16		T1	34
all_values[6]	auto[1]	auto[1]	4822850	1			T26	42		T27	143		T1	138
all_values[7]	auto[0]	auto[0]	2612154	1			T23	24726		T24	416		T25	204
all_values[7]	auto[0]	auto[1]	4799762	1			T26	57		T27	98		T1	157
all_values[7]	auto[1]	auto[0]	520372	1			T26	4		T27	13		T13	139
all_values[7]	auto[1]	auto[1]	4834684	1			T26	23		T27	126		T1	169
all_values[8]	auto[0]	auto[0]	2611615	1			T23	24726		T24	416		T25	204
all_values[8]	auto[0]	auto[1]	4813723	1			T26	37		T27	91		T1	245
all_values[8]	auto[1]	auto[0]	530054	1			T26	13		T27	9		T1	2
all_values[8]	auto[1]	auto[1]	4811580	1			T26	27		T27	147		T1	86
all_values[9]	auto[0]	auto[0]	2608732	1			T23	24726		T24	416		T25	204
all_values[9]	auto[0]	auto[1]	4835617	1			T26	28		T27	76		T1	167
all_values[9]	auto[1]	auto[0]	514341	1			T26	15		T27	18		T1	27
all_values[9]	auto[1]	auto[1]	4808282	1			T26	30		T27	159		T1	140
all_values[10]	auto[0]	auto[0]	2603966	1			T23	24726		T24	416		T25	204
all_values[10]	auto[0]	auto[1]	4807948	1			T26	44		T27	169		T1	173
all_values[10]	auto[1]	auto[0]	521054	1			T26	1		T27	10		T13	112
all_values[10]	auto[1]	auto[1]	4834004	1			T26	39		T27	61		T1	130
all_values[11]	auto[0]	auto[0]	2611395	1			T23	24726		T24	416		T25	204
all_values[11]	auto[0]	auto[1]	4828156	1			T26	44		T27	103		T1	196
all_values[11]	auto[1]	auto[0]	505954	1			T26	23		T27	18		T1	8
all_values[11]	auto[1]	auto[1]	4821467	1			T26	17		T27	136		T1	119
all_values[12]	auto[0]	auto[0]	2608859	1			T23	24726		T24	416		T25	204
all_values[12]	auto[0]	auto[1]	4863104	1			T26	11		T27	126		T1	145
all_values[12]	auto[1]	auto[0]	515466	1			T26	23		T27	4		T1	15
all_values[12]	auto[1]	auto[1]	4779543	1			T26	35		T27	102		T1	174
all_values[13]	auto[0]	auto[0]	2604070	1			T23	24726		T24	416		T25	204
all_values[13]	auto[0]	auto[1]	4827768	1			T26	42		T27	95		T1	239
all_values[13]	auto[1]	auto[0]	513574	1			T26	21		T27	15		T1	4
all_values[13]	auto[1]	auto[1]	4821560	1			T26	19		T27	125		T1	98
all_values[14]	auto[0]	auto[0]	2612448	1			T23	24726		T24	416		T25	204
all_values[14]	auto[0]	auto[1]	4837716	1			T26	42		T27	82		T1	174
all_values[14]	auto[1]	auto[0]	517816	1			T26	23		T27	10		T1	25
all_values[14]	auto[1]	auto[1]	4798992	1			T26	23		T27	149		T1	137
all_values[15]	auto[0]	auto[0]	2611438	1			T23	24726		T24	416		T25	204
all_values[15]	auto[0]	auto[1]	4815869	1			T26	31		T27	167		T1	195
all_values[15]	auto[1]	auto[0]	517356	1			T26	20		T27	12		T1	6
all_values[15]	auto[1]	auto[1]	4822309	1			T26	33		T27	74		T1	125
all_values[16]	auto[0]	auto[0]	2615821	1			T23	24726		T24	416		T25	204
all_values[16]	auto[0]	auto[1]	4815511	1			T26	59		T27	102		T1	202
all_values[16]	auto[1]	auto[0]	517812	1			T27	23		T13	116		T2	20
all_values[16]	auto[1]	auto[1]	4817828	1			T26	25		T27	105		T1	139
all_values[17]	auto[0]	auto[0]	2611163	1			T23	24726		T24	416		T25	204
all_values[17]	auto[0]	auto[1]	4862052	1			T26	21		T27	110		T1	212
all_values[17]	auto[1]	auto[0]	513028	1			T26	8		T27	7		T1	15
all_values[17]	auto[1]	auto[1]	4780729	1			T26	66		T27	124		T1	115
all_values[18]	auto[0]	auto[0]	2605959	1			T23	24726		T24	416		T25	204
all_values[18]	auto[0]	auto[1]	4791998	1			T26	22		T27	87		T1	196
all_values[18]	auto[1]	auto[0]	522047	1			T26	22		T27	28		T1	2
all_values[18]	auto[1]	auto[1]	4846968	1			T26	51		T27	135		T1	131
all_values[19]	auto[0]	auto[0]	2615451	1			T23	24726		T24	416		T25	204
all_values[19]	auto[0]	auto[1]	4807710	1			T26	49		T27	71		T1	145
all_values[19]	auto[1]	auto[0]	520025	1			T26	3		T27	29		T1	3
all_values[19]	auto[1]	auto[1]	4823786	1			T26	37		T27	154		T1	187
all_values[20]	auto[0]	auto[0]	2617070	1			T23	24726		T24	416		T25	204
all_values[20]	auto[0]	auto[1]	4812728	1			T26	44		T27	95		T1	163
all_values[20]	auto[1]	auto[0]	517689	1			T26	10		T27	30		T1	5
all_values[20]	auto[1]	auto[1]	4819485	1			T26	30		T27	111		T1	162
all_values[21]	auto[0]	auto[0]	2618664	1			T23	24726		T24	416		T25	204
all_values[21]	auto[0]	auto[1]	4838316	1			T26	34		T27	117		T1	160
all_values[21]	auto[1]	auto[0]	525430	1			T26	8		T27	13		T1	5
all_values[21]	auto[1]	auto[1]	4784562	1			T26	47		T27	110		T1	128
all_values[22]	auto[0]	auto[0]	2610005	1			T23	24726		T24	416		T25	204
all_values[22]	auto[0]	auto[1]	4823959	1			T26	58		T27	114		T1	180
all_values[22]	auto[1]	auto[0]	515241	1			T26	9		T27	23		T1	42
all_values[22]	auto[1]	auto[1]	4817767	1			T26	15		T27	111		T1	115
all_values[23]	auto[0]	auto[0]	2611397	1			T23	24726		T24	416		T25	204
all_values[23]	auto[0]	auto[1]	4836146	1			T26	51		T27	143		T1	193
all_values[23]	auto[1]	auto[0]	516643	1			T26	3		T27	4		T1	1
all_values[23]	auto[1]	auto[1]	4802786	1			T26	33		T27	92		T1	142
all_values[24]	auto[0]	auto[0]	2611215	1			T23	24726		T24	416		T25	204
all_values[24]	auto[0]	auto[1]	4852648	1			T26	27		T27	83		T1	128
all_values[24]	auto[1]	auto[0]	519599	1			T26	19		T27	21		T1	8
all_values[24]	auto[1]	auto[1]	4783510	1			T26	36		T27	154		T1	190
all_values[25]	auto[0]	auto[0]	2609337	1			T23	24726		T24	416		T25	204
all_values[25]	auto[0]	auto[1]	4850101	1			T26	9		T27	136		T1	211
all_values[25]	auto[1]	auto[0]	516201	1			T26	7		T27	4		T1	7
all_values[25]	auto[1]	auto[1]	4791333	1			T26	69		T27	106		T1	107
all_values[26]	auto[0]	auto[0]	2630265	1			T23	24726		T24	416		T25	204
all_values[26]	auto[0]	auto[1]	4818849	1			T26	25		T27	103		T1	137
all_values[26]	auto[1]	auto[0]	521156	1			T26	15		T27	27		T1	7
all_values[26]	auto[1]	auto[1]	4796702	1			T26	37		T27	106		T1	175
all_values[27]	auto[0]	auto[0]	2610981	1			T23	24726		T24	416		T25	204
all_values[27]	auto[0]	auto[1]	4844600	1			T26	27		T27	112		T1	156
all_values[27]	auto[1]	auto[0]	520827	1			T26	17		T27	8		T1	15
all_values[27]	auto[1]	auto[1]	4790564	1			T26	51		T27	129		T1	164
all_values[28]	auto[0]	auto[0]	2614482	1			T23	24726		T24	416		T25	204
all_values[28]	auto[0]	auto[1]	4826962	1			T26	37		T27	103		T1	173
all_values[28]	auto[1]	auto[0]	521146	1			T26	18		T1	7		T13	39
all_values[28]	auto[1]	auto[1]	4804382	1			T26	36		T27	132		T1	133
all_values[29]	auto[0]	auto[0]	2607108	1			T23	24726		T24	416		T25	204
all_values[29]	auto[0]	auto[1]	4838823	1			T26	32		T27	127		T1	148
all_values[29]	auto[1]	auto[0]	518517	1			T26	40		T27	12		T13	125
all_values[29]	auto[1]	auto[1]	4802524	1			T26	21		T27	88		T1	191
all_values[30]	auto[0]	auto[0]	2611665	1			T23	24726		T24	416		T25	204
all_values[30]	auto[0]	auto[1]	4836398	1			T26	57		T27	120		T1	180
all_values[30]	auto[1]	auto[0]	521750	1			T26	1		T27	8		T1	9
all_values[30]	auto[1]	auto[1]	4797159	1			T26	16		T27	111		T1	152
all_values[31]	auto[0]	auto[0]	2616341	1			T23	24726		T24	416		T25	204
all_values[31]	auto[0]	auto[1]	4855007	1			T26	52		T27	96		T1	159
all_values[31]	auto[1]	auto[0]	523895	1			T26	8		T27	11		T1	8
all_values[31]	auto[1]	auto[1]	4771729	1			T26	34		T27	118		T1	165