Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3791339	1			T23	53		T24	1		T25	1
all_pins[1]	3791339	1			T23	53		T24	1		T25	1
all_pins[2]	3791339	1			T23	53		T24	1		T25	1
all_pins[3]	3791339	1			T23	53		T24	1		T25	1
all_pins[4]	3791339	1			T23	53		T24	1		T25	1
all_pins[5]	3791339	1			T23	53		T24	1		T25	1
all_pins[6]	3791339	1			T23	53		T24	1		T25	1
all_pins[7]	3791339	1			T23	53		T24	1		T25	1
all_pins[8]	3791339	1			T23	53		T24	1		T25	1
all_pins[9]	3791339	1			T23	53		T24	1		T25	1
all_pins[10]	3791339	1			T23	53		T24	1		T25	1
all_pins[11]	3791339	1			T23	53		T24	1		T25	1
all_pins[12]	3791339	1			T23	53		T24	1		T25	1
all_pins[13]	3791339	1			T23	53		T24	1		T25	1
all_pins[14]	3791339	1			T23	53		T24	1		T25	1
all_pins[15]	3791339	1			T23	53		T24	1		T25	1
all_pins[16]	3791339	1			T23	53		T24	1		T25	1
all_pins[17]	3791339	1			T23	53		T24	1		T25	1
all_pins[18]	3791339	1			T23	53		T24	1		T25	1
all_pins[19]	3791339	1			T23	53		T24	1		T25	1
all_pins[20]	3791339	1			T23	53		T24	1		T25	1
all_pins[21]	3791339	1			T23	53		T24	1		T25	1
all_pins[22]	3791339	1			T23	53		T24	1		T25	1
all_pins[23]	3791339	1			T23	53		T24	1		T25	1
all_pins[24]	3791339	1			T23	53		T24	1		T25	1
all_pins[25]	3791339	1			T23	53		T24	1		T25	1
all_pins[26]	3791339	1			T23	53		T24	1		T25	1
all_pins[27]	3791339	1			T23	53		T24	1		T25	1
all_pins[28]	3791339	1			T23	53		T24	1		T25	1
all_pins[29]	3791339	1			T23	53		T24	1		T25	1
all_pins[30]	3791339	1			T23	53		T24	1		T25	1
all_pins[31]	3791339	1			T23	53		T24	1		T25	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	75363226	1			T23	908		T24	32		T25	32
values[0x1]	45959622	1			T23	788		T26	592		T27	1724
transitions[0x0=>0x1]	27527121	1			T23	402		T26	379		T27	975
transitions[0x1=>0x0]	27526960	1			T23	401		T26	378		T27	974

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2350892	1			T23	31		T24	1		T25	1
all_pins[0]	values[0x1]	1440447	1			T23	22		T26	18		T27	32
all_pins[0]	transitions[0x0=>0x1]	892491	1			T23	9		T26	13		T27	12
all_pins[0]	transitions[0x1=>0x0]	887704	1			T23	17		T26	13		T27	41
all_pins[1]	values[0x0]	2358718	1			T23	30		T24	1		T25	1
all_pins[1]	values[0x1]	1432621	1			T23	23		T26	4		T27	59
all_pins[1]	transitions[0x0=>0x1]	854095	1			T23	11		T26	1		T27	41
all_pins[1]	transitions[0x1=>0x0]	861921	1			T23	10		T26	15		T27	14
all_pins[2]	values[0x0]	2353759	1			T23	23		T24	1		T25	1
all_pins[2]	values[0x1]	1437580	1			T23	30		T26	19		T27	62
all_pins[2]	transitions[0x0=>0x1]	859938	1			T23	16		T26	19		T27	30
all_pins[2]	transitions[0x1=>0x0]	854979	1			T23	9		T26	4		T27	27
all_pins[3]	values[0x0]	2356838	1			T23	27		T24	1		T25	1
all_pins[3]	values[0x1]	1434501	1			T23	26		T26	16		T27	60
all_pins[3]	transitions[0x0=>0x1]	857758	1			T23	11		T26	11		T27	31
all_pins[3]	transitions[0x1=>0x0]	860837	1			T23	15		T26	14		T27	33
all_pins[4]	values[0x0]	2356105	1			T23	32		T24	1		T25	1
all_pins[4]	values[0x1]	1435234	1			T23	21		T26	25		T27	47
all_pins[4]	transitions[0x0=>0x1]	859408	1			T23	13		T26	17		T27	23
all_pins[4]	transitions[0x1=>0x0]	858675	1			T23	18		T26	8		T27	36
all_pins[5]	values[0x0]	2351058	1			T23	29		T24	1		T25	1
all_pins[5]	values[0x1]	1440281	1			T23	24		T26	20		T27	63
all_pins[5]	transitions[0x0=>0x1]	865089	1			T23	16		T26	10		T27	37
all_pins[5]	transitions[0x1=>0x0]	860042	1			T23	13		T26	15		T27	21
all_pins[6]	values[0x0]	2352987	1			T23	27		T24	1		T25	1
all_pins[6]	values[0x1]	1438352	1			T23	26		T26	21		T27	63
all_pins[6]	transitions[0x0=>0x1]	860095	1			T23	13		T26	19		T27	26
all_pins[6]	transitions[0x1=>0x0]	862024	1			T23	11		T26	18		T27	26
all_pins[7]	values[0x0]	2351954	1			T23	26		T24	1		T25	1
all_pins[7]	values[0x1]	1439385	1			T23	27		T26	13		T27	55
all_pins[7]	transitions[0x0=>0x1]	860990	1			T23	10		T26	9		T27	32
all_pins[7]	transitions[0x1=>0x0]	859957	1			T23	9		T26	17		T27	40
all_pins[8]	values[0x0]	2360593	1			T23	23		T24	1		T25	1
all_pins[8]	values[0x1]	1430746	1			T23	30		T26	16		T27	69
all_pins[8]	transitions[0x0=>0x1]	855891	1			T23	14		T26	10		T27	50
all_pins[8]	transitions[0x1=>0x0]	864530	1			T23	11		T26	7		T27	36
all_pins[9]	values[0x0]	2353078	1			T23	32		T24	1		T25	1
all_pins[9]	values[0x1]	1438261	1			T23	21		T26	14		T27	67
all_pins[9]	transitions[0x0=>0x1]	862943	1			T23	8		T26	6		T27	30
all_pins[9]	transitions[0x1=>0x0]	855428	1			T23	17		T26	8		T27	32
all_pins[10]	values[0x0]	2351121	1			T23	23		T24	1		T25	1
all_pins[10]	values[0x1]	1440218	1			T23	30		T26	19		T27	28
all_pins[10]	transitions[0x0=>0x1]	860851	1			T23	19		T26	8		T27	20
all_pins[10]	transitions[0x1=>0x0]	858894	1			T23	10		T26	3		T27	59
all_pins[11]	values[0x0]	2355428	1			T23	32		T24	1		T25	1
all_pins[11]	values[0x1]	1435911	1			T23	21		T26	10		T27	56
all_pins[11]	transitions[0x0=>0x1]	856986	1			T23	10		T26	9		T27	45
all_pins[11]	transitions[0x1=>0x0]	861293	1			T23	19		T26	18		T27	17
all_pins[12]	values[0x0]	2358537	1			T23	33		T24	1		T25	1
all_pins[12]	values[0x1]	1432802	1			T23	20		T26	18		T27	40
all_pins[12]	transitions[0x0=>0x1]	857242	1			T23	12		T26	15		T27	18
all_pins[12]	transitions[0x1=>0x0]	860351	1			T23	13		T26	7		T27	34
all_pins[13]	values[0x0]	2353499	1			T23	24		T24	1		T25	1
all_pins[13]	values[0x1]	1437840	1			T23	29		T26	7		T27	47
all_pins[13]	transitions[0x0=>0x1]	863251	1			T23	16		T26	5		T27	38
all_pins[13]	transitions[0x1=>0x0]	858213	1			T23	7		T26	16		T27	31
all_pins[14]	values[0x0]	2355911	1			T23	31		T24	1		T25	1
all_pins[14]	values[0x1]	1435428	1			T23	22		T26	12		T27	62
all_pins[14]	transitions[0x0=>0x1]	860644	1			T23	11		T26	11		T27	32
all_pins[14]	transitions[0x1=>0x0]	863056	1			T23	18		T26	6		T27	17
all_pins[15]	values[0x0]	2353347	1			T23	29		T24	1		T25	1
all_pins[15]	values[0x1]	1437992	1			T23	24		T26	23		T27	34
all_pins[15]	transitions[0x0=>0x1]	859150	1			T23	12		T26	22		T27	28
all_pins[15]	transitions[0x1=>0x0]	856586	1			T23	10		T26	11		T27	56
all_pins[16]	values[0x0]	2354463	1			T23	23		T24	1		T25	1
all_pins[16]	values[0x1]	1436876	1			T23	30		T26	13		T27	43
all_pins[16]	transitions[0x0=>0x1]	858635	1			T23	14		T26	5		T27	35
all_pins[16]	transitions[0x1=>0x0]	859751	1			T23	8		T26	15		T27	26
all_pins[17]	values[0x0]	2360692	1			T23	35		T24	1		T25	1
all_pins[17]	values[0x1]	1430647	1			T23	18		T26	41		T27	58
all_pins[17]	transitions[0x0=>0x1]	854852	1			T23	6		T26	31		T27	32
all_pins[17]	transitions[0x1=>0x0]	861081	1			T23	18		T26	3		T27	17
all_pins[18]	values[0x0]	2349368	1			T23	20		T24	1		T25	1
all_pins[18]	values[0x1]	1441971	1			T23	33		T26	31		T27	48
all_pins[18]	transitions[0x0=>0x1]	865068	1			T23	21		T26	7		T27	32
all_pins[18]	transitions[0x1=>0x0]	853744	1			T23	6		T26	17		T27	42
all_pins[19]	values[0x0]	2354689	1			T23	33		T24	1		T25	1
all_pins[19]	values[0x1]	1436650	1			T23	20		T26	23		T27	73
all_pins[19]	transitions[0x0=>0x1]	857405	1			T23	9		T26	6		T27	45
all_pins[19]	transitions[0x1=>0x0]	862726	1			T23	22		T26	14		T27	20
all_pins[20]	values[0x0]	2355450	1			T23	24		T24	1		T25	1
all_pins[20]	values[0x1]	1435889	1			T23	29		T26	17		T27	55
all_pins[20]	transitions[0x0=>0x1]	859132	1			T23	16		T27	19		T1	23
all_pins[20]	transitions[0x1=>0x0]	859893	1			T23	7		T26	6		T27	37
all_pins[21]	values[0x0]	2356081	1			T23	31		T24	1		T25	1
all_pins[21]	values[0x1]	1435258	1			T23	22		T26	25		T27	40
all_pins[21]	transitions[0x0=>0x1]	858679	1			T23	6		T26	23		T27	28
all_pins[21]	transitions[0x1=>0x0]	859310	1			T23	13		T26	15		T27	43
all_pins[22]	values[0x0]	2355402	1			T23	32		T24	1		T25	1
all_pins[22]	values[0x1]	1435937	1			T23	21		T26	6		T27	50
all_pins[22]	transitions[0x0=>0x1]	859566	1			T23	12		T26	4		T27	25
all_pins[22]	transitions[0x1=>0x0]	858887	1			T23	13		T26	23		T27	15
all_pins[23]	values[0x0]	2351646	1			T23	32		T24	1		T25	1
all_pins[23]	values[0x1]	1439693	1			T23	21		T26	18		T27	44
all_pins[23]	transitions[0x0=>0x1]	861197	1			T23	12		T26	18		T27	25
all_pins[23]	transitions[0x1=>0x0]	857441	1			T23	12		T26	6		T27	31
all_pins[24]	values[0x0]	2359480	1			T23	26		T24	1		T25	1
all_pins[24]	values[0x1]	1431859	1			T23	27		T26	18		T27	69
all_pins[24]	transitions[0x0=>0x1]	854559	1			T23	17		T26	7		T27	40
all_pins[24]	transitions[0x1=>0x0]	862393	1			T23	11		T26	7		T27	15
all_pins[25]	values[0x0]	2355712	1			T23	27		T24	1		T25	1
all_pins[25]	values[0x1]	1435627	1			T23	26		T26	38		T27	67
all_pins[25]	transitions[0x0=>0x1]	862097	1			T23	9		T26	26		T27	30
all_pins[25]	transitions[0x1=>0x0]	858329	1			T23	10		T26	6		T27	32
all_pins[26]	values[0x0]	2359493	1			T23	29		T24	1		T25	1
all_pins[26]	values[0x1]	1431846	1			T23	24		T26	19		T27	46
all_pins[26]	transitions[0x0=>0x1]	853971	1			T23	10		T26	9		T27	19
all_pins[26]	transitions[0x1=>0x0]	857752	1			T23	12		T26	28		T27	40
all_pins[27]	values[0x0]	2355853	1			T23	25		T24	1		T25	1
all_pins[27]	values[0x1]	1435486	1			T23	28		T26	28		T27	72
all_pins[27]	transitions[0x0=>0x1]	861123	1			T23	15		T26	15		T27	47
all_pins[27]	transitions[0x1=>0x0]	857483	1			T23	11		T26	6		T27	21
all_pins[28]	values[0x0]	2355250	1			T23	33		T24	1		T25	1
all_pins[28]	values[0x1]	1436089	1			T23	20		T26	18		T27	54
all_pins[28]	transitions[0x0=>0x1]	857131	1			T23	9		T26	8		T27	17
all_pins[28]	transitions[0x1=>0x0]	856528	1			T23	17		T26	18		T27	35
all_pins[29]	values[0x0]	2352995	1			T23	31		T24	1		T25	1
all_pins[29]	values[0x1]	1438344	1			T23	22		T26	13		T27	45
all_pins[29]	transitions[0x0=>0x1]	859531	1			T23	14		T26	6		T27	13
all_pins[29]	transitions[0x1=>0x0]	857276	1			T23	12		T26	11		T27	22
all_pins[30]	values[0x0]	2357309	1			T23	33		T24	1		T25	1
all_pins[30]	values[0x1]	1434030	1			T23	20		T26	10		T27	54
all_pins[30]	transitions[0x0=>0x1]	857393	1			T23	13		T26	10		T27	35
all_pins[30]	transitions[0x1=>0x0]	861707	1			T23	15		T26	13		T27	26
all_pins[31]	values[0x0]	2355518	1			T23	22		T24	1		T25	1
all_pins[31]	values[0x1]	1435821	1			T23	31		T26	19		T27	62
all_pins[31]	transitions[0x0=>0x1]	859960	1			T23	18		T26	19		T27	40
all_pins[31]	transitions[0x1=>0x0]	858169	1			T23	7		T26	10		T27	32