Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12766972	1			T23	24726		T24	416		T25	204
all_values[1]	12766972	1			T23	24726		T24	416		T25	204
all_values[2]	12766972	1			T23	24726		T24	416		T25	204
all_values[3]	12766972	1			T23	24726		T24	416		T25	204
all_values[4]	12766972	1			T23	24726		T24	416		T25	204
all_values[5]	12766972	1			T23	24726		T24	416		T25	204
all_values[6]	12766972	1			T23	24726		T24	416		T25	204
all_values[7]	12766972	1			T23	24726		T24	416		T25	204
all_values[8]	12766972	1			T23	24726		T24	416		T25	204
all_values[9]	12766972	1			T23	24726		T24	416		T25	204
all_values[10]	12766972	1			T23	24726		T24	416		T25	204
all_values[11]	12766972	1			T23	24726		T24	416		T25	204
all_values[12]	12766972	1			T23	24726		T24	416		T25	204
all_values[13]	12766972	1			T23	24726		T24	416		T25	204
all_values[14]	12766972	1			T23	24726		T24	416		T25	204
all_values[15]	12766972	1			T23	24726		T24	416		T25	204
all_values[16]	12766972	1			T23	24726		T24	416		T25	204
all_values[17]	12766972	1			T23	24726		T24	416		T25	204
all_values[18]	12766972	1			T23	24726		T24	416		T25	204
all_values[19]	12766972	1			T23	24726		T24	416		T25	204
all_values[20]	12766972	1			T23	24726		T24	416		T25	204
all_values[21]	12766972	1			T23	24726		T24	416		T25	204
all_values[22]	12766972	1			T23	24726		T24	416		T25	204
all_values[23]	12766972	1			T23	24726		T24	416		T25	204
all_values[24]	12766972	1			T23	24726		T24	416		T25	204
all_values[25]	12766972	1			T23	24726		T24	416		T25	204
all_values[26]	12766972	1			T23	24726		T24	416		T25	204
all_values[27]	12766972	1			T23	24726		T24	416		T25	204
all_values[28]	12766972	1			T23	24726		T24	416		T25	204
all_values[29]	12766972	1			T23	24726		T24	416		T25	204
all_values[30]	12766972	1			T23	24726		T24	416		T25	204
all_values[31]	12766972	1			T23	24726		T24	416		T25	204

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

238064079

1

T23

791232

T24

13312

T25

6528

auto[1]

170479025

1

T26

1461

T27

4266

T1

4847

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100179847

1

T23

791232

T24

13312

T25

6528

auto[1]

308363257

1

T26

2296

T27

7331

T1

10206

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

404088731

1

T23

791232

T24

13312

T25

6528

auto[1]

4454373

1

T1

497

T2

346

T14

51644

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2617267	1			T23	24726		T24	416		T25	204
all_values[0]	auto[0]	auto[0]	auto[1]	4739073	1			T26	54		T27	170		T1	168
all_values[0]	auto[0]	auto[1]	auto[0]	512281	1			T26	2		T27	5		T13	51
all_values[0]	auto[0]	auto[1]	auto[1]	4759523	1			T26	22		T27	72		T1	144
all_values[0]	auto[1]	auto[0]	auto[1]	69463	1			T1	8		T2	4		T14	772
all_values[0]	auto[1]	auto[1]	auto[1]	69365	1			T1	7		T2	2		T14	795
all_values[1]	auto[0]	auto[0]	auto[0]	2615382	1			T23	24726		T24	416		T25	204
all_values[1]	auto[0]	auto[0]	auto[1]	4766615	1			T26	38		T27	106		T1	163
all_values[1]	auto[0]	auto[1]	auto[0]	510401	1			T26	16		T27	14		T1	10
all_values[1]	auto[0]	auto[1]	auto[1]	4735221	1			T26	11		T27	130		T1	119
all_values[1]	auto[1]	auto[0]	auto[1]	69699	1			T1	7		T2	5		T14	836
all_values[1]	auto[1]	auto[1]	auto[1]	69654	1			T1	3		T2	5		T14	796
all_values[2]	auto[0]	auto[0]	auto[0]	2617755	1			T23	24726		T24	416		T25	204
all_values[2]	auto[0]	auto[0]	auto[1]	4744796	1			T26	61		T27	99		T1	110
all_values[2]	auto[0]	auto[1]	auto[0]	518186	1			T26	2		T27	9		T1	6
all_values[2]	auto[0]	auto[1]	auto[1]	4747176	1			T26	30		T27	148		T1	201
all_values[2]	auto[1]	auto[0]	auto[1]	69465	1			T1	4		T2	7		T14	794
all_values[2]	auto[1]	auto[1]	auto[1]	69594	1			T1	12		T2	5		T14	766
all_values[3]	auto[0]	auto[0]	auto[0]	2613801	1			T23	24726		T24	416		T25	204
all_values[3]	auto[0]	auto[0]	auto[1]	4728650	1			T26	27		T27	98		T1	157
all_values[3]	auto[0]	auto[1]	auto[0]	516213	1			T26	5		T27	27		T1	12
all_values[3]	auto[0]	auto[1]	auto[1]	4769218	1			T26	37		T27	122		T1	134
all_values[3]	auto[1]	auto[0]	auto[1]	69746	1			T1	9		T2	7		T14	816
all_values[3]	auto[1]	auto[1]	auto[1]	69344	1			T1	4		T2	4		T14	746
all_values[4]	auto[0]	auto[0]	auto[0]	2616962	1			T23	24726		T24	416		T25	204
all_values[4]	auto[0]	auto[0]	auto[1]	4754222	1			T26	39		T27	141		T1	143
all_values[4]	auto[0]	auto[1]	auto[0]	510873	1			T26	9		T27	13		T1	9
all_values[4]	auto[0]	auto[1]	auto[1]	4745516	1			T26	46		T27	82		T1	153
all_values[4]	auto[1]	auto[0]	auto[1]	70132	1			T1	7		T2	11		T14	794
all_values[4]	auto[1]	auto[1]	auto[1]	69267	1			T1	8		T2	3		T14	806
all_values[5]	auto[0]	auto[0]	auto[0]	2614133	1			T23	24726		T24	416		T25	204
all_values[5]	auto[0]	auto[0]	auto[1]	4749594	1			T26	29		T27	93		T1	268
all_values[5]	auto[0]	auto[1]	auto[0]	514852	1			T26	21		T27	15		T13	44
all_values[5]	auto[0]	auto[1]	auto[1]	4749091	1			T26	28		T27	148		T1	55
all_values[5]	auto[1]	auto[0]	auto[1]	69529	1			T1	9		T2	5		T14	812
all_values[5]	auto[1]	auto[1]	auto[1]	69773	1			T1	3		T2	1		T14	818
all_values[6]	auto[0]	auto[0]	auto[0]	2613748	1			T23	24726		T24	416		T25	204
all_values[6]	auto[0]	auto[0]	auto[1]	4741382	1			T26	42		T27	88		T1	157
all_values[6]	auto[0]	auto[1]	auto[0]	519399	1			T26	9		T27	16		T1	34
all_values[6]	auto[0]	auto[1]	auto[1]	4753027	1			T26	42		T27	143		T1	130
all_values[6]	auto[1]	auto[0]	auto[1]	69593	1			T1	7		T2	12		T14	781
all_values[6]	auto[1]	auto[1]	auto[1]	69823	1			T1	8		T2	1		T14	768
all_values[7]	auto[0]	auto[0]	auto[0]	2612154	1			T23	24726		T24	416		T25	204
all_values[7]	auto[0]	auto[0]	auto[1]	4729949	1			T26	57		T27	98		T1	150
all_values[7]	auto[0]	auto[1]	auto[0]	520372	1			T26	4		T27	13		T13	139
all_values[7]	auto[0]	auto[1]	auto[1]	4764965	1			T26	23		T27	126		T1	160
all_values[7]	auto[1]	auto[0]	auto[1]	69813	1			T1	7		T2	9		T14	801
all_values[7]	auto[1]	auto[1]	auto[1]	69719	1			T1	9		T2	5		T14	780
all_values[8]	auto[0]	auto[0]	auto[0]	2611615	1			T23	24726		T24	416		T25	204
all_values[8]	auto[0]	auto[0]	auto[1]	4744220	1			T26	37		T27	91		T1	233
all_values[8]	auto[0]	auto[1]	auto[0]	530054	1			T26	13		T27	9		T1	2
all_values[8]	auto[0]	auto[1]	auto[1]	4742217	1			T26	27		T27	147		T1	80
all_values[8]	auto[1]	auto[0]	auto[1]	69503	1			T1	12		T2	7		T14	815
all_values[8]	auto[1]	auto[1]	auto[1]	69363	1			T1	6		T2	5		T14	805
all_values[9]	auto[0]	auto[0]	auto[0]	2608732	1			T23	24726		T24	416		T25	204
all_values[9]	auto[0]	auto[0]	auto[1]	4766461	1			T26	28		T27	76		T1	159
all_values[9]	auto[0]	auto[1]	auto[0]	514341	1			T26	15		T27	18		T1	27
all_values[9]	auto[0]	auto[1]	auto[1]	4738737	1			T26	30		T27	159		T1	131
all_values[9]	auto[1]	auto[0]	auto[1]	69156	1			T1	8		T2	6		T14	808
all_values[9]	auto[1]	auto[1]	auto[1]	69545	1			T1	9		T2	4		T14	784
all_values[10]	auto[0]	auto[0]	auto[0]	2603966	1			T23	24726		T24	416		T25	204
all_values[10]	auto[0]	auto[0]	auto[1]	4738864	1			T26	44		T27	169		T1	164
all_values[10]	auto[0]	auto[1]	auto[0]	521054	1			T26	1		T27	10		T13	112
all_values[10]	auto[0]	auto[1]	auto[1]	4764408	1			T26	39		T27	61		T1	129
all_values[10]	auto[1]	auto[0]	auto[1]	69084	1			T1	9		T2	6		T14	900
all_values[10]	auto[1]	auto[1]	auto[1]	69596	1			T1	1		T2	6		T14	744
all_values[11]	auto[0]	auto[0]	auto[0]	2611395	1			T23	24726		T24	416		T25	204
all_values[11]	auto[0]	auto[0]	auto[1]	4758485	1			T26	44		T27	103		T1	186
all_values[11]	auto[0]	auto[1]	auto[0]	505954	1			T26	23		T27	18		T1	8
all_values[11]	auto[0]	auto[1]	auto[1]	4752259	1			T26	17		T27	136		T1	115
all_values[11]	auto[1]	auto[0]	auto[1]	69671	1			T1	10		T2	9		T14	792
all_values[11]	auto[1]	auto[1]	auto[1]	69208	1			T1	4		T2	5		T14	857
all_values[12]	auto[0]	auto[0]	auto[0]	2608859	1			T23	24726		T24	416		T25	204
all_values[12]	auto[0]	auto[0]	auto[1]	4792890	1			T26	11		T27	126		T1	137
all_values[12]	auto[0]	auto[1]	auto[0]	515466	1			T26	23		T27	4		T1	15
all_values[12]	auto[0]	auto[1]	auto[1]	4710989	1			T26	35		T27	102		T1	167
all_values[12]	auto[1]	auto[0]	auto[1]	70214	1			T1	8		T2	6		T14	826
all_values[12]	auto[1]	auto[1]	auto[1]	68554	1			T1	7		T2	4		T14	807
all_values[13]	auto[0]	auto[0]	auto[0]	2604070	1			T23	24726		T24	416		T25	204
all_values[13]	auto[0]	auto[0]	auto[1]	4758025	1			T26	42		T27	95		T1	225
all_values[13]	auto[0]	auto[1]	auto[0]	513574	1			T26	21		T27	15		T1	4
all_values[13]	auto[0]	auto[1]	auto[1]	4752102	1			T26	19		T27	125		T1	94
all_values[13]	auto[1]	auto[0]	auto[1]	69743	1			T1	14		T2	6		T14	828
all_values[13]	auto[1]	auto[1]	auto[1]	69458	1			T1	4		T2	3		T14	779
all_values[14]	auto[0]	auto[0]	auto[0]	2612448	1			T23	24726		T24	416		T25	204
all_values[14]	auto[0]	auto[0]	auto[1]	4767900	1			T26	42		T27	82		T1	166
all_values[14]	auto[0]	auto[1]	auto[0]	517816	1			T26	23		T27	10		T1	25
all_values[14]	auto[0]	auto[1]	auto[1]	4729667	1			T26	23		T27	149		T1	128
all_values[14]	auto[1]	auto[0]	auto[1]	69816	1			T1	8		T2	6		T14	856
all_values[14]	auto[1]	auto[1]	auto[1]	69325	1			T1	9		T2	5		T14	811
all_values[15]	auto[0]	auto[0]	auto[0]	2611438	1			T23	24726		T24	416		T25	204
all_values[15]	auto[0]	auto[0]	auto[1]	4745875	1			T26	31		T27	167		T1	185
all_values[15]	auto[0]	auto[1]	auto[0]	517356	1			T26	20		T27	12		T1	6
all_values[15]	auto[0]	auto[1]	auto[1]	4752694	1			T26	33		T27	74		T1	120
all_values[15]	auto[1]	auto[0]	auto[1]	69994	1			T1	10		T2	9		T14	815
all_values[15]	auto[1]	auto[1]	auto[1]	69615	1			T1	5		T2	7		T14	783
all_values[16]	auto[0]	auto[0]	auto[0]	2615821	1			T23	24726		T24	416		T25	204
all_values[16]	auto[0]	auto[0]	auto[1]	4745263	1			T26	59		T27	102		T1	192
all_values[16]	auto[0]	auto[1]	auto[0]	517812	1			T27	23		T13	116		T2	20
all_values[16]	auto[0]	auto[1]	auto[1]	4748628	1			T26	25		T27	105		T1	134
all_values[16]	auto[1]	auto[0]	auto[1]	70248	1			T1	10		T2	6		T14	783
all_values[16]	auto[1]	auto[1]	auto[1]	69200	1			T1	5		T2	3		T14	838
all_values[17]	auto[0]	auto[0]	auto[0]	2611163	1			T23	24726		T24	416		T25	204
all_values[17]	auto[0]	auto[0]	auto[1]	4792079	1			T26	21		T27	110		T1	204
all_values[17]	auto[0]	auto[1]	auto[0]	513028	1			T26	8		T27	7		T1	15
all_values[17]	auto[0]	auto[1]	auto[1]	4711690	1			T26	66		T27	124		T1	106
all_values[17]	auto[1]	auto[0]	auto[1]	69973	1			T1	8		T2	7		T14	807
all_values[17]	auto[1]	auto[1]	auto[1]	69039	1			T1	9		T2	2		T14	808
all_values[18]	auto[0]	auto[0]	auto[0]	2605959	1			T23	24726		T24	416		T25	204
all_values[18]	auto[0]	auto[0]	auto[1]	4721765	1			T26	22		T27	87		T1	186
all_values[18]	auto[0]	auto[1]	auto[0]	522047	1			T26	22		T27	28		T1	2
all_values[18]	auto[0]	auto[1]	auto[1]	4777533	1			T26	51		T27	135		T1	127
all_values[18]	auto[1]	auto[0]	auto[1]	70233	1			T1	10		T2	7		T14	796
all_values[18]	auto[1]	auto[1]	auto[1]	69435	1			T1	4		T2	3		T14	808
all_values[19]	auto[0]	auto[0]	auto[0]	2615451	1			T23	24726		T24	416		T25	204
all_values[19]	auto[0]	auto[0]	auto[1]	4737483	1			T26	49		T27	71		T1	134
all_values[19]	auto[0]	auto[1]	auto[0]	520025	1			T26	3		T27	29		T1	3
all_values[19]	auto[0]	auto[1]	auto[1]	4754687	1			T26	37		T27	154		T1	181
all_values[19]	auto[1]	auto[0]	auto[1]	70227	1			T1	11		T2	6		T14	810
all_values[19]	auto[1]	auto[1]	auto[1]	69099	1			T1	6		T2	3		T14	799
all_values[20]	auto[0]	auto[0]	auto[0]	2617070	1			T23	24726		T24	416		T25	204
all_values[20]	auto[0]	auto[0]	auto[1]	4742670	1			T26	44		T27	95		T1	157
all_values[20]	auto[0]	auto[1]	auto[0]	517689	1			T26	10		T27	30		T1	5
all_values[20]	auto[0]	auto[1]	auto[1]	4750207	1			T26	30		T27	111		T1	153
all_values[20]	auto[1]	auto[0]	auto[1]	70058	1			T1	6		T2	5		T14	811
all_values[20]	auto[1]	auto[1]	auto[1]	69278	1			T1	9		T2	5		T14	798
all_values[21]	auto[0]	auto[0]	auto[0]	2618664	1			T23	24726		T24	416		T25	204
all_values[21]	auto[0]	auto[0]	auto[1]	4767961	1			T26	34		T27	117		T1	154
all_values[21]	auto[0]	auto[1]	auto[0]	525430	1			T26	8		T27	13		T1	5
all_values[21]	auto[0]	auto[1]	auto[1]	4715834	1			T26	47		T27	110		T1	120
all_values[21]	auto[1]	auto[0]	auto[1]	70355	1			T1	6		T2	5		T14	787
all_values[21]	auto[1]	auto[1]	auto[1]	68728	1			T1	8		T2	3		T14	829
all_values[22]	auto[0]	auto[0]	auto[0]	2610005	1			T23	24726		T24	416		T25	204
all_values[22]	auto[0]	auto[0]	auto[1]	4754096	1			T26	58		T27	114		T1	168
all_values[22]	auto[0]	auto[1]	auto[0]	515241	1			T26	9		T27	23		T1	42
all_values[22]	auto[0]	auto[1]	auto[1]	4748586	1			T26	15		T27	111		T1	109
all_values[22]	auto[1]	auto[0]	auto[1]	69863	1			T1	12		T2	7		T14	807
all_values[22]	auto[1]	auto[1]	auto[1]	69181	1			T1	6		T2	3		T14	803
all_values[23]	auto[0]	auto[0]	auto[0]	2611397	1			T23	24726		T24	416		T25	204
all_values[23]	auto[0]	auto[0]	auto[1]	4766744	1			T26	51		T27	143		T1	189
all_values[23]	auto[0]	auto[1]	auto[0]	516643	1			T26	3		T27	4		T1	1
all_values[23]	auto[0]	auto[1]	auto[1]	4732897	1			T26	33		T27	92		T1	136
all_values[23]	auto[1]	auto[0]	auto[1]	69402	1			T1	4		T2	9		T14	853
all_values[23]	auto[1]	auto[1]	auto[1]	69889	1			T1	6		T2	4		T14	796
all_values[24]	auto[0]	auto[0]	auto[0]	2611215	1			T23	24726		T24	416		T25	204
all_values[24]	auto[0]	auto[0]	auto[1]	4782962	1			T26	27		T27	83		T1	119
all_values[24]	auto[0]	auto[1]	auto[0]	519599	1			T26	19		T27	21		T1	8
all_values[24]	auto[0]	auto[1]	auto[1]	4713895	1			T26	36		T27	154		T1	177
all_values[24]	auto[1]	auto[0]	auto[1]	69686	1			T1	9		T2	9		T14	807
all_values[24]	auto[1]	auto[1]	auto[1]	69615	1			T1	13		T2	4		T14	882
all_values[25]	auto[0]	auto[0]	auto[0]	2609337	1			T23	24726		T24	416		T25	204
all_values[25]	auto[0]	auto[0]	auto[1]	4780114	1			T26	9		T27	136		T1	203
all_values[25]	auto[0]	auto[1]	auto[0]	516201	1			T26	7		T27	4		T1	7
all_values[25]	auto[0]	auto[1]	auto[1]	4722009	1			T26	69		T27	106		T1	101
all_values[25]	auto[1]	auto[0]	auto[1]	69987	1			T1	8		T2	5		T14	842
all_values[25]	auto[1]	auto[1]	auto[1]	69324	1			T1	6		T2	5		T14	803
all_values[26]	auto[0]	auto[0]	auto[0]	2630265	1			T23	24726		T24	416		T25	204
all_values[26]	auto[0]	auto[0]	auto[1]	4749200	1			T26	25		T27	103		T1	128
all_values[26]	auto[0]	auto[1]	auto[0]	521156	1			T26	15		T27	27		T1	7
all_values[26]	auto[0]	auto[1]	auto[1]	4727260	1			T26	37		T27	106		T1	165
all_values[26]	auto[1]	auto[0]	auto[1]	69649	1			T1	9		T2	10		T14	834
all_values[26]	auto[1]	auto[1]	auto[1]	69442	1			T1	10		T2	1		T14	801
all_values[27]	auto[0]	auto[0]	auto[0]	2610981	1			T23	24726		T24	416		T25	204
all_values[27]	auto[0]	auto[0]	auto[1]	4774475	1			T26	27		T27	112		T1	149
all_values[27]	auto[0]	auto[1]	auto[0]	520827	1			T26	17		T27	8		T1	15
all_values[27]	auto[0]	auto[1]	auto[1]	4720937	1			T26	51		T27	129		T1	152
all_values[27]	auto[1]	auto[0]	auto[1]	70125	1			T1	7		T2	6		T14	775
all_values[27]	auto[1]	auto[1]	auto[1]	69627	1			T1	12		T2	4		T14	823
all_values[28]	auto[0]	auto[0]	auto[0]	2614482	1			T23	24726		T24	416		T25	204
all_values[28]	auto[0]	auto[0]	auto[1]	4756435	1			T26	37		T27	103		T1	162
all_values[28]	auto[0]	auto[1]	auto[0]	521146	1			T26	18		T1	7		T13	39
all_values[28]	auto[0]	auto[1]	auto[1]	4735830	1			T26	36		T27	132		T1	127
all_values[28]	auto[1]	auto[0]	auto[1]	70527	1			T1	11		T2	8		T14	827
all_values[28]	auto[1]	auto[1]	auto[1]	68552	1			T1	6		T2	2		T14	798
all_values[29]	auto[0]	auto[0]	auto[0]	2607108	1			T23	24726		T24	416		T25	204
all_values[29]	auto[0]	auto[0]	auto[1]	4768744	1			T26	32		T27	127		T1	141
all_values[29]	auto[0]	auto[1]	auto[0]	518517	1			T26	40		T27	12		T13	125
all_values[29]	auto[0]	auto[1]	auto[1]	4733641	1			T26	21		T27	88		T1	182
all_values[29]	auto[1]	auto[0]	auto[1]	70079	1			T1	7		T2	7		T14	889
all_values[29]	auto[1]	auto[1]	auto[1]	68883	1			T1	9		T2	1		T14	776
all_values[30]	auto[0]	auto[0]	auto[0]	2611665	1			T23	24726		T24	416		T25	204
all_values[30]	auto[0]	auto[0]	auto[1]	4766206	1			T26	57		T27	120		T1	170
all_values[30]	auto[0]	auto[1]	auto[0]	521750	1			T26	1		T27	8		T1	9
all_values[30]	auto[0]	auto[1]	auto[1]	4727814	1			T26	16		T27	111		T1	146
all_values[30]	auto[1]	auto[0]	auto[1]	70192	1			T1	10		T2	7		T14	837
all_values[30]	auto[1]	auto[1]	auto[1]	69345	1			T1	6		T2	6		T14	784
all_values[31]	auto[0]	auto[0]	auto[0]	2616341	1			T23	24726		T24	416		T25	204
all_values[31]	auto[0]	auto[0]	auto[1]	4784848	1			T26	52		T27	96		T1	150
all_values[31]	auto[0]	auto[1]	auto[0]	523895	1			T26	8		T27	11		T1	8
all_values[31]	auto[0]	auto[1]	auto[1]	4702580	1			T26	34		T27	118		T1	156
all_values[31]	auto[1]	auto[0]	auto[1]	70159	1			T1	9		T2	11		T14	786
all_values[31]	auto[1]	auto[1]	auto[1]	69149	1			T1	9		T2	2		T14	756

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal