Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[1]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[2]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[3]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[4]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[5]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[6]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[7]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[8]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[9]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[10]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[11]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[12]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[13]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[14]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[15]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[16]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[17]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[18]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[19]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[20]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[21]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[22]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[23]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[24]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[25]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[26]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[27]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[28]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[29]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[30]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[31]	12546914	1			T23	24726		T24	800		T25	401

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236633624

1

T23

390696

T24

20381

T25

10160

auto[1]

164867624

1

T23

400536

T24

5219

T25

2672

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

323099674

1

T23

791232

T24

19508

T25

9176

auto[1]

78401574

1

T24

6092

T25

3656

T1

4268

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300101112

1

T23

791232

T24

12667

T25

6655

auto[1]

101400136

1

T24

12933

T25

6177

T1

5477

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4651966	1			T23	12430		T24	343		T25	102
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3500232	1			T23	12296		T24	31		T25	8
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1234639	1			T24	70		T25	25		T1	73
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1519668	1			T24	233		T25	173		T1	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	423657	1			T24	43		T25	18		T1	112
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1216752	1			T24	80		T25	75		T1	89
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4636162	1			T23	12171		T24	354		T25	169
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3505322	1			T23	12555		T24	59		T25	10
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1232859	1			T24	129		T25	66		T1	49
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1522116	1			T24	177		T25	111		T1	1
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	424789	1			T24	24		T25	7		T1	118
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1225666	1			T24	57		T25	38		T1	66
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4635950	1			T23	12087		T24	247		T25	156
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3502937	1			T23	12639		T24	29		T25	16
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1232593	1			T24	90		T25	47		T1	96
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1523406	1			T24	290		T25	131		T1	5
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	426600	1			T24	42		T25	14		T1	110
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1225428	1			T24	102		T25	37		T1	58
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4641824	1			T23	14028		T24	255		T25	136
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3506240	1			T23	10698		T24	36		T25	7
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1231445	1			T24	106		T25	38		T1	96
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1523550	1			T24	243		T25	142		T1	1
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	426630	1			T24	37		T25	16		T1	99
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1217225	1			T24	123		T25	62		T1	31
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4633019	1			T23	12467		T24	247		T25	102
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3512483	1			T23	12259		T24	30		T25	16
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1235013	1			T24	101		T25	61		T1	54
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1517029	1			T24	281		T25	152		T1	7
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	427003	1			T24	37		T25	18		T1	92
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1222367	1			T24	104		T25	52		T1	79
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4643410	1			T23	11734		T24	225		T25	139
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3505718	1			T23	12992		T24	26		T25	16
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1230828	1			T24	95		T25	60		T1	77
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1518104	1			T24	324		T25	113		T1	3
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	423253	1			T24	46		T25	9		T1	104
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1225601	1			T24	84		T25	64		T1	73
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4636448	1			T23	12608		T24	287		T25	104
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3512461	1			T23	12118		T24	38		T25	13
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1231229	1			T24	64		T25	76		T1	78
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1521795	1			T24	293		T25	143		T1	5
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	423497	1			T24	34		T25	17		T1	111
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1221484	1			T24	84		T25	48		T1	59
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4644956	1			T23	11821		T24	226		T25	123
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3500666	1			T23	12905		T24	25		T25	18
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1233428	1			T24	122		T25	22		T1	93
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1524195	1			T24	298		T25	165		T11	21
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	425086	1			T24	47		T25	17		T1	104
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1218583	1			T24	82		T25	56		T1	26
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4632060	1			T23	10902		T24	313		T25	105
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3509646	1			T23	13824		T24	28		T25	16
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1235777	1			T24	99		T25	65		T1	91
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1521549	1			T24	248		T25	139		T1	3
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	423722	1			T24	39		T25	20		T1	80
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1224160	1			T24	73		T25	56		T1	32
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4642125	1			T23	12267		T24	263		T25	113
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3506648	1			T23	12459		T24	29		T25	8
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1229340	1			T24	118		T25	37		T1	73
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1523956	1			T24	278		T25	180		T1	4
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	423837	1			T24	37		T25	22		T1	71
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1221008	1			T24	75		T25	41		T1	79
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4636544	1			T23	12394		T24	191		T25	99
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3510194	1			T23	12332		T24	28		T25	16
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1229216	1			T24	83		T25	34		T1	49
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1525666	1			T24	340		T25	150		T1	7
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	425813	1			T24	49		T25	11		T1	149
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1219481	1			T24	109		T25	91		T1	59
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4641362	1			T23	12104		T24	282		T25	141
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3508063	1			T23	12622		T24	29		T25	15
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1231696	1			T24	91		T25	48		T1	30
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1520678	1			T24	246		T25	137		T1	12
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	424367	1			T24	41		T25	13		T1	132
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1220748	1			T24	111		T25	47		T1	86
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4639926	1			T23	11272		T24	285		T25	124
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3505407	1			T23	13454		T24	31		T25	14
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1229964	1			T24	83		T25	107		T1	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1525165	1			T24	280		T25	104		T1	7
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	424317	1			T24	29		T25	14		T1	144
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1222135	1			T24	92		T25	38		T1	83
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4652100	1			T23	13459		T24	345		T25	211
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3497986	1			T23	11267		T24	41		T25	18
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1230856	1			T24	89		T25	46		T1	45
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1522825	1			T24	232		T25	82		T1	2
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	420212	1			T24	30		T25	5		T1	79
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1222935	1			T24	63		T25	39		T1	78
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4638263	1			T23	12170		T24	274		T25	95
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3504606	1			T23	12556		T24	37		T25	13
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1235243	1			T24	90		T25	39		T1	105
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1519428	1			T24	274		T25	155		T1	1
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	424735	1			T24	34		T25	16		T1	70
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1224639	1			T24	91		T25	83		T1	12
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4630251	1			T23	11468		T24	258		T25	120
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3514312	1			T23	13258		T24	25		T25	14
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1226303	1			T24	91		T25	51		T1	77
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1521287	1			T24	285		T25	137		T1	7
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	427402	1			T24	30		T25	11		T1	101
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1227359	1			T24	111		T25	68		T1	67
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4656583	1			T23	13062		T24	231		T25	123
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3496097	1			T23	11664		T24	23		T25	19
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1230660	1			T24	68		T25	94		T1	68
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1523290	1			T24	341		T25	116		T1	6
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	424564	1			T24	39		T25	5		T1	86
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1215720	1			T24	98		T25	44		T1	65
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4654602	1			T23	11324		T24	320		T25	119
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3504930	1			T23	13402		T24	22		T25	15
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1228206	1			T24	91		T25	77		T1	39
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1520893	1			T24	240		T25	99		T1	4
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	423600	1			T24	22		T25	16		T1	103
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1214683	1			T24	105		T25	75		T1	68
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4631492	1			T23	12148		T24	243		T25	199
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3518438	1			T23	12578		T24	37		T25	10
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1230108	1			T24	119		T25	40		T1	77
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1525080	1			T24	298		T25	120		T1	4
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	424393	1			T24	38		T25	10		T1	106
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1217403	1			T24	65		T25	22		T1	50
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4641394	1			T23	12176		T24	275		T25	156
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3510222	1			T23	12550		T24	45		T25	22
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1230519	1			T24	114		T25	85		T1	68
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1523183	1			T24	220		T25	69		T1	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	424614	1			T24	29		T25	10		T1	127
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1216982	1			T24	117		T25	59		T1	73
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4646161	1			T23	12280		T24	261		T25	161
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3507002	1			T23	12446		T24	33		T25	23
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1226696	1			T24	116		T25	99		T1	99
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1526541	1			T24	281		T25	55		T1	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	425449	1			T24	29		T25	4		T1	74
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1215065	1			T24	80		T25	59		T1	49
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4649227	1			T23	12326		T24	276		T25	151
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3505226	1			T23	12400		T24	28		T25	19
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1228037	1			T24	95		T25	62		T1	105
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1524833	1			T24	247		T25	96		T1	3
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	422555	1			T24	40		T25	18		T1	34
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1217036	1			T24	114		T25	55		T1	73
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4642062	1			T23	12174		T24	324		T25	91
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3509135	1			T23	12552		T24	28		T25	18
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1228096	1			T24	100		T25	42		T1	44
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1524824	1			T24	242		T25	134		T1	2
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	422945	1			T24	33		T25	16		T1	114
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1219852	1			T24	73		T25	100		T1	57
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4629830	1			T23	12155		T24	275		T25	145
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3517915	1			T23	12571		T24	31		T25	17
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1220756	1			T24	112		T25	80		T1	36
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1530321	1			T24	255		T25	103		T1	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	428628	1			T24	32		T25	9		T1	133
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1219464	1			T24	95		T25	47		T1	76
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4646031	1			T23	13409		T24	339		T25	114
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3499108	1			T23	11317		T24	24		T25	15
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1224011	1			T24	84		T25	65		T1	55
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1530870	1			T24	252		T25	110		T1	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	423858	1			T24	40		T25	18		T1	130
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1223036	1			T24	61		T25	79		T1	74
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4644960	1			T23	11983		T24	299		T25	149
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3508734	1			T23	12743		T24	35		T25	15
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1226384	1			T24	89		T25	36		T1	80
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1526543	1			T24	240		T25	148		T11	49
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	423685	1			T24	39		T25	11		T1	79
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1216608	1			T24	98		T25	42		T1	60
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4639631	1			T23	11234		T24	221		T25	159
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3506710	1			T23	13492		T24	20		T25	19
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1229229	1			T24	88		T25	63		T1	54
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1528557	1			T24	294		T25	128		T1	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	425127	1			T24	44		T25	5		T1	94
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1217660	1			T24	133		T25	27		T1	68
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4632890	1			T23	10932		T24	265		T25	135
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3512969	1			T23	13794		T24	26		T25	15
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1227213	1			T24	101		T25	67		T1	63
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1531130	1			T24	251		T25	123		T1	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	426492	1			T24	31		T25	21		T1	137
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1216220	1			T24	126		T25	40		T1	76
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4632871	1			T23	12195		T24	235		T25	85
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3515029	1			T23	12531		T24	40		T25	7
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1226704	1			T24	84		T25	52		T1	67
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1530896	1			T24	300		T25	155		T1	6
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	422203	1			T24	32		T25	21		T1	82
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1219211	1			T24	109		T25	81		T1	87
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4634350	1			T23	13073		T24	211		T25	170
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3515004	1			T23	11653		T24	21		T25	21
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1228076	1			T24	89		T25	73		T1	92
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1525019	1			T24	306		T25	76		T1	4
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	424527	1			T24	47		T25	9		T1	80
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1219938	1			T24	126		T25	52		T1	66
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4651332	1			T23	12310		T24	266		T25	142
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3499744	1			T23	12416		T24	39		T25	12
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1230626	1			T24	78		T25	63		T1	44
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1516858	1			T24	271		T25	115		T1	5
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	425395	1			T24	31		T25	18		T1	101
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1222959	1			T24	115		T25	51		T1	75
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4647083	1			T23	12533		T24	203		T25	149
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3501178	1			T23	12193		T24	20		T25	14
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1228135	1			T24	85		T25	69		T1	69
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1523619	1			T24	348		T25	123		T1	5
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	426618	1			T24	42		T25	7		T1	106
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1220281	1			T24	102		T25	39		T1	93

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal