Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[1]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[2]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[3]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[4]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[5]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[6]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[7]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[8]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[9]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[10]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[11]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[12]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[13]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[14]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[15]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[16]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[17]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[18]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[19]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[20]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[21]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[22]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[23]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[24]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[25]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[26]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[27]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[28]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[29]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[30]	12546914	1			T23	24726		T24	800		T25	401
bins_for_gpio_bits[31]	12546914	1			T23	24726		T24	800		T25	401

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236633624

1

T23

390696

T24

20381

T25

10160

auto[1]

164867624

1

T23

400536

T24

5219

T25

2672

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236625669

1

T23

390696

T24

20373

T25

10160

auto[1]

164875579

1

T23

400536

T24

5227

T25

2672

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7187634	1			T23	12430		T24	631		T25	291
bins_for_gpio_bits[0]	auto[0]	auto[1]	218371	1			T24	15		T25	9		T1	8
bins_for_gpio_bits[0]	auto[1]	auto[0]	218639	1			T24	15		T25	9		T1	8
bins_for_gpio_bits[0]	auto[1]	auto[1]	4922270	1			T23	12296		T24	139		T25	92
bins_for_gpio_bits[1]	auto[0]	auto[0]	7172238	1			T23	12171		T24	646		T25	338
bins_for_gpio_bits[1]	auto[0]	auto[1]	218656	1			T24	13		T25	8		T1	8
bins_for_gpio_bits[1]	auto[1]	auto[0]	218899	1			T24	14		T25	8		T1	7
bins_for_gpio_bits[1]	auto[1]	auto[1]	4937121	1			T23	12555		T24	127		T25	47
bins_for_gpio_bits[2]	auto[0]	auto[0]	7172433	1			T23	12087		T24	607		T25	324
bins_for_gpio_bits[2]	auto[0]	auto[1]	219250	1			T24	19		T25	10		T1	12
bins_for_gpio_bits[2]	auto[1]	auto[0]	219516	1			T24	20		T25	10		T1	12
bins_for_gpio_bits[2]	auto[1]	auto[1]	4935715	1			T23	12639		T24	154		T25	57
bins_for_gpio_bits[3]	auto[0]	auto[0]	7178296	1			T23	14028		T24	582		T25	305
bins_for_gpio_bits[3]	auto[0]	auto[1]	218277	1			T24	22		T25	11		T1	15
bins_for_gpio_bits[3]	auto[1]	auto[0]	218523	1			T24	22		T25	11		T1	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	4931818	1			T23	10698		T24	174		T25	74
bins_for_gpio_bits[4]	auto[0]	auto[0]	7166435	1			T23	12467		T24	612		T25	307
bins_for_gpio_bits[4]	auto[0]	auto[1]	218363	1			T24	17		T25	8		T1	10
bins_for_gpio_bits[4]	auto[1]	auto[0]	218626	1			T24	17		T25	8		T1	10
bins_for_gpio_bits[4]	auto[1]	auto[1]	4943490	1			T23	12259		T24	154		T25	78
bins_for_gpio_bits[5]	auto[0]	auto[0]	7173492	1			T23	11734		T24	627		T25	304
bins_for_gpio_bits[5]	auto[0]	auto[1]	218620	1			T24	17		T25	8		T1	9
bins_for_gpio_bits[5]	auto[1]	auto[0]	218850	1			T24	17		T25	8		T1	9
bins_for_gpio_bits[5]	auto[1]	auto[1]	4935952	1			T23	12992		T24	139		T25	81
bins_for_gpio_bits[6]	auto[0]	auto[0]	7170483	1			T23	12608		T24	629		T25	312
bins_for_gpio_bits[6]	auto[0]	auto[1]	218755	1			T24	15		T25	11		T1	10
bins_for_gpio_bits[6]	auto[1]	auto[0]	218989	1			T24	15		T25	11		T1	10
bins_for_gpio_bits[6]	auto[1]	auto[1]	4938687	1			T23	12118		T24	141		T25	67
bins_for_gpio_bits[7]	auto[0]	auto[0]	7184415	1			T23	11821		T24	630		T25	301
bins_for_gpio_bits[7]	auto[0]	auto[1]	217918	1			T24	16		T25	9		T1	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	218164	1			T24	16		T25	9		T1	13
bins_for_gpio_bits[7]	auto[1]	auto[1]	4926417	1			T23	12905		T24	138		T25	82
bins_for_gpio_bits[8]	auto[0]	auto[0]	7169948	1			T23	10902		T24	648		T25	298
bins_for_gpio_bits[8]	auto[0]	auto[1]	219175	1			T24	12		T25	11		T1	14
bins_for_gpio_bits[8]	auto[1]	auto[0]	219438	1			T24	12		T25	11		T1	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	4938353	1			T23	13824		T24	128		T25	81
bins_for_gpio_bits[9]	auto[0]	auto[0]	7176364	1			T23	12267		T24	645		T25	321
bins_for_gpio_bits[9]	auto[0]	auto[1]	218816	1			T24	14		T25	9		T1	15
bins_for_gpio_bits[9]	auto[1]	auto[0]	219057	1			T24	14		T25	9		T1	14
bins_for_gpio_bits[9]	auto[1]	auto[1]	4932677	1			T23	12459		T24	127		T25	62
bins_for_gpio_bits[10]	auto[0]	auto[0]	7172321	1			T23	12394		T24	593		T25	270
bins_for_gpio_bits[10]	auto[0]	auto[1]	218861	1			T24	21		T25	13		T1	7
bins_for_gpio_bits[10]	auto[1]	auto[0]	219105	1			T24	21		T25	13		T1	7
bins_for_gpio_bits[10]	auto[1]	auto[1]	4936627	1			T23	12332		T24	165		T25	105
bins_for_gpio_bits[11]	auto[0]	auto[0]	7175177	1			T23	12104		T24	599		T25	317
bins_for_gpio_bits[11]	auto[0]	auto[1]	218306	1			T24	20		T25	9		T1	7
bins_for_gpio_bits[11]	auto[1]	auto[0]	218559	1			T24	20		T25	9		T1	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	4934872	1			T23	12622		T24	161		T25	66
bins_for_gpio_bits[12]	auto[0]	auto[0]	7176910	1			T23	11272		T24	632		T25	325
bins_for_gpio_bits[12]	auto[0]	auto[1]	217918	1			T24	16		T25	10		T1	6
bins_for_gpio_bits[12]	auto[1]	auto[0]	218145	1			T24	16		T25	10		T1	6
bins_for_gpio_bits[12]	auto[1]	auto[1]	4933941	1			T23	13454		T24	136		T25	56
bins_for_gpio_bits[13]	auto[0]	auto[0]	7186501	1			T23	13459		T24	656		T25	331
bins_for_gpio_bits[13]	auto[0]	auto[1]	219041	1			T24	10		T25	8		T1	12
bins_for_gpio_bits[13]	auto[1]	auto[0]	219280	1			T24	10		T25	8		T1	12
bins_for_gpio_bits[13]	auto[1]	auto[1]	4922092	1			T23	11267		T24	124		T25	54
bins_for_gpio_bits[14]	auto[0]	auto[0]	7173660	1			T23	12170		T24	623		T25	277
bins_for_gpio_bits[14]	auto[0]	auto[1]	219009	1			T24	15		T25	12		T1	14
bins_for_gpio_bits[14]	auto[1]	auto[0]	219274	1			T24	15		T25	12		T1	13
bins_for_gpio_bits[14]	auto[1]	auto[1]	4934971	1			T23	12556		T24	147		T25	100
bins_for_gpio_bits[15]	auto[0]	auto[0]	7158841	1			T23	11468		T24	613		T25	295
bins_for_gpio_bits[15]	auto[0]	auto[1]	218743	1			T24	21		T25	13		T1	14
bins_for_gpio_bits[15]	auto[1]	auto[0]	219000	1			T24	21		T25	13		T1	14
bins_for_gpio_bits[15]	auto[1]	auto[1]	4950330	1			T23	13258		T24	145		T25	80
bins_for_gpio_bits[16]	auto[0]	auto[0]	7192064	1			T23	13062		T24	623		T25	327
bins_for_gpio_bits[16]	auto[0]	auto[1]	218183	1			T24	17		T25	6		T1	12
bins_for_gpio_bits[16]	auto[1]	auto[0]	218469	1			T24	17		T25	6		T1	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	4918198	1			T23	11664		T24	143		T25	62
bins_for_gpio_bits[17]	auto[0]	auto[0]	7185098	1			T23	11324		T24	632		T25	283
bins_for_gpio_bits[17]	auto[0]	auto[1]	218322	1			T24	18		T25	12		T1	10
bins_for_gpio_bits[17]	auto[1]	auto[0]	218603	1			T24	19		T25	12		T1	10
bins_for_gpio_bits[17]	auto[1]	auto[1]	4924891	1			T23	13402		T24	131		T25	94
bins_for_gpio_bits[18]	auto[0]	auto[0]	7167423	1			T23	12148		T24	640		T25	354
bins_for_gpio_bits[18]	auto[0]	auto[1]	218977	1			T24	20		T25	5		T1	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	219257	1			T24	20		T25	5		T1	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	4941257	1			T23	12578		T24	120		T25	37
bins_for_gpio_bits[19]	auto[0]	auto[0]	7176181	1			T23	12176		T24	589		T25	300
bins_for_gpio_bits[19]	auto[0]	auto[1]	218712	1			T24	20		T25	10		T1	8
bins_for_gpio_bits[19]	auto[1]	auto[0]	218915	1			T24	20		T25	10		T1	7
bins_for_gpio_bits[19]	auto[1]	auto[1]	4933106	1			T23	12550		T24	171		T25	81
bins_for_gpio_bits[20]	auto[0]	auto[0]	7180876	1			T23	12280		T24	642		T25	306
bins_for_gpio_bits[20]	auto[0]	auto[1]	218332	1			T24	16		T25	9		T1	16
bins_for_gpio_bits[20]	auto[1]	auto[0]	218522	1			T24	16		T25	9		T1	15
bins_for_gpio_bits[20]	auto[1]	auto[1]	4929184	1			T23	12446		T24	126		T25	77
bins_for_gpio_bits[21]	auto[0]	auto[0]	7183006	1			T23	12326		T24	595		T25	300
bins_for_gpio_bits[21]	auto[0]	auto[1]	218854	1			T24	23		T25	9		T1	16
bins_for_gpio_bits[21]	auto[1]	auto[0]	219091	1			T24	23		T25	9		T1	15
bins_for_gpio_bits[21]	auto[1]	auto[1]	4925963	1			T23	12400		T24	159		T25	83
bins_for_gpio_bits[22]	auto[0]	auto[0]	7176446	1			T23	12174		T24	650		T25	255
bins_for_gpio_bits[22]	auto[0]	auto[1]	218259	1			T24	16		T25	12		T1	9
bins_for_gpio_bits[22]	auto[1]	auto[0]	218536	1			T24	16		T25	12		T1	9
bins_for_gpio_bits[22]	auto[1]	auto[1]	4933673	1			T23	12552		T24	118		T25	122
bins_for_gpio_bits[23]	auto[0]	auto[0]	7162225	1			T23	12155		T24	623		T25	317
bins_for_gpio_bits[23]	auto[0]	auto[1]	218436	1			T24	18		T25	11		T1	6
bins_for_gpio_bits[23]	auto[1]	auto[0]	218682	1			T24	19		T25	11		T1	6
bins_for_gpio_bits[23]	auto[1]	auto[1]	4947571	1			T23	12571		T24	140		T25	62
bins_for_gpio_bits[24]	auto[0]	auto[0]	7181541	1			T23	13409		T24	662		T25	277
bins_for_gpio_bits[24]	auto[0]	auto[1]	219147	1			T24	13		T25	12		T1	11
bins_for_gpio_bits[24]	auto[1]	auto[0]	219371	1			T24	13		T25	12		T1	11
bins_for_gpio_bits[24]	auto[1]	auto[1]	4926855	1			T23	11317		T24	112		T25	100
bins_for_gpio_bits[25]	auto[0]	auto[0]	7179333	1			T23	11983		T24	610		T25	326
bins_for_gpio_bits[25]	auto[0]	auto[1]	218337	1			T24	18		T25	7		T1	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	218554	1			T24	18		T25	7		T1	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	4930690	1			T23	12743		T24	154		T25	61
bins_for_gpio_bits[26]	auto[0]	auto[0]	7178786	1			T23	11234		T24	580		T25	342
bins_for_gpio_bits[26]	auto[0]	auto[1]	218391	1			T24	23		T25	8		T1	9
bins_for_gpio_bits[26]	auto[1]	auto[0]	218631	1			T24	23		T25	8		T1	9
bins_for_gpio_bits[26]	auto[1]	auto[1]	4931106	1			T23	13492		T24	174		T25	43
bins_for_gpio_bits[27]	auto[0]	auto[0]	7172023	1			T23	10932		T24	592		T25	318
bins_for_gpio_bits[27]	auto[0]	auto[1]	218910	1			T24	24		T25	7		T1	10
bins_for_gpio_bits[27]	auto[1]	auto[0]	219210	1			T24	25		T25	7		T1	10
bins_for_gpio_bits[27]	auto[1]	auto[1]	4936771	1			T23	13794		T24	159		T25	69
bins_for_gpio_bits[28]	auto[0]	auto[0]	7171150	1			T23	12195		T24	597		T25	276
bins_for_gpio_bits[28]	auto[0]	auto[1]	219086	1			T24	21		T25	16		T1	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	219321	1			T24	22		T25	16		T1	12
bins_for_gpio_bits[28]	auto[1]	auto[1]	4937357	1			T23	12531		T24	160		T25	93
bins_for_gpio_bits[29]	auto[0]	auto[0]	7168491	1			T23	13073		T24	582		T25	311
bins_for_gpio_bits[29]	auto[0]	auto[1]	218709	1			T24	23		T25	8		T1	13
bins_for_gpio_bits[29]	auto[1]	auto[0]	218954	1			T24	24		T25	8		T1	13
bins_for_gpio_bits[29]	auto[1]	auto[1]	4940760	1			T23	11653		T24	171		T25	74
bins_for_gpio_bits[30]	auto[0]	auto[0]	7180003	1			T23	12310		T24	591		T25	309
bins_for_gpio_bits[30]	auto[0]	auto[1]	218535	1			T24	23		T25	11		T1	12
bins_for_gpio_bits[30]	auto[1]	auto[0]	218813	1			T24	24		T25	11		T1	12
bins_for_gpio_bits[30]	auto[1]	auto[1]	4929563	1			T23	12416		T24	162		T25	70
bins_for_gpio_bits[31]	auto[0]	auto[0]	7180359	1			T23	12533		T24	616		T25	334
bins_for_gpio_bits[31]	auto[0]	auto[1]	218247	1			T24	20		T25	7		T1	10
bins_for_gpio_bits[31]	auto[1]	auto[0]	218478	1			T24	20		T25	7		T1	10
bins_for_gpio_bits[31]	auto[1]	auto[1]	4929830	1			T23	12193		T24	144		T25	53