Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7433256 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5333716 |
1 |
|
|
T26 |
49 |
|
T27 |
163 |
|
T1 |
58 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12087939 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
679033 |
1 |
|
|
T26 |
3 |
|
T27 |
8 |
|
T1 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7468174 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5298798 |
1 |
|
|
T26 |
52 |
|
T27 |
117 |
|
T1 |
154 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2319032 |
1 |
|
|
T26 |
20 |
|
T27 |
30 |
|
T1 |
131 |
| auto[1] |
auto[0] |
auto[1] |
340919 |
1 |
|
|
T26 |
1 |
|
T1 |
3 |
|
T13 |
70 |
| auto[1] |
auto[1] |
auto[0] |
2300733 |
1 |
|
|
T26 |
29 |
|
T27 |
79 |
|
T1 |
18 |
| auto[1] |
auto[1] |
auto[1] |
338114 |
1 |
|
|
T26 |
2 |
|
T27 |
8 |
|
T1 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |