Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7471963 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5295009 |
1 |
|
|
T26 |
58 |
|
T27 |
106 |
|
T1 |
189 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10527311 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
2239661 |
1 |
|
|
T26 |
13 |
|
T27 |
75 |
|
T1 |
108 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7405185 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5361787 |
1 |
|
|
T26 |
26 |
|
T27 |
177 |
|
T1 |
121 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1581128 |
1 |
|
|
T26 |
3 |
|
T27 |
47 |
|
T1 |
5 |
| auto[1] |
auto[0] |
auto[1] |
1132496 |
1 |
|
|
T26 |
2 |
|
T27 |
43 |
|
T1 |
57 |
| auto[1] |
auto[1] |
auto[0] |
1540998 |
1 |
|
|
T26 |
10 |
|
T27 |
55 |
|
T1 |
8 |
| auto[1] |
auto[1] |
auto[1] |
1107165 |
1 |
|
|
T26 |
11 |
|
T27 |
32 |
|
T1 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |