Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7397957 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5369015 |
1 |
|
|
T26 |
73 |
|
T27 |
163 |
|
T1 |
133 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10547264 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
2219708 |
1 |
|
|
T26 |
30 |
|
T27 |
52 |
|
T1 |
92 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7465621 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5301351 |
1 |
|
|
T26 |
58 |
|
T27 |
90 |
|
T1 |
134 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1534481 |
1 |
|
|
T26 |
6 |
|
T27 |
25 |
|
T1 |
18 |
| auto[1] |
auto[0] |
auto[1] |
1105310 |
1 |
|
|
T26 |
10 |
|
T27 |
19 |
|
T1 |
57 |
| auto[1] |
auto[1] |
auto[0] |
1547162 |
1 |
|
|
T26 |
22 |
|
T27 |
13 |
|
T1 |
24 |
| auto[1] |
auto[1] |
auto[1] |
1114398 |
1 |
|
|
T26 |
20 |
|
T27 |
33 |
|
T1 |
35 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |