Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7429798 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5337174 |
1 |
|
|
T26 |
40 |
|
T27 |
141 |
|
T1 |
167 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10540532 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
2226440 |
1 |
|
|
T26 |
26 |
|
T27 |
47 |
|
T1 |
114 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7454215 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5312757 |
1 |
|
|
T26 |
52 |
|
T27 |
114 |
|
T1 |
146 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1532618 |
1 |
|
|
T26 |
17 |
|
T27 |
23 |
|
T1 |
21 |
| auto[1] |
auto[0] |
auto[1] |
1106479 |
1 |
|
|
T26 |
13 |
|
T27 |
14 |
|
T1 |
59 |
| auto[1] |
auto[1] |
auto[0] |
1553699 |
1 |
|
|
T26 |
9 |
|
T27 |
44 |
|
T1 |
11 |
| auto[1] |
auto[1] |
auto[1] |
1119961 |
1 |
|
|
T26 |
13 |
|
T27 |
33 |
|
T1 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |