Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7412197 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5354775 |
1 |
|
|
T26 |
42 |
|
T27 |
149 |
|
T1 |
150 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12085604 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
681368 |
1 |
|
|
T26 |
3 |
|
T27 |
11 |
|
T1 |
14 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7445794 |
1 |
|
|
T23 |
24726 |
|
T24 |
416 |
|
T25 |
204 |
| auto[1] |
5321178 |
1 |
|
|
T26 |
49 |
|
T27 |
122 |
|
T1 |
252 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2312520 |
1 |
|
|
T26 |
15 |
|
T27 |
58 |
|
T1 |
139 |
| auto[1] |
auto[0] |
auto[1] |
339193 |
1 |
|
|
T27 |
8 |
|
T1 |
10 |
|
T13 |
113 |
| auto[1] |
auto[1] |
auto[0] |
2327290 |
1 |
|
|
T26 |
31 |
|
T27 |
53 |
|
T1 |
99 |
| auto[1] |
auto[1] |
auto[1] |
342175 |
1 |
|
|
T26 |
3 |
|
T27 |
3 |
|
T1 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |