Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 944
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T761 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2133074657 Jun 23 05:27:39 PM PDT 24 Jun 23 05:27:40 PM PDT 24 148295717 ps
T90 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.397514582 Jun 23 05:27:41 PM PDT 24 Jun 23 05:27:43 PM PDT 24 32297617 ps
T762 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2381391173 Jun 23 05:27:40 PM PDT 24 Jun 23 05:27:42 PM PDT 24 32724405 ps
T763 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3797831596 Jun 23 05:27:29 PM PDT 24 Jun 23 05:27:31 PM PDT 24 54751971 ps
T764 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3647732904 Jun 23 05:27:36 PM PDT 24 Jun 23 05:27:38 PM PDT 24 20031660 ps
T765 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1407366948 Jun 23 05:27:30 PM PDT 24 Jun 23 05:27:31 PM PDT 24 25714125 ps
T766 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3502342059 Jun 23 05:27:45 PM PDT 24 Jun 23 05:27:46 PM PDT 24 18931125 ps
T767 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1256738435 Jun 23 05:27:39 PM PDT 24 Jun 23 05:27:40 PM PDT 24 19667588 ps
T768 /workspace/coverage/cover_reg_top/25.gpio_intr_test.1421312866 Jun 23 05:27:43 PM PDT 24 Jun 23 05:27:44 PM PDT 24 46357213 ps
T769 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2958680858 Jun 23 05:27:30 PM PDT 24 Jun 23 05:27:31 PM PDT 24 20725799 ps
T770 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2208381097 Jun 23 05:27:35 PM PDT 24 Jun 23 05:27:37 PM PDT 24 44729621 ps
T771 /workspace/coverage/cover_reg_top/26.gpio_intr_test.119319419 Jun 23 05:27:47 PM PDT 24 Jun 23 05:27:48 PM PDT 24 42584669 ps
T44 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1487954572 Jun 23 05:27:35 PM PDT 24 Jun 23 05:27:37 PM PDT 24 895894927 ps
T772 /workspace/coverage/cover_reg_top/8.gpio_intr_test.3637592276 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:35 PM PDT 24 12090841 ps
T773 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2682998067 Jun 23 05:27:42 PM PDT 24 Jun 23 05:27:45 PM PDT 24 2762405173 ps
T78 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.684684397 Jun 23 05:27:28 PM PDT 24 Jun 23 05:27:29 PM PDT 24 44463213 ps
T774 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2390715142 Jun 23 05:27:23 PM PDT 24 Jun 23 05:27:26 PM PDT 24 275945435 ps
T42 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1799005257 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:36 PM PDT 24 100319415 ps
T775 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.61841779 Jun 23 05:27:40 PM PDT 24 Jun 23 05:27:42 PM PDT 24 408207031 ps
T776 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1967241461 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 54619867 ps
T777 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1538522564 Jun 23 05:27:32 PM PDT 24 Jun 23 05:27:35 PM PDT 24 106584124 ps
T778 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.281262103 Jun 23 05:27:29 PM PDT 24 Jun 23 05:27:30 PM PDT 24 29027736 ps
T779 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1831863063 Jun 23 05:27:34 PM PDT 24 Jun 23 05:27:38 PM PDT 24 147937517 ps
T780 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1685404888 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:32 PM PDT 24 47489704 ps
T781 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2135870396 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 45628651 ps
T782 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1100374108 Jun 23 05:27:35 PM PDT 24 Jun 23 05:27:37 PM PDT 24 11379490 ps
T783 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3041945215 Jun 23 05:27:43 PM PDT 24 Jun 23 05:27:44 PM PDT 24 38324830 ps
T784 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1736187921 Jun 23 05:27:42 PM PDT 24 Jun 23 05:27:43 PM PDT 24 90858848 ps
T785 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2835056781 Jun 23 05:27:45 PM PDT 24 Jun 23 05:27:46 PM PDT 24 26861745 ps
T786 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1154498281 Jun 23 05:27:36 PM PDT 24 Jun 23 05:27:38 PM PDT 24 51570798 ps
T787 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2851952411 Jun 23 05:27:29 PM PDT 24 Jun 23 05:27:31 PM PDT 24 240421760 ps
T788 /workspace/coverage/cover_reg_top/36.gpio_intr_test.1088321911 Jun 23 05:27:44 PM PDT 24 Jun 23 05:27:45 PM PDT 24 49327949 ps
T789 /workspace/coverage/cover_reg_top/43.gpio_intr_test.2802048396 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:50 PM PDT 24 87147345 ps
T790 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1576994749 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 206269440 ps
T791 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.548621310 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:35 PM PDT 24 134526310 ps
T792 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2334379503 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 84720793 ps
T793 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.489737613 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:35 PM PDT 24 69215532 ps
T794 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.51435390 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:35 PM PDT 24 2825306188 ps
T795 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2690610328 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 178458470 ps
T796 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2657218324 Jun 23 05:27:30 PM PDT 24 Jun 23 05:27:32 PM PDT 24 21394472 ps
T797 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.765907422 Jun 23 05:27:26 PM PDT 24 Jun 23 05:27:28 PM PDT 24 31221711 ps
T79 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2293485743 Jun 23 05:27:39 PM PDT 24 Jun 23 05:27:40 PM PDT 24 18880169 ps
T798 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2691424755 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:53 PM PDT 24 128001684 ps
T799 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3060532893 Jun 23 05:27:43 PM PDT 24 Jun 23 05:27:46 PM PDT 24 129033568 ps
T800 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1445924755 Jun 23 05:27:39 PM PDT 24 Jun 23 05:27:41 PM PDT 24 92042025 ps
T801 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.323286445 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 45089091 ps
T802 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2244215615 Jun 23 05:27:41 PM PDT 24 Jun 23 05:27:45 PM PDT 24 458091615 ps
T803 /workspace/coverage/cover_reg_top/14.gpio_intr_test.1830763058 Jun 23 05:27:39 PM PDT 24 Jun 23 05:27:40 PM PDT 24 50989695 ps
T804 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2353104105 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:52 PM PDT 24 11105181 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3695311388 Jun 23 05:27:39 PM PDT 24 Jun 23 05:27:41 PM PDT 24 635279267 ps
T806 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.32404238 Jun 23 05:27:43 PM PDT 24 Jun 23 05:27:45 PM PDT 24 68646343 ps
T807 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2757756167 Jun 23 05:27:30 PM PDT 24 Jun 23 05:27:32 PM PDT 24 141818285 ps
T808 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.65547697 Jun 23 05:27:34 PM PDT 24 Jun 23 05:27:37 PM PDT 24 47371647 ps
T80 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3005826982 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:34 PM PDT 24 44208629 ps
T809 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2593063453 Jun 23 05:27:43 PM PDT 24 Jun 23 05:27:45 PM PDT 24 63021744 ps
T810 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3760724920 Jun 23 05:27:46 PM PDT 24 Jun 23 05:27:47 PM PDT 24 20587748 ps
T811 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1262934488 Jun 23 05:27:34 PM PDT 24 Jun 23 05:27:36 PM PDT 24 31942496 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_intr_test.878484971 Jun 23 05:27:35 PM PDT 24 Jun 23 05:27:37 PM PDT 24 21036603 ps
T813 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2755475328 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:35 PM PDT 24 18519432 ps
T814 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3253889740 Jun 23 05:27:29 PM PDT 24 Jun 23 05:27:30 PM PDT 24 38401197 ps
T815 /workspace/coverage/cover_reg_top/49.gpio_intr_test.3485009437 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:52 PM PDT 24 15010080 ps
T816 /workspace/coverage/cover_reg_top/44.gpio_intr_test.4274636557 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:50 PM PDT 24 42962693 ps
T817 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1226257312 Jun 23 05:27:34 PM PDT 24 Jun 23 05:27:36 PM PDT 24 43228597 ps
T818 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4083707677 Jun 23 05:27:32 PM PDT 24 Jun 23 05:27:36 PM PDT 24 338853949 ps
T819 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.830469410 Jun 23 05:27:41 PM PDT 24 Jun 23 05:27:43 PM PDT 24 33785423 ps
T820 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1211355161 Jun 23 05:27:37 PM PDT 24 Jun 23 05:27:39 PM PDT 24 29589326 ps
T821 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3318308204 Jun 23 05:27:36 PM PDT 24 Jun 23 05:27:38 PM PDT 24 15384979 ps
T822 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2762218557 Jun 23 05:27:41 PM PDT 24 Jun 23 05:27:42 PM PDT 24 45289212 ps
T81 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2461799885 Jun 23 05:27:25 PM PDT 24 Jun 23 05:27:26 PM PDT 24 45866408 ps
T823 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.954246186 Jun 23 05:27:36 PM PDT 24 Jun 23 05:27:38 PM PDT 24 92591456 ps
T824 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3923225252 Jun 23 05:27:24 PM PDT 24 Jun 23 05:27:25 PM PDT 24 211990239 ps
T825 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2632777771 Jun 23 05:27:46 PM PDT 24 Jun 23 05:27:47 PM PDT 24 19171772 ps
T826 /workspace/coverage/cover_reg_top/1.gpio_intr_test.391761890 Jun 23 05:27:32 PM PDT 24 Jun 23 05:27:34 PM PDT 24 27486301 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.966224406 Jun 23 05:27:41 PM PDT 24 Jun 23 05:27:43 PM PDT 24 82002703 ps
T828 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1940312981 Jun 23 05:27:32 PM PDT 24 Jun 23 05:27:34 PM PDT 24 27468560 ps
T829 /workspace/coverage/cover_reg_top/20.gpio_intr_test.564637456 Jun 23 05:27:42 PM PDT 24 Jun 23 05:27:43 PM PDT 24 12864677 ps
T830 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.723518867 Jun 23 05:27:43 PM PDT 24 Jun 23 05:27:47 PM PDT 24 191902433 ps
T831 /workspace/coverage/cover_reg_top/46.gpio_intr_test.2150335442 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:50 PM PDT 24 14980477 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.64794737 Jun 23 05:27:37 PM PDT 24 Jun 23 05:27:39 PM PDT 24 295530292 ps
T82 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1957439469 Jun 23 05:27:30 PM PDT 24 Jun 23 05:27:32 PM PDT 24 31788430 ps
T833 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1259034739 Jun 23 05:27:34 PM PDT 24 Jun 23 05:27:36 PM PDT 24 168491542 ps
T834 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3452656565 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 34825515 ps
T835 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2534911664 Jun 23 05:27:30 PM PDT 24 Jun 23 05:27:31 PM PDT 24 108790507 ps
T836 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.791482971 Jun 23 05:27:37 PM PDT 24 Jun 23 05:27:39 PM PDT 24 42513193 ps
T83 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1268072130 Jun 23 05:27:28 PM PDT 24 Jun 23 05:27:29 PM PDT 24 16832208 ps
T837 /workspace/coverage/cover_reg_top/37.gpio_intr_test.889054105 Jun 23 05:27:45 PM PDT 24 Jun 23 05:27:47 PM PDT 24 36402751 ps
T838 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2340642507 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:35 PM PDT 24 66138186 ps
T84 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3465346335 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:36 PM PDT 24 394648585 ps
T839 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.4128739848 Jun 23 05:27:28 PM PDT 24 Jun 23 05:27:29 PM PDT 24 195697655 ps
T840 /workspace/coverage/cover_reg_top/22.gpio_intr_test.2913030025 Jun 23 05:27:45 PM PDT 24 Jun 23 05:27:47 PM PDT 24 22655970 ps
T841 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2234322865 Jun 23 05:27:31 PM PDT 24 Jun 23 05:27:33 PM PDT 24 65105494 ps
T842 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3809521410 Jun 23 05:27:43 PM PDT 24 Jun 23 05:27:45 PM PDT 24 26868435 ps
T843 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1762664411 Jun 23 05:27:33 PM PDT 24 Jun 23 05:27:35 PM PDT 24 42141711 ps
T844 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.302262854 Jun 23 05:27:28 PM PDT 24 Jun 23 05:27:30 PM PDT 24 345801319 ps
T845 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.754633349 Jun 23 05:28:14 PM PDT 24 Jun 23 05:28:17 PM PDT 24 79610868 ps
T846 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2310976953 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 307174157 ps
T847 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.564128402 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 45510166 ps
T848 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2401489771 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:53 PM PDT 24 365324528 ps
T849 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2320184678 Jun 23 05:27:59 PM PDT 24 Jun 23 05:28:01 PM PDT 24 91720261 ps
T850 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3341582863 Jun 23 05:28:16 PM PDT 24 Jun 23 05:28:20 PM PDT 24 45225148 ps
T851 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2606168350 Jun 23 05:28:01 PM PDT 24 Jun 23 05:28:03 PM PDT 24 56667840 ps
T852 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3657774853 Jun 23 05:27:48 PM PDT 24 Jun 23 05:27:50 PM PDT 24 174287364 ps
T853 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4097061941 Jun 23 05:27:59 PM PDT 24 Jun 23 05:28:01 PM PDT 24 565892165 ps
T854 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520134116 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 95785382 ps
T855 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3323837423 Jun 23 05:27:53 PM PDT 24 Jun 23 05:27:55 PM PDT 24 106625654 ps
T856 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2520568961 Jun 23 05:27:56 PM PDT 24 Jun 23 05:27:58 PM PDT 24 33056285 ps
T857 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.35330966 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 144832486 ps
T858 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3946236392 Jun 23 05:28:08 PM PDT 24 Jun 23 05:28:10 PM PDT 24 229495065 ps
T859 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2780722834 Jun 23 05:27:57 PM PDT 24 Jun 23 05:27:58 PM PDT 24 200622534 ps
T860 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3955133056 Jun 23 05:28:08 PM PDT 24 Jun 23 05:28:10 PM PDT 24 49704673 ps
T861 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.465977418 Jun 23 05:28:05 PM PDT 24 Jun 23 05:28:07 PM PDT 24 68198318 ps
T862 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3354396214 Jun 23 05:27:57 PM PDT 24 Jun 23 05:27:58 PM PDT 24 59195564 ps
T863 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3833792561 Jun 23 05:27:58 PM PDT 24 Jun 23 05:28:00 PM PDT 24 86828724 ps
T864 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1417753292 Jun 23 05:27:59 PM PDT 24 Jun 23 05:28:01 PM PDT 24 285231895 ps
T865 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1642646542 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 87945945 ps
T866 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2488744654 Jun 23 05:28:02 PM PDT 24 Jun 23 05:28:03 PM PDT 24 183834175 ps
T867 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1261651131 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:03 PM PDT 24 93447438 ps
T868 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2522424502 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:01 PM PDT 24 28611373 ps
T869 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.44452934 Jun 23 05:28:04 PM PDT 24 Jun 23 05:28:06 PM PDT 24 71838272 ps
T870 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3116107203 Jun 23 05:27:53 PM PDT 24 Jun 23 05:27:55 PM PDT 24 237337949 ps
T871 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1217969297 Jun 23 05:27:50 PM PDT 24 Jun 23 05:27:52 PM PDT 24 103333725 ps
T872 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509061690 Jun 23 05:28:01 PM PDT 24 Jun 23 05:28:03 PM PDT 24 276362517 ps
T873 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3545233315 Jun 23 05:27:55 PM PDT 24 Jun 23 05:27:57 PM PDT 24 102759735 ps
T874 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1782815100 Jun 23 05:27:57 PM PDT 24 Jun 23 05:27:58 PM PDT 24 46428661 ps
T875 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3713931516 Jun 23 05:27:59 PM PDT 24 Jun 23 05:28:00 PM PDT 24 86501473 ps
T876 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1949171403 Jun 23 05:27:55 PM PDT 24 Jun 23 05:27:56 PM PDT 24 347449959 ps
T877 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1192231967 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:01 PM PDT 24 117359982 ps
T878 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4050216603 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:01 PM PDT 24 159981007 ps
T879 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2547949578 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 97961332 ps
T880 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2260561390 Jun 23 05:28:03 PM PDT 24 Jun 23 05:28:04 PM PDT 24 64216602 ps
T881 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.68520360 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:54 PM PDT 24 190653836 ps
T882 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4062384077 Jun 23 05:27:58 PM PDT 24 Jun 23 05:28:00 PM PDT 24 39171257 ps
T883 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1300779009 Jun 23 05:28:15 PM PDT 24 Jun 23 05:28:19 PM PDT 24 76938217 ps
T884 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.488642363 Jun 23 05:27:48 PM PDT 24 Jun 23 05:27:50 PM PDT 24 276203471 ps
T885 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.675315401 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:53 PM PDT 24 108810528 ps
T886 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3882813825 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:54 PM PDT 24 63352231 ps
T887 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3569767648 Jun 23 05:28:08 PM PDT 24 Jun 23 05:28:09 PM PDT 24 38905434 ps
T888 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2099093460 Jun 23 05:28:03 PM PDT 24 Jun 23 05:28:04 PM PDT 24 392679406 ps
T889 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2042493932 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:02 PM PDT 24 218795143 ps
T890 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.198175723 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:51 PM PDT 24 506597959 ps
T891 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3116091131 Jun 23 05:27:59 PM PDT 24 Jun 23 05:28:01 PM PDT 24 28046318 ps
T892 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2509516270 Jun 23 05:27:56 PM PDT 24 Jun 23 05:27:58 PM PDT 24 33736684 ps
T893 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1778669746 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:54 PM PDT 24 27356181 ps
T894 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1739764536 Jun 23 05:27:58 PM PDT 24 Jun 23 05:28:00 PM PDT 24 102796959 ps
T895 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3637266914 Jun 23 05:27:50 PM PDT 24 Jun 23 05:27:52 PM PDT 24 327242046 ps
T896 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2104890625 Jun 23 05:27:58 PM PDT 24 Jun 23 05:28:00 PM PDT 24 68588638 ps
T897 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.89521900 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:58 PM PDT 24 1258578324 ps
T898 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1510210457 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 273965728 ps
T899 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3051317117 Jun 23 05:28:06 PM PDT 24 Jun 23 05:28:07 PM PDT 24 30301806 ps
T900 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2768508156 Jun 23 05:28:06 PM PDT 24 Jun 23 05:28:08 PM PDT 24 88480305 ps
T901 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3998020744 Jun 23 05:28:06 PM PDT 24 Jun 23 05:28:08 PM PDT 24 75059009 ps
T902 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.72498078 Jun 23 05:28:05 PM PDT 24 Jun 23 05:28:07 PM PDT 24 90282143 ps
T903 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2623832666 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:54 PM PDT 24 109054560 ps
T904 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.466574272 Jun 23 05:28:03 PM PDT 24 Jun 23 05:28:04 PM PDT 24 282781686 ps
T905 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2435451671 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:51 PM PDT 24 162553966 ps
T906 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4100029681 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:02 PM PDT 24 86913082 ps
T907 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.653956040 Jun 23 05:27:56 PM PDT 24 Jun 23 05:27:58 PM PDT 24 178002257 ps
T908 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1589914373 Jun 23 05:27:58 PM PDT 24 Jun 23 05:28:00 PM PDT 24 76309019 ps
T909 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2477769625 Jun 23 05:28:17 PM PDT 24 Jun 23 05:28:21 PM PDT 24 205739607 ps
T910 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.163472679 Jun 23 05:27:56 PM PDT 24 Jun 23 05:27:58 PM PDT 24 56029372 ps
T911 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304342033 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:51 PM PDT 24 101889399 ps
T912 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.448965680 Jun 23 05:28:07 PM PDT 24 Jun 23 05:28:09 PM PDT 24 42078136 ps
T913 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3018681516 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:51 PM PDT 24 474419023 ps
T914 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.360180188 Jun 23 05:27:58 PM PDT 24 Jun 23 05:28:00 PM PDT 24 438864500 ps
T915 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1614794579 Jun 23 05:27:56 PM PDT 24 Jun 23 05:27:57 PM PDT 24 21592126 ps
T916 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1442020026 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:53 PM PDT 24 108034944 ps
T917 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3855449633 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:53 PM PDT 24 303541235 ps
T918 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1207754655 Jun 23 05:27:58 PM PDT 24 Jun 23 05:27:59 PM PDT 24 44712315 ps
T919 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1550096185 Jun 23 05:27:55 PM PDT 24 Jun 23 05:27:56 PM PDT 24 74638559 ps
T920 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1350908343 Jun 23 05:28:04 PM PDT 24 Jun 23 05:28:05 PM PDT 24 242114550 ps
T921 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3939604707 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:50 PM PDT 24 114867791 ps
T922 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.170075043 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:54 PM PDT 24 108347247 ps
T923 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.526780431 Jun 23 05:28:01 PM PDT 24 Jun 23 05:28:03 PM PDT 24 91666041 ps
T924 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1232298068 Jun 23 05:27:52 PM PDT 24 Jun 23 05:27:54 PM PDT 24 196560547 ps
T925 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1489983299 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 135605917 ps
T926 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4185024534 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:03 PM PDT 24 153394286 ps
T927 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3280865511 Jun 23 05:27:57 PM PDT 24 Jun 23 05:27:58 PM PDT 24 425387215 ps
T928 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2842784251 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:53 PM PDT 24 41353188 ps
T929 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.307517390 Jun 23 05:27:55 PM PDT 24 Jun 23 05:27:56 PM PDT 24 169114000 ps
T930 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2274021344 Jun 23 05:27:57 PM PDT 24 Jun 23 05:27:59 PM PDT 24 182580984 ps
T931 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2897132784 Jun 23 05:28:15 PM PDT 24 Jun 23 05:28:18 PM PDT 24 77443581 ps
T932 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1431817393 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:56 PM PDT 24 264456673 ps
T933 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.174541808 Jun 23 05:28:00 PM PDT 24 Jun 23 05:28:02 PM PDT 24 63197131 ps
T934 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.571616316 Jun 23 05:28:13 PM PDT 24 Jun 23 05:28:14 PM PDT 24 72221091 ps
T935 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4260552062 Jun 23 05:28:04 PM PDT 24 Jun 23 05:28:05 PM PDT 24 28084880 ps
T936 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.81555940 Jun 23 05:27:54 PM PDT 24 Jun 23 05:27:55 PM PDT 24 32635229 ps
T937 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1046889168 Jun 23 05:28:14 PM PDT 24 Jun 23 05:28:15 PM PDT 24 78752016 ps
T938 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3170917991 Jun 23 05:27:51 PM PDT 24 Jun 23 05:27:53 PM PDT 24 34737795 ps
T939 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2700193099 Jun 23 05:27:59 PM PDT 24 Jun 23 05:28:01 PM PDT 24 77876588 ps
T940 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2477174424 Jun 23 05:27:57 PM PDT 24 Jun 23 05:27:59 PM PDT 24 43114415 ps
T941 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.440833149 Jun 23 05:27:53 PM PDT 24 Jun 23 05:27:54 PM PDT 24 32569591 ps
T942 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1103860320 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:51 PM PDT 24 252701949 ps
T943 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.738026548 Jun 23 05:27:49 PM PDT 24 Jun 23 05:27:50 PM PDT 24 71068300 ps
T944 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1247085399 Jun 23 05:28:01 PM PDT 24 Jun 23 05:28:03 PM PDT 24 24163558 ps

Test location /workspace/coverage/default/1.gpio_full_random.981475826
Short name T2
Test name
Test status
Simulation time 383145248 ps
CPU time 1 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:16 PM PDT 24
Peak memory 196720 kb
Host smart-2542f5b1-dc91-4118-9b1d-499379fd5a1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981475826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.981475826
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.235799708
Short name T59
Test name
Test status
Simulation time 63854418 ps
CPU time 2.5 seconds
Started Jun 23 05:29:40 PM PDT 24
Finished Jun 23 05:29:43 PM PDT 24
Peak memory 198152 kb
Host smart-04cf3d48-e7ae-4caa-8fdf-3d1da02799cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235799708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.235799708
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.1325722663
Short name T30
Test name
Test status
Simulation time 548490985175 ps
CPU time 1575.56 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:55:39 PM PDT 24
Peak memory 198224 kb
Host smart-548c782e-1e8f-43ae-859d-694556d98779
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1325722663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.1325722663
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3267450400
Short name T1
Test name
Test status
Simulation time 148939802 ps
CPU time 1.31 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 198008 kb
Host smart-b2f3ac4a-d36d-43b2-a911-ed797d3eeec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267450400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3267450400
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1427371684
Short name T16
Test name
Test status
Simulation time 36955222 ps
CPU time 0.82 seconds
Started Jun 23 05:28:12 PM PDT 24
Finished Jun 23 05:28:14 PM PDT 24
Peak memory 213680 kb
Host smart-7534409e-a25c-448f-b913-a340bc377722
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427371684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1427371684
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3828452617
Short name T69
Test name
Test status
Simulation time 40039759 ps
CPU time 0.62 seconds
Started Jun 23 05:27:38 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 194692 kb
Host smart-ac29a8c1-f000-4421-bb71-d6afd41744f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828452617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3828452617
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1539793647
Short name T41
Test name
Test status
Simulation time 83637416 ps
CPU time 1.15 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 197872 kb
Host smart-e7eac430-53a0-49fd-aad9-adee355783e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539793647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1539793647
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.4233100866
Short name T233
Test name
Test status
Simulation time 41950910 ps
CPU time 0.57 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:20 PM PDT 24
Peak memory 193828 kb
Host smart-4362ede8-10ad-4c45-9c74-244b80df2c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233100866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.4233100866
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_stress_all.4047092643
Short name T14
Test name
Test status
Simulation time 12191209597 ps
CPU time 176.24 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:32:11 PM PDT 24
Peak memory 198076 kb
Host smart-e1a16c7e-4007-4cd7-b3d2-c616e8650ed5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047092643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.4047092643
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3657900446
Short name T77
Test name
Test status
Simulation time 29527091 ps
CPU time 0.85 seconds
Started Jun 23 05:27:26 PM PDT 24
Finished Jun 23 05:27:27 PM PDT 24
Peak memory 195828 kb
Host smart-f0186086-215d-48d3-90bf-49b8acb39245
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657900446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3657900446
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.236502938
Short name T72
Test name
Test status
Simulation time 91797861 ps
CPU time 0.71 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 194628 kb
Host smart-011615e6-d857-4394-94fa-f4166e42c435
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236502938 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 10.gpio_same_csr_outstanding.236502938
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1172780371
Short name T33
Test name
Test status
Simulation time 70475350 ps
CPU time 1.19 seconds
Started Jun 23 05:27:38 PM PDT 24
Finished Jun 23 05:27:40 PM PDT 24
Peak memory 197836 kb
Host smart-910b48e2-c19c-42f5-82b6-2e7e624d935c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172780371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1172780371
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2903340874
Short name T43
Test name
Test status
Simulation time 121262453 ps
CPU time 1.46 seconds
Started Jun 23 05:27:24 PM PDT 24
Finished Jun 23 05:27:26 PM PDT 24
Peak memory 197816 kb
Host smart-65f904bf-9b79-427f-9721-327d0a7988a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903340874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2903340874
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.51435390
Short name T794
Test name
Test status
Simulation time 2825306188 ps
CPU time 2.32 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 196808 kb
Host smart-98f850e6-0892-4598-afeb-5a436d8e8afe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51435390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.51435390
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.684684397
Short name T78
Test name
Test status
Simulation time 44463213 ps
CPU time 0.6 seconds
Started Jun 23 05:27:28 PM PDT 24
Finished Jun 23 05:27:29 PM PDT 24
Peak memory 194844 kb
Host smart-4326a7ac-dda7-4f4b-8161-9a0236471e26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684684397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.684684397
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.3923225252
Short name T824
Test name
Test status
Simulation time 211990239 ps
CPU time 1.02 seconds
Started Jun 23 05:27:24 PM PDT 24
Finished Jun 23 05:27:25 PM PDT 24
Peak memory 197620 kb
Host smart-18b1a06c-7b4f-4de5-afcf-a5d6fa79bf00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923225252 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.3923225252
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2461799885
Short name T81
Test name
Test status
Simulation time 45866408 ps
CPU time 0.58 seconds
Started Jun 23 05:27:25 PM PDT 24
Finished Jun 23 05:27:26 PM PDT 24
Peak memory 193064 kb
Host smart-6ddfd485-8f56-4a43-bca1-480bb7eceb54
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461799885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2461799885
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1422384328
Short name T717
Test name
Test status
Simulation time 12825348 ps
CPU time 0.66 seconds
Started Jun 23 05:27:25 PM PDT 24
Finished Jun 23 05:27:27 PM PDT 24
Peak memory 193476 kb
Host smart-ebbccf92-17ab-482e-b0e3-c71d227dd45b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422384328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1422384328
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.765907422
Short name T797
Test name
Test status
Simulation time 31221711 ps
CPU time 0.65 seconds
Started Jun 23 05:27:26 PM PDT 24
Finished Jun 23 05:27:28 PM PDT 24
Peak memory 195052 kb
Host smart-38d9ad24-3b93-4c97-a8d2-59790f5f0663
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765907422 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.765907422
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2390715142
Short name T774
Test name
Test status
Simulation time 275945435 ps
CPU time 1.45 seconds
Started Jun 23 05:27:23 PM PDT 24
Finished Jun 23 05:27:26 PM PDT 24
Peak memory 197788 kb
Host smart-3b3b173d-b4b9-4f8a-9626-8c65c7a18c64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390715142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2390715142
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2196962935
Short name T757
Test name
Test status
Simulation time 18384619 ps
CPU time 0.66 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:32 PM PDT 24
Peak memory 195180 kb
Host smart-1f8c5967-296a-431f-b26f-c59bcaed450c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196962935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2196962935
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1967241461
Short name T776
Test name
Test status
Simulation time 54619867 ps
CPU time 1.33 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 196256 kb
Host smart-e93341ea-4c35-4770-90f1-bfc2a55f85da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967241461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1967241461
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1762664411
Short name T843
Test name
Test status
Simulation time 42141711 ps
CPU time 0.64 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 194484 kb
Host smart-de2d40ea-1b9e-457e-8fbd-1596eed1599b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762664411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1762664411
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.1538522564
Short name T777
Test name
Test status
Simulation time 106584124 ps
CPU time 0.93 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 197700 kb
Host smart-46ee4d67-1d0e-4345-a5e3-93d525e9d02d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538522564 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.1538522564
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.3253889740
Short name T814
Test name
Test status
Simulation time 38401197 ps
CPU time 0.61 seconds
Started Jun 23 05:27:29 PM PDT 24
Finished Jun 23 05:27:30 PM PDT 24
Peak memory 195208 kb
Host smart-6cbcbc75-cf84-47e0-806b-2116ff290220
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253889740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.3253889740
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.391761890
Short name T826
Test name
Test status
Simulation time 27486301 ps
CPU time 0.64 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:34 PM PDT 24
Peak memory 194044 kb
Host smart-eeaa0fef-abdc-48ea-ad11-6fd6194c1a89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391761890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.391761890
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.2958680858
Short name T769
Test name
Test status
Simulation time 20725799 ps
CPU time 0.68 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:31 PM PDT 24
Peak memory 195440 kb
Host smart-ba98a6c0-cd77-4d87-87c0-5a7ddd8a84c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958680858 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.2958680858
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2334379503
Short name T792
Test name
Test status
Simulation time 84720793 ps
CPU time 1.62 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 197868 kb
Host smart-9d9b2351-9243-4083-9eab-213ef82ff866
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334379503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2334379503
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.4128739848
Short name T839
Test name
Test status
Simulation time 195697655 ps
CPU time 1.52 seconds
Started Jun 23 05:27:28 PM PDT 24
Finished Jun 23 05:27:29 PM PDT 24
Peak memory 197836 kb
Host smart-5c799793-45d7-4f32-9bc9-eedd0a26f9bc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128739848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.4128739848
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.283480384
Short name T747
Test name
Test status
Simulation time 47685010 ps
CPU time 1.06 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 197688 kb
Host smart-2db9a675-1036-4a1e-bb93-1f2984bd3f00
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283480384 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.283480384
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.599839043
Short name T74
Test name
Test status
Simulation time 127967239 ps
CPU time 0.63 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:40 PM PDT 24
Peak memory 194652 kb
Host smart-0ab2d0a8-55d2-4988-a2db-dd0517268d91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599839043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.599839043
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.595684860
Short name T716
Test name
Test status
Simulation time 32319001 ps
CPU time 0.66 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 194140 kb
Host smart-746961a9-4ca7-4395-8b2f-19a0d4776890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595684860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.595684860
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.784144838
Short name T744
Test name
Test status
Simulation time 69153319 ps
CPU time 1.16 seconds
Started Jun 23 05:27:37 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 197864 kb
Host smart-3df64e23-934d-471b-b14f-031ac966eb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784144838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.784144838
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.917155853
Short name T760
Test name
Test status
Simulation time 65124017 ps
CPU time 0.84 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 196800 kb
Host smart-48d14931-fbbe-4f78-96b4-52e73cb87116
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917155853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.917155853
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.4240153678
Short name T720
Test name
Test status
Simulation time 55943791 ps
CPU time 0.92 seconds
Started Jun 23 05:27:42 PM PDT 24
Finished Jun 23 05:27:44 PM PDT 24
Peak memory 197572 kb
Host smart-100eabc0-0cc5-4649-89c2-4ab7776fea39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240153678 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.4240153678
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1100374108
Short name T782
Test name
Test status
Simulation time 11379490 ps
CPU time 0.63 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 193032 kb
Host smart-bb1ec78b-38a3-4e4e-924e-c085b151a41d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100374108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1100374108
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3647732904
Short name T764
Test name
Test status
Simulation time 20031660 ps
CPU time 0.63 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 193456 kb
Host smart-55e92df2-0ea4-401b-a90b-23cd863988e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647732904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3647732904
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1154498281
Short name T786
Test name
Test status
Simulation time 51570798 ps
CPU time 0.72 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 195256 kb
Host smart-bd2099c5-4348-4632-93cc-fc517ee6ef87
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154498281 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1154498281
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2516033553
Short name T739
Test name
Test status
Simulation time 2367694608 ps
CPU time 2.62 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 197888 kb
Host smart-623f276e-e1d8-4565-935f-8d045a411a87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516033553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2516033553
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.1925079101
Short name T104
Test name
Test status
Simulation time 78459275 ps
CPU time 1.17 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 197844 kb
Host smart-95d2a16f-ec56-4825-b453-4594b10a3c4f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925079101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.1925079101
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1211355161
Short name T820
Test name
Test status
Simulation time 29589326 ps
CPU time 0.91 seconds
Started Jun 23 05:27:37 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 197636 kb
Host smart-047f5359-01eb-4710-ba8d-2f44037818ea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211355161 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1211355161
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1736187921
Short name T784
Test name
Test status
Simulation time 90858848 ps
CPU time 0.56 seconds
Started Jun 23 05:27:42 PM PDT 24
Finished Jun 23 05:27:43 PM PDT 24
Peak memory 193112 kb
Host smart-c37bd2c5-d096-4338-98ed-9f7657da37ff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736187921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1736187921
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.878484971
Short name T812
Test name
Test status
Simulation time 21036603 ps
CPU time 0.58 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 193396 kb
Host smart-2ae79756-a15e-417d-9ff3-d73a37ea9e3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878484971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.878484971
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2554948603
Short name T68
Test name
Test status
Simulation time 40225837 ps
CPU time 0.68 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 194692 kb
Host smart-0afee7f5-cb48-47f5-88c5-974d4a00829e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554948603 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2554948603
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3598860230
Short name T740
Test name
Test status
Simulation time 331801366 ps
CPU time 2.1 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 197780 kb
Host smart-cb5b9348-18fd-45d6-bf81-37713fd7eeb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598860230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3598860230
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.64794737
Short name T832
Test name
Test status
Simulation time 295530292 ps
CPU time 1.17 seconds
Started Jun 23 05:27:37 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 197804 kb
Host smart-d17ba02e-a8b7-434e-a6e6-fce6053266d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64794737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.gpio_tl_intg_err.64794737
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2753773323
Short name T746
Test name
Test status
Simulation time 83877648 ps
CPU time 1.31 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 197884 kb
Host smart-f0eeb973-e47f-4e0c-96a3-05b1488e3d5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753773323 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2753773323
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3318308204
Short name T821
Test name
Test status
Simulation time 15384979 ps
CPU time 0.62 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 194704 kb
Host smart-9095d529-cc09-4e74-bac8-d4225cd6832b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318308204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3318308204
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1090555874
Short name T723
Test name
Test status
Simulation time 12942976 ps
CPU time 0.57 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 193404 kb
Host smart-48199514-cd7e-43fa-8a34-a1f669441458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090555874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1090555874
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2755475328
Short name T813
Test name
Test status
Simulation time 18519432 ps
CPU time 0.65 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 194348 kb
Host smart-4434f245-7c87-4b92-8f4d-8d94d04f04bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755475328 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2755475328
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2244215615
Short name T802
Test name
Test status
Simulation time 458091615 ps
CPU time 2.52 seconds
Started Jun 23 05:27:41 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 197752 kb
Host smart-ecf2007c-3b50-4b86-8759-c824f06b13f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244215615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2244215615
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.954246186
Short name T823
Test name
Test status
Simulation time 92591456 ps
CPU time 0.85 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 196820 kb
Host smart-4a54451a-cedc-49ee-b66f-099422067e1e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954246186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.954246186
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.61841779
Short name T775
Test name
Test status
Simulation time 408207031 ps
CPU time 0.96 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:42 PM PDT 24
Peak memory 197696 kb
Host smart-d9ca94e9-ad1c-41e4-9c86-f31fe902e87b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61841779 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.61841779
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1123851778
Short name T75
Test name
Test status
Simulation time 20725364 ps
CPU time 0.59 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:40 PM PDT 24
Peak memory 194632 kb
Host smart-f1eca6bb-98f3-45ca-bb57-62b76de21505
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123851778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1123851778
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.1830763058
Short name T803
Test name
Test status
Simulation time 50989695 ps
CPU time 0.58 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:40 PM PDT 24
Peak memory 193460 kb
Host smart-c3bb35ed-d34f-4ada-8553-6fd297f6c7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830763058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.1830763058
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3809521410
Short name T842
Test name
Test status
Simulation time 26868435 ps
CPU time 0.84 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 196412 kb
Host smart-744ca73f-f197-439b-b7d4-67d8353d9aab
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809521410 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3809521410
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.723518867
Short name T830
Test name
Test status
Simulation time 191902433 ps
CPU time 2.58 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 197800 kb
Host smart-6af481bd-6c17-4461-94fa-45d540d069ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723518867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.723518867
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1716863271
Short name T735
Test name
Test status
Simulation time 24670243 ps
CPU time 0.87 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:41 PM PDT 24
Peak memory 197688 kb
Host smart-257dc9e3-8ac5-4d44-aed8-1779055e0f3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716863271 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1716863271
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2258928780
Short name T752
Test name
Test status
Simulation time 76160086 ps
CPU time 0.6 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:42 PM PDT 24
Peak memory 194340 kb
Host smart-7b8854e7-62ac-4158-9d7c-e94fbd27f79e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258928780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2258928780
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.4122306673
Short name T730
Test name
Test status
Simulation time 20165239 ps
CPU time 0.69 seconds
Started Jun 23 05:27:37 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 193476 kb
Host smart-739a2622-253c-4a4a-8c30-ef0d4b903f67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122306673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.4122306673
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.397514582
Short name T90
Test name
Test status
Simulation time 32297617 ps
CPU time 0.67 seconds
Started Jun 23 05:27:41 PM PDT 24
Finished Jun 23 05:27:43 PM PDT 24
Peak memory 194540 kb
Host smart-5e189985-fb19-40cb-9fc6-4e955adb6558
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397514582 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.397514582
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.2588896571
Short name T729
Test name
Test status
Simulation time 170668096 ps
CPU time 3.03 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:43 PM PDT 24
Peak memory 197828 kb
Host smart-b1ef1b7f-c29e-47ee-9d5f-ee4adf5a9773
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588896571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.2588896571
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3695311388
Short name T805
Test name
Test status
Simulation time 635279267 ps
CPU time 0.88 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:41 PM PDT 24
Peak memory 196692 kb
Host smart-d2285e9c-c7c0-4c72-bdae-01946d3a6464
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695311388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3695311388
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2035358451
Short name T715
Test name
Test status
Simulation time 37307397 ps
CPU time 1.79 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:43 PM PDT 24
Peak memory 197884 kb
Host smart-bcf599d1-7de7-4cd1-914c-6fe28386666e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035358451 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2035358451
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.830469410
Short name T819
Test name
Test status
Simulation time 33785423 ps
CPU time 0.58 seconds
Started Jun 23 05:27:41 PM PDT 24
Finished Jun 23 05:27:43 PM PDT 24
Peak memory 194284 kb
Host smart-ceb8388f-2768-40f8-9d28-3a95f4505c94
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830469410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.830469410
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3079293197
Short name T733
Test name
Test status
Simulation time 78368470 ps
CPU time 0.61 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:44 PM PDT 24
Peak memory 193364 kb
Host smart-529ab28e-b279-4136-b513-2f8c66665aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079293197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3079293197
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3475993665
Short name T70
Test name
Test status
Simulation time 23115505 ps
CPU time 0.82 seconds
Started Jun 23 05:27:41 PM PDT 24
Finished Jun 23 05:27:42 PM PDT 24
Peak memory 196004 kb
Host smart-6e67a96e-d338-464e-affe-805cdf0cdf4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475993665 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3475993665
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1810530943
Short name T759
Test name
Test status
Simulation time 62424369 ps
CPU time 1.56 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:42 PM PDT 24
Peak memory 197804 kb
Host smart-adbf1bfc-e1c4-4611-b8b5-d9d895a000a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810530943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1810530943
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.966224406
Short name T827
Test name
Test status
Simulation time 82002703 ps
CPU time 1.18 seconds
Started Jun 23 05:27:41 PM PDT 24
Finished Jun 23 05:27:43 PM PDT 24
Peak memory 197836 kb
Host smart-4e3132d8-03ea-4ba3-a7c6-34af6c6d0e47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966224406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.966224406
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2762218557
Short name T822
Test name
Test status
Simulation time 45289212 ps
CPU time 0.78 seconds
Started Jun 23 05:27:41 PM PDT 24
Finished Jun 23 05:27:42 PM PDT 24
Peak memory 197692 kb
Host smart-1ebd4733-5802-4afd-a382-6a586c41b558
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762218557 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2762218557
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.632230408
Short name T732
Test name
Test status
Simulation time 14149682 ps
CPU time 0.62 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:41 PM PDT 24
Peak memory 193464 kb
Host smart-771f6f28-12fc-4c0e-a08a-e956c1804a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632230408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.632230408
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.233357153
Short name T71
Test name
Test status
Simulation time 98372735 ps
CPU time 0.74 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:41 PM PDT 24
Peak memory 196016 kb
Host smart-10a8f71a-3ed9-46fe-856b-e8dda3f1a291
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233357153 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.233357153
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2747066149
Short name T743
Test name
Test status
Simulation time 53563533 ps
CPU time 2.61 seconds
Started Jun 23 05:27:42 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 197808 kb
Host smart-f89a90b7-f6f5-43ca-94e2-6220ce0db8b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747066149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2747066149
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1445924755
Short name T800
Test name
Test status
Simulation time 92042025 ps
CPU time 1.19 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:41 PM PDT 24
Peak memory 197812 kb
Host smart-e71ffde6-3e80-48c8-9993-36ca14b5cbe9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445924755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1445924755
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2381391173
Short name T762
Test name
Test status
Simulation time 32724405 ps
CPU time 1.56 seconds
Started Jun 23 05:27:40 PM PDT 24
Finished Jun 23 05:27:42 PM PDT 24
Peak memory 197876 kb
Host smart-08cf881d-025e-44d7-9324-38818ecdc498
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381391173 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2381391173
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1256738435
Short name T767
Test name
Test status
Simulation time 19667588 ps
CPU time 0.65 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:40 PM PDT 24
Peak memory 195464 kb
Host smart-bed407a1-7992-44c3-8414-2a7b321629d3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256738435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1256738435
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3041945215
Short name T783
Test name
Test status
Simulation time 38324830 ps
CPU time 0.61 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:44 PM PDT 24
Peak memory 193472 kb
Host smart-007feb0d-af5f-420f-bae5-4e79ec8c891a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041945215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3041945215
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1986350365
Short name T89
Test name
Test status
Simulation time 117366828 ps
CPU time 0.78 seconds
Started Jun 23 05:27:37 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 196128 kb
Host smart-d7d8f138-3803-48ce-b4f6-6cef275f8100
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986350365 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1986350365
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.32404238
Short name T806
Test name
Test status
Simulation time 68646343 ps
CPU time 1.15 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 197836 kb
Host smart-3041f0b6-85ba-40f6-a925-41f1e2fb0df3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32404238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.32404238
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2133074657
Short name T761
Test name
Test status
Simulation time 148295717 ps
CPU time 1.19 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:40 PM PDT 24
Peak memory 197832 kb
Host smart-a1ff1716-bae2-4534-b497-7b06c79d70d1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133074657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2133074657
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.791482971
Short name T836
Test name
Test status
Simulation time 42513193 ps
CPU time 0.76 seconds
Started Jun 23 05:27:37 PM PDT 24
Finished Jun 23 05:27:39 PM PDT 24
Peak memory 197684 kb
Host smart-8de67fa0-cfee-448b-b89d-8c4b045f3c12
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791482971 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.791482971
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2293485743
Short name T79
Test name
Test status
Simulation time 18880169 ps
CPU time 0.63 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:40 PM PDT 24
Peak memory 195132 kb
Host smart-c0e18344-dee3-4371-a537-0331d3ef5fc0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293485743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2293485743
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3760724920
Short name T810
Test name
Test status
Simulation time 20587748 ps
CPU time 0.65 seconds
Started Jun 23 05:27:46 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 193412 kb
Host smart-87c478a2-7e50-4a50-bdca-3a6636564a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760724920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3760724920
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2593063453
Short name T809
Test name
Test status
Simulation time 63021744 ps
CPU time 0.81 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 196560 kb
Host smart-5bbf871d-6791-4205-986f-bdca09ee4b5f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593063453 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2593063453
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3060532893
Short name T799
Test name
Test status
Simulation time 129033568 ps
CPU time 2.33 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 197688 kb
Host smart-d8900d1c-228b-43e2-ab7e-0613ce8e5d35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060532893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3060532893
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2109631600
Short name T35
Test name
Test status
Simulation time 121778204 ps
CPU time 1.46 seconds
Started Jun 23 05:27:39 PM PDT 24
Finished Jun 23 05:27:41 PM PDT 24
Peak memory 197832 kb
Host smart-880e5c27-205d-4348-a6af-647d4af728b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109631600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2109631600
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.884363337
Short name T76
Test name
Test status
Simulation time 29925734 ps
CPU time 0.75 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 195772 kb
Host smart-8677ec47-03ea-428f-ab8e-4c26dcaa594c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884363337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.884363337
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.1269612311
Short name T103
Test name
Test status
Simulation time 450904479 ps
CPU time 3.5 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 196988 kb
Host smart-1aa70f7c-d0e7-474c-9698-165d4c0be71e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269612311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.1269612311
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3005826982
Short name T80
Test name
Test status
Simulation time 44208629 ps
CPU time 0.6 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:34 PM PDT 24
Peak memory 194120 kb
Host smart-4b2a2e64-32c4-483a-a566-cc1441ef1014
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005826982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3005826982
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1407366948
Short name T765
Test name
Test status
Simulation time 25714125 ps
CPU time 0.83 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:31 PM PDT 24
Peak memory 197620 kb
Host smart-fc452138-030d-4427-8cb6-7e80bc2d509c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407366948 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1407366948
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1957439469
Short name T82
Test name
Test status
Simulation time 31788430 ps
CPU time 0.64 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:32 PM PDT 24
Peak memory 194596 kb
Host smart-d90cfbf9-f292-4541-a0c6-5dacd7e1eacc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957439469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1957439469
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.782798417
Short name T756
Test name
Test status
Simulation time 16105471 ps
CPU time 0.62 seconds
Started Jun 23 05:27:28 PM PDT 24
Finished Jun 23 05:27:29 PM PDT 24
Peak memory 193536 kb
Host smart-352c76a2-2bd3-470f-a418-9ce4fec7931d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782798417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.782798417
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2135870396
Short name T781
Test name
Test status
Simulation time 45628651 ps
CPU time 0.66 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 194748 kb
Host smart-c35991e0-6f32-475a-83af-2a985d9a351e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135870396 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2135870396
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.1614574997
Short name T725
Test name
Test status
Simulation time 30878964 ps
CPU time 1.58 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 197832 kb
Host smart-f414f428-2cac-40b0-9924-b52cb6b1268c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614574997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.1614574997
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.2851952411
Short name T787
Test name
Test status
Simulation time 240421760 ps
CPU time 1.35 seconds
Started Jun 23 05:27:29 PM PDT 24
Finished Jun 23 05:27:31 PM PDT 24
Peak memory 197860 kb
Host smart-b923fbb5-c363-46fe-a2fa-7a80fad6fea6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851952411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.2851952411
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.564637456
Short name T829
Test name
Test status
Simulation time 12864677 ps
CPU time 0.6 seconds
Started Jun 23 05:27:42 PM PDT 24
Finished Jun 23 05:27:43 PM PDT 24
Peak memory 193456 kb
Host smart-c685dbf2-b338-4e23-b638-a848e5d7ccb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564637456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.564637456
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2835056781
Short name T785
Test name
Test status
Simulation time 26861745 ps
CPU time 0.6 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 194052 kb
Host smart-d0f2c9ad-9bcb-4d08-a630-a537d56b8a39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835056781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2835056781
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2913030025
Short name T840
Test name
Test status
Simulation time 22655970 ps
CPU time 0.71 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 193432 kb
Host smart-bdb055a9-3949-4335-97b3-6cd67a18f5cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913030025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2913030025
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3366914768
Short name T722
Test name
Test status
Simulation time 15830830 ps
CPU time 0.6 seconds
Started Jun 23 05:27:44 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 193424 kb
Host smart-8f65d94a-393c-4dbf-9f74-bc3857f2b6f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366914768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3366914768
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1882627123
Short name T758
Test name
Test status
Simulation time 14710712 ps
CPU time 0.61 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 194012 kb
Host smart-12894693-f302-4d13-b5f1-ef0196ddd30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882627123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1882627123
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1421312866
Short name T768
Test name
Test status
Simulation time 46357213 ps
CPU time 0.58 seconds
Started Jun 23 05:27:43 PM PDT 24
Finished Jun 23 05:27:44 PM PDT 24
Peak memory 193380 kb
Host smart-c7265b29-92bd-4ca5-b888-3e1b48c14a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421312866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1421312866
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.119319419
Short name T771
Test name
Test status
Simulation time 42584669 ps
CPU time 0.55 seconds
Started Jun 23 05:27:47 PM PDT 24
Finished Jun 23 05:27:48 PM PDT 24
Peak memory 194068 kb
Host smart-1b027897-c0b7-4e56-9d9c-b9315007302e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119319419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.119319419
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.2008691775
Short name T753
Test name
Test status
Simulation time 15497976 ps
CPU time 0.59 seconds
Started Jun 23 05:27:44 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 193440 kb
Host smart-361842f0-e305-4f20-b465-bb45d5e1ef53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008691775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.2008691775
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2632777771
Short name T825
Test name
Test status
Simulation time 19171772 ps
CPU time 0.67 seconds
Started Jun 23 05:27:46 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 193416 kb
Host smart-1e52487e-2408-41df-afd6-3ae14251c9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632777771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2632777771
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3502342059
Short name T766
Test name
Test status
Simulation time 18931125 ps
CPU time 0.59 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 194104 kb
Host smart-c67ca09a-cd68-44a0-b1b9-73adccd20fc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502342059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3502342059
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.872258214
Short name T73
Test name
Test status
Simulation time 56176973 ps
CPU time 0.81 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:31 PM PDT 24
Peak memory 195800 kb
Host smart-965b5c60-fad0-412c-855e-d2dbc3ed1a98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872258214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.872258214
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.3465346335
Short name T84
Test name
Test status
Simulation time 394648585 ps
CPU time 3.46 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 197004 kb
Host smart-7924463f-af29-4a43-8a26-c1edb5cf29da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465346335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.3465346335
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.281262103
Short name T778
Test name
Test status
Simulation time 29027736 ps
CPU time 0.66 seconds
Started Jun 23 05:27:29 PM PDT 24
Finished Jun 23 05:27:30 PM PDT 24
Peak memory 195052 kb
Host smart-9241e29c-6987-4065-ab89-4e3546fa101e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281262103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.281262103
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.216127911
Short name T721
Test name
Test status
Simulation time 499727333 ps
CPU time 0.94 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 197624 kb
Host smart-01b08137-62ed-4957-abaa-964ad1b8116e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216127911 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.216127911
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2362725053
Short name T748
Test name
Test status
Simulation time 27713404 ps
CPU time 0.65 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 194736 kb
Host smart-7e38bb31-0702-4ef3-8abc-e7ab4a6c4d53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362725053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2362725053
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1084769213
Short name T738
Test name
Test status
Simulation time 24145800 ps
CPU time 0.57 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 193376 kb
Host smart-01aac837-50e3-40ba-b25d-606bbe6da4e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084769213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1084769213
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.542730651
Short name T87
Test name
Test status
Simulation time 31930294 ps
CPU time 0.84 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:34 PM PDT 24
Peak memory 196676 kb
Host smart-2357b3cf-fc6a-4c29-b028-494d7d95aaa5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542730651 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.542730651
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.302262854
Short name T844
Test name
Test status
Simulation time 345801319 ps
CPU time 2.1 seconds
Started Jun 23 05:27:28 PM PDT 24
Finished Jun 23 05:27:30 PM PDT 24
Peak memory 197808 kb
Host smart-f96c5398-6bc7-4ef3-a594-0fc7103811ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302262854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.302262854
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.953090748
Short name T34
Test name
Test status
Simulation time 74528396 ps
CPU time 1.14 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 197844 kb
Host smart-fa0af654-0162-49dd-ba13-5d287d7f2200
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953090748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.953090748
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3845131725
Short name T734
Test name
Test status
Simulation time 16149989 ps
CPU time 0.63 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 193416 kb
Host smart-cdf67fd9-6e6f-4e89-91ee-31ad8b7e7392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845131725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3845131725
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.1226026921
Short name T741
Test name
Test status
Simulation time 44483555 ps
CPU time 0.63 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 193512 kb
Host smart-237dcc4a-e7c6-4237-9830-93d3d77f9692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226026921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.1226026921
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2396018871
Short name T751
Test name
Test status
Simulation time 14984248 ps
CPU time 0.62 seconds
Started Jun 23 05:27:44 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 193324 kb
Host smart-4b227169-26cd-4b68-8ba4-e68b6966c966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396018871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2396018871
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.1418423028
Short name T719
Test name
Test status
Simulation time 13868795 ps
CPU time 0.59 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 193404 kb
Host smart-2b9a29ba-3c58-488d-ae83-848973c6e119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418423028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.1418423028
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2129589337
Short name T755
Test name
Test status
Simulation time 34383682 ps
CPU time 0.66 seconds
Started Jun 23 05:27:44 PM PDT 24
Finished Jun 23 05:27:46 PM PDT 24
Peak memory 193404 kb
Host smart-5f4a0d16-fc5c-4a39-ab55-a36d26b216ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129589337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2129589337
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.4128622709
Short name T718
Test name
Test status
Simulation time 14099541 ps
CPU time 0.6 seconds
Started Jun 23 05:27:47 PM PDT 24
Finished Jun 23 05:27:48 PM PDT 24
Peak memory 194108 kb
Host smart-f3a02b86-6a00-43e2-ba3a-828f2ece6ec1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128622709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.4128622709
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.1088321911
Short name T788
Test name
Test status
Simulation time 49327949 ps
CPU time 0.67 seconds
Started Jun 23 05:27:44 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 193500 kb
Host smart-06ac2f80-52a0-418e-b535-58b3116f427c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088321911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.1088321911
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.889054105
Short name T837
Test name
Test status
Simulation time 36402751 ps
CPU time 0.58 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 193424 kb
Host smart-9a337475-cf22-44b5-9f80-909b55de9f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889054105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.889054105
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.983568432
Short name T745
Test name
Test status
Simulation time 84253419 ps
CPU time 0.6 seconds
Started Jun 23 05:27:46 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 193356 kb
Host smart-da90c011-7831-4e67-8d64-0522e0c0ffdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983568432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.983568432
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3433450889
Short name T736
Test name
Test status
Simulation time 45899817 ps
CPU time 0.58 seconds
Started Jun 23 05:27:45 PM PDT 24
Finished Jun 23 05:27:47 PM PDT 24
Peak memory 194084 kb
Host smart-fa16cf58-e5bd-4e43-9691-7b781aae9d5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433450889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3433450889
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1811188023
Short name T742
Test name
Test status
Simulation time 18924937 ps
CPU time 0.67 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:31 PM PDT 24
Peak memory 195000 kb
Host smart-9379b2a9-29d1-4080-ad93-788d75ac6ede
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811188023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1811188023
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.372889909
Short name T101
Test name
Test status
Simulation time 783191502 ps
CPU time 3.47 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 197088 kb
Host smart-d9ae7cb6-02a4-49ee-a784-dbd102c31ec0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372889909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.372889909
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2234322865
Short name T841
Test name
Test status
Simulation time 65105494 ps
CPU time 0.64 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 194648 kb
Host smart-f65af0c9-e723-4802-84ec-1cc3f60f17f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234322865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2234322865
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2690610328
Short name T795
Test name
Test status
Simulation time 178458470 ps
CPU time 0.73 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 197384 kb
Host smart-1474f0e6-e739-45f5-b6e7-b902748302e4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690610328 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2690610328
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1268072130
Short name T83
Test name
Test status
Simulation time 16832208 ps
CPU time 0.63 seconds
Started Jun 23 05:27:28 PM PDT 24
Finished Jun 23 05:27:29 PM PDT 24
Peak memory 195268 kb
Host smart-cffcffc0-926d-4a68-9b53-cecd59eb0151
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268072130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1268072130
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1685404888
Short name T780
Test name
Test status
Simulation time 47489704 ps
CPU time 0.58 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:32 PM PDT 24
Peak memory 193984 kb
Host smart-4a422e6f-db74-4874-8829-72df79ee0520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685404888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1685404888
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1039672333
Short name T88
Test name
Test status
Simulation time 116882544 ps
CPU time 0.85 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:34 PM PDT 24
Peak memory 196136 kb
Host smart-d594039e-ea1d-481e-9d1a-212dd3d8c3e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039672333 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1039672333
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1576994749
Short name T790
Test name
Test status
Simulation time 206269440 ps
CPU time 1.49 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 197816 kb
Host smart-252f0279-186e-4c44-9c64-377f6d6ddbfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576994749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1576994749
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3658571178
Short name T749
Test name
Test status
Simulation time 13063667 ps
CPU time 0.6 seconds
Started Jun 23 05:27:50 PM PDT 24
Finished Jun 23 05:27:52 PM PDT 24
Peak memory 194088 kb
Host smart-f04f8360-99ab-44a9-9b73-7f85539f3a96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658571178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3658571178
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2353104105
Short name T804
Test name
Test status
Simulation time 11105181 ps
CPU time 0.57 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:52 PM PDT 24
Peak memory 193400 kb
Host smart-c83e1c3e-7f24-4647-a5d1-d8e129ef451c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353104105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2353104105
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.178983270
Short name T727
Test name
Test status
Simulation time 91444677 ps
CPU time 0.61 seconds
Started Jun 23 05:27:47 PM PDT 24
Finished Jun 23 05:27:48 PM PDT 24
Peak memory 193460 kb
Host smart-6c696d58-297a-414c-aa8c-70dc51669443
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178983270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.178983270
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2802048396
Short name T789
Test name
Test status
Simulation time 87147345 ps
CPU time 0.58 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:50 PM PDT 24
Peak memory 193352 kb
Host smart-b343683e-c1d6-43a0-ad9d-0962a20ac6fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802048396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2802048396
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4274636557
Short name T816
Test name
Test status
Simulation time 42962693 ps
CPU time 0.62 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:50 PM PDT 24
Peak memory 193412 kb
Host smart-6d83e49e-3c44-4942-bb01-515e5f2cd94d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274636557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4274636557
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.781979377
Short name T737
Test name
Test status
Simulation time 52475015 ps
CPU time 0.63 seconds
Started Jun 23 05:27:48 PM PDT 24
Finished Jun 23 05:27:49 PM PDT 24
Peak memory 193496 kb
Host smart-499a73b7-5b93-41a2-8e66-024221a9b6d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781979377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.781979377
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2150335442
Short name T831
Test name
Test status
Simulation time 14980477 ps
CPU time 0.62 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:50 PM PDT 24
Peak memory 193460 kb
Host smart-7505e67c-6a5d-4c35-9e01-31f6b360f2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150335442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2150335442
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2691424755
Short name T798
Test name
Test status
Simulation time 128001684 ps
CPU time 0.6 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:53 PM PDT 24
Peak memory 193460 kb
Host smart-f83b9bd4-0937-46f8-9380-ce599b0cc3a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691424755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2691424755
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.3060696256
Short name T726
Test name
Test status
Simulation time 69447360 ps
CPU time 0.58 seconds
Started Jun 23 05:27:48 PM PDT 24
Finished Jun 23 05:27:49 PM PDT 24
Peak memory 194092 kb
Host smart-0720f084-c11e-48aa-8f78-85230146e295
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060696256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.3060696256
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3485009437
Short name T815
Test name
Test status
Simulation time 15010080 ps
CPU time 0.6 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:52 PM PDT 24
Peak memory 193452 kb
Host smart-cc0e98f8-8672-4a07-8bd7-400beaff0a92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485009437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3485009437
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2657218324
Short name T796
Test name
Test status
Simulation time 21394472 ps
CPU time 0.77 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:32 PM PDT 24
Peak memory 197388 kb
Host smart-c25b5c36-409e-43fd-a7ae-a726dac58d27
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657218324 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2657218324
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3452656565
Short name T834
Test name
Test status
Simulation time 34825515 ps
CPU time 0.6 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 194276 kb
Host smart-dacdd984-f1b5-41be-9b53-b0e2b473e0f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452656565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3452656565
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.337559824
Short name T754
Test name
Test status
Simulation time 19763027 ps
CPU time 0.62 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 193512 kb
Host smart-0dd40abd-6059-475b-a296-41d599af3692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337559824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.337559824
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.1940312981
Short name T828
Test name
Test status
Simulation time 27468560 ps
CPU time 0.7 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:34 PM PDT 24
Peak memory 194756 kb
Host smart-6b773176-7313-4521-a0dd-0d772785a466
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940312981 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.1940312981
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2300109672
Short name T731
Test name
Test status
Simulation time 84105362 ps
CPU time 1.7 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:32 PM PDT 24
Peak memory 197808 kb
Host smart-a14d89c0-62f3-4b63-aa41-1d24b0dd7cea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300109672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2300109672
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.323286445
Short name T801
Test name
Test status
Simulation time 45089091 ps
CPU time 0.92 seconds
Started Jun 23 05:27:31 PM PDT 24
Finished Jun 23 05:27:33 PM PDT 24
Peak memory 196892 kb
Host smart-a9951fd4-4a11-4010-84f9-26d0957a2687
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323286445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.323286445
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2917528166
Short name T724
Test name
Test status
Simulation time 164057636 ps
CPU time 1 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:34 PM PDT 24
Peak memory 197688 kb
Host smart-b04e2888-24d2-4472-a6f3-31e9a79a621a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917528166 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2917528166
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2534911664
Short name T835
Test name
Test status
Simulation time 108790507 ps
CPU time 0.59 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:31 PM PDT 24
Peak memory 194736 kb
Host smart-69bd80e0-d855-4743-a8db-434118895f1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534911664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2534911664
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3797831596
Short name T763
Test name
Test status
Simulation time 54751971 ps
CPU time 0.59 seconds
Started Jun 23 05:27:29 PM PDT 24
Finished Jun 23 05:27:31 PM PDT 24
Peak memory 193424 kb
Host smart-290497db-e502-48c6-848b-f63bee36b413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797831596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3797831596
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.489737613
Short name T793
Test name
Test status
Simulation time 69215532 ps
CPU time 0.67 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 194592 kb
Host smart-5227fe41-d495-4b20-b82c-05f97b58d868
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489737613 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.489737613
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.4083707677
Short name T818
Test name
Test status
Simulation time 338853949 ps
CPU time 2 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 197808 kb
Host smart-21c1dc9f-6e54-47b5-8e2f-ff068a43bb75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083707677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.4083707677
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2757756167
Short name T807
Test name
Test status
Simulation time 141818285 ps
CPU time 1.14 seconds
Started Jun 23 05:27:30 PM PDT 24
Finished Jun 23 05:27:32 PM PDT 24
Peak memory 197816 kb
Host smart-cf27c32d-b4ac-4f8c-9430-0c9df6fd01cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757756167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2757756167
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.46814570
Short name T750
Test name
Test status
Simulation time 110785938 ps
CPU time 0.91 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 197648 kb
Host smart-2b316e8e-1ff3-42da-94c3-c96c0e3bca3a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46814570 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.46814570
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2503348327
Short name T67
Test name
Test status
Simulation time 18419373 ps
CPU time 0.6 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 192952 kb
Host smart-1c10c6ae-3be9-4a6b-9c03-f2ec5d59dda9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503348327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2503348327
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.74747384
Short name T728
Test name
Test status
Simulation time 18574472 ps
CPU time 0.56 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 193440 kb
Host smart-3690f1d3-3c2e-42bc-99ec-ef21f15e5763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74747384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.74747384
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.2748339814
Short name T85
Test name
Test status
Simulation time 59830963 ps
CPU time 0.69 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 195424 kb
Host smart-de80f854-1374-4592-93a6-8e39fd829f70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748339814 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.2748339814
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1831863063
Short name T779
Test name
Test status
Simulation time 147937517 ps
CPU time 1.67 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 197880 kb
Host smart-9f8d2950-1ed4-45ab-a58c-24162114fdf6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831863063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1831863063
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.65547697
Short name T808
Test name
Test status
Simulation time 47371647 ps
CPU time 0.92 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 196864 kb
Host smart-8c858c0c-a66e-48ec-9c5f-a05da55045fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65547697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.gpio_tl_intg_err.65547697
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1226257312
Short name T817
Test name
Test status
Simulation time 43228597 ps
CPU time 1.08 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 198040 kb
Host smart-5d534d2e-b2b6-478e-be48-a0c5f9125875
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226257312 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1226257312
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2208381097
Short name T770
Test name
Test status
Simulation time 44729621 ps
CPU time 0.63 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 194548 kb
Host smart-f3d6461e-49f1-4a75-8a5c-5cb067a3d126
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208381097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2208381097
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3637592276
Short name T772
Test name
Test status
Simulation time 12090841 ps
CPU time 0.6 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 194072 kb
Host smart-12942064-5fb4-420a-be80-fa5bd97df921
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637592276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3637592276
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3886152283
Short name T86
Test name
Test status
Simulation time 22082449 ps
CPU time 0.82 seconds
Started Jun 23 05:27:36 PM PDT 24
Finished Jun 23 05:27:38 PM PDT 24
Peak memory 196000 kb
Host smart-b720e144-c427-4585-8488-55548ed09827
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886152283 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3886152283
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.2340642507
Short name T838
Test name
Test status
Simulation time 66138186 ps
CPU time 1.07 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 197828 kb
Host smart-207100db-b15c-4031-ba97-3be2a866d309
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340642507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.2340642507
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1799005257
Short name T42
Test name
Test status
Simulation time 100319415 ps
CPU time 1.45 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 197872 kb
Host smart-941eb4d4-b44d-4326-b571-8085fa057dfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799005257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1799005257
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1259034739
Short name T833
Test name
Test status
Simulation time 168491542 ps
CPU time 0.98 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 197592 kb
Host smart-dac4564e-823f-4c33-8d6c-6106844ac1f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259034739 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1259034739
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2584399383
Short name T102
Test name
Test status
Simulation time 42881917 ps
CPU time 0.57 seconds
Started Jun 23 05:27:32 PM PDT 24
Finished Jun 23 05:27:34 PM PDT 24
Peak memory 194424 kb
Host smart-0e2d3348-826f-4e91-b979-02c183283860
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584399383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2584399383
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1262934488
Short name T811
Test name
Test status
Simulation time 31942496 ps
CPU time 0.57 seconds
Started Jun 23 05:27:34 PM PDT 24
Finished Jun 23 05:27:36 PM PDT 24
Peak memory 193388 kb
Host smart-c7323422-2331-4158-99d9-8b4fd15129e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262934488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1262934488
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.548621310
Short name T791
Test name
Test status
Simulation time 134526310 ps
CPU time 0.66 seconds
Started Jun 23 05:27:33 PM PDT 24
Finished Jun 23 05:27:35 PM PDT 24
Peak memory 194720 kb
Host smart-c6513f3c-6918-407b-b154-32dd9d9605c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548621310 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 9.gpio_same_csr_outstanding.548621310
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2682998067
Short name T773
Test name
Test status
Simulation time 2762405173 ps
CPU time 2.8 seconds
Started Jun 23 05:27:42 PM PDT 24
Finished Jun 23 05:27:45 PM PDT 24
Peak memory 197816 kb
Host smart-46361c15-96e6-49db-b692-6acfc82c2379
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682998067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2682998067
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1487954572
Short name T44
Test name
Test status
Simulation time 895894927 ps
CPU time 1.47 seconds
Started Jun 23 05:27:35 PM PDT 24
Finished Jun 23 05:27:37 PM PDT 24
Peak memory 197828 kb
Host smart-cc02c9dd-41fe-44c3-b991-be8b5c6b0bcc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487954572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1487954572
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.737043764
Short name T271
Test name
Test status
Simulation time 13059763 ps
CPU time 0.56 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:16 PM PDT 24
Peak memory 194536 kb
Host smart-2ca6e231-1788-4f77-b6ca-3adbfeca7dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737043764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.737043764
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.174628137
Short name T251
Test name
Test status
Simulation time 228232680 ps
CPU time 0.75 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:21 PM PDT 24
Peak memory 195092 kb
Host smart-ccf13843-9a6a-4b6a-acdf-dc6e687dbce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174628137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.174628137
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3220912215
Short name T712
Test name
Test status
Simulation time 626301285 ps
CPU time 15.67 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 196848 kb
Host smart-9b8dfd38-b19a-467f-b816-fd6293c5edb8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220912215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3220912215
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3027782701
Short name T657
Test name
Test status
Simulation time 106967829 ps
CPU time 0.65 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:15 PM PDT 24
Peak memory 194612 kb
Host smart-b40cff08-a47e-4f91-901d-1d99a6699cf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027782701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3027782701
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3568139229
Short name T26
Test name
Test status
Simulation time 38451468 ps
CPU time 0.79 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:17 PM PDT 24
Peak memory 195316 kb
Host smart-d2dfc1b2-3e60-4366-9475-38b2d53f13f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568139229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3568139229
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2731872285
Short name T314
Test name
Test status
Simulation time 58455935 ps
CPU time 1.36 seconds
Started Jun 23 05:28:08 PM PDT 24
Finished Jun 23 05:28:10 PM PDT 24
Peak memory 198124 kb
Host smart-df8a772c-1fff-4f90-ab53-e319eae6a19e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731872285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2731872285
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1598604713
Short name T211
Test name
Test status
Simulation time 270729116 ps
CPU time 1.66 seconds
Started Jun 23 05:28:05 PM PDT 24
Finished Jun 23 05:28:06 PM PDT 24
Peak memory 195812 kb
Host smart-95639f42-968a-4fe8-8b0f-13e2f1d25481
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598604713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1598604713
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.1976382567
Short name T63
Test name
Test status
Simulation time 157937523 ps
CPU time 0.79 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:17 PM PDT 24
Peak memory 195284 kb
Host smart-dd1430dd-e81b-4ec3-9c76-faf2e696b42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976382567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.1976382567
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.4101234413
Short name T24
Test name
Test status
Simulation time 359158384 ps
CPU time 1.25 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 197092 kb
Host smart-63d7f554-a6c6-4581-ad84-7e92f66bcfc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101234413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.4101234413
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2037620586
Short name T506
Test name
Test status
Simulation time 247624875 ps
CPU time 1.67 seconds
Started Jun 23 05:28:07 PM PDT 24
Finished Jun 23 05:28:09 PM PDT 24
Peak memory 197196 kb
Host smart-41944d1c-fc27-478c-8593-38af3b5e9c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037620586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2037620586
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.4135695473
Short name T45
Test name
Test status
Simulation time 33743220 ps
CPU time 0.81 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:16 PM PDT 24
Peak memory 213656 kb
Host smart-2a38cd1e-4ac0-4ab7-aea0-73afd32635df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135695473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.4135695473
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.3148518056
Short name T508
Test name
Test status
Simulation time 77911327 ps
CPU time 1.18 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:11 PM PDT 24
Peak memory 195744 kb
Host smart-94de9138-9626-418b-8864-3c5508ed2206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148518056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.3148518056
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.4027215611
Short name T392
Test name
Test status
Simulation time 61119245 ps
CPU time 1.19 seconds
Started Jun 23 05:28:05 PM PDT 24
Finished Jun 23 05:28:06 PM PDT 24
Peak memory 195804 kb
Host smart-2cfb4b29-bd8f-4e3f-8833-a048afe7281d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027215611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.4027215611
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2326152479
Short name T100
Test name
Test status
Simulation time 26814319680 ps
CPU time 185.06 seconds
Started Jun 23 05:28:04 PM PDT 24
Finished Jun 23 05:31:09 PM PDT 24
Peak memory 198144 kb
Host smart-92129899-2d08-4de7-9579-a54ad4c4c36d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326152479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2326152479
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.1081133637
Short name T397
Test name
Test status
Simulation time 87863336 ps
CPU time 0.9 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:10 PM PDT 24
Peak memory 196332 kb
Host smart-52398989-4578-4e5d-bfd3-5cb926397b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081133637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.1081133637
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3840414411
Short name T298
Test name
Test status
Simulation time 494323143 ps
CPU time 17.84 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:34 PM PDT 24
Peak memory 196304 kb
Host smart-79abb9cb-d9ca-4a91-8f03-b7f09eb6d43c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840414411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3840414411
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.4016863695
Short name T118
Test name
Test status
Simulation time 403647471 ps
CPU time 1.17 seconds
Started Jun 23 05:28:21 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 195784 kb
Host smart-72519dc9-013b-4034-8069-162552c0a222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016863695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.4016863695
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2096574531
Short name T332
Test name
Test status
Simulation time 505864076 ps
CPU time 3.29 seconds
Started Jun 23 05:28:08 PM PDT 24
Finished Jun 23 05:28:12 PM PDT 24
Peak memory 198092 kb
Host smart-50c8a4ff-c9ea-4671-9c35-455cccbb659c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096574531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2096574531
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.427405560
Short name T689
Test name
Test status
Simulation time 134437428 ps
CPU time 0.84 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:17 PM PDT 24
Peak memory 195012 kb
Host smart-94483afc-8bc0-4c54-bb06-67d8869fabf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427405560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.427405560
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.193169110
Short name T428
Test name
Test status
Simulation time 52667322 ps
CPU time 1.23 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 197360 kb
Host smart-7424f007-cfb0-4139-9780-fe27bedeab59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193169110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.193169110
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1554215726
Short name T539
Test name
Test status
Simulation time 23350820 ps
CPU time 0.91 seconds
Started Jun 23 05:28:02 PM PDT 24
Finished Jun 23 05:28:04 PM PDT 24
Peak memory 196088 kb
Host smart-23fb143d-eff4-4b5c-8c1e-b74ff63df2c0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554215726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1554215726
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2834209518
Short name T382
Test name
Test status
Simulation time 563941473 ps
CPU time 1.69 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 198012 kb
Host smart-a7aed824-94c1-4429-9e0d-c6e8810cd93c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834209518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2834209518
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.2695120028
Short name T459
Test name
Test status
Simulation time 85844853 ps
CPU time 0.95 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:16 PM PDT 24
Peak memory 195572 kb
Host smart-2e7bf34b-1133-4d47-9f99-f2c2bb9242bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695120028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2695120028
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.2207451355
Short name T475
Test name
Test status
Simulation time 62936434 ps
CPU time 0.93 seconds
Started Jun 23 05:28:11 PM PDT 24
Finished Jun 23 05:28:12 PM PDT 24
Peak memory 196464 kb
Host smart-af89a260-3d44-4761-9aa1-baf74a7f43a7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207451355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.2207451355
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4256058085
Short name T281
Test name
Test status
Simulation time 2650688233 ps
CPU time 63.42 seconds
Started Jun 23 05:28:10 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 197968 kb
Host smart-9f75088d-fca0-470f-a96c-fa9b4ccc8c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256058085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4256058085
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.406949937
Short name T303
Test name
Test status
Simulation time 84605536272 ps
CPU time 449.31 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:35:48 PM PDT 24
Peak memory 198144 kb
Host smart-eb848d29-eeba-4f03-97e6-359a91b679ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=406949937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.406949937
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2565531072
Short name T596
Test name
Test status
Simulation time 28553873 ps
CPU time 0.57 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 192688 kb
Host smart-6cf215f6-5144-4d17-9e8a-6909adeab399
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565531072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2565531072
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.4224789597
Short name T606
Test name
Test status
Simulation time 99122456 ps
CPU time 0.92 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 195988 kb
Host smart-24c0b94c-dc7b-4ba9-b02e-e6723ae05085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224789597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.4224789597
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.283128338
Short name T228
Test name
Test status
Simulation time 3190154717 ps
CPU time 24.58 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:52 PM PDT 24
Peak memory 198160 kb
Host smart-f94e9057-35e0-4335-b24f-6a6fa16100ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283128338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.283128338
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1255823306
Short name T438
Test name
Test status
Simulation time 226277251 ps
CPU time 1.03 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 196520 kb
Host smart-560f076a-bc0b-4499-bb1b-416710cd1bba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255823306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1255823306
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.623976234
Short name T98
Test name
Test status
Simulation time 119363177 ps
CPU time 0.97 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 196532 kb
Host smart-fb821751-d35b-4753-8d3a-e4e8028d987d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623976234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.623976234
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1305728292
Short name T658
Test name
Test status
Simulation time 141045538 ps
CPU time 1.36 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 196688 kb
Host smart-388b6ac5-a8a0-4b8b-b76f-9a147d4d74d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305728292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1305728292
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2907294813
Short name T587
Test name
Test status
Simulation time 135854994 ps
CPU time 3.05 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 198076 kb
Host smart-98f6d6fc-5c72-40ea-876a-7cbad9776a50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907294813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2907294813
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.720828250
Short name T238
Test name
Test status
Simulation time 102188149 ps
CPU time 0.99 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 196016 kb
Host smart-31880c65-5a6a-4971-8e7e-5e3d04c1c184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720828250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.720828250
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.1132081755
Short name T260
Test name
Test status
Simulation time 15331122 ps
CPU time 0.71 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 196060 kb
Host smart-ff5d0f20-1359-4c00-904f-ca678875132e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132081755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.1132081755
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.2093283799
Short name T615
Test name
Test status
Simulation time 123042199 ps
CPU time 1.54 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 198028 kb
Host smart-3b828ea0-1ba0-40c5-bfcb-993e872e3f4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093283799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.2093283799
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1135565143
Short name T437
Test name
Test status
Simulation time 31468871 ps
CPU time 0.95 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 195796 kb
Host smart-9350e304-0a75-4c8b-bcdc-50b446812b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135565143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1135565143
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3998716988
Short name T189
Test name
Test status
Simulation time 51231332 ps
CPU time 0.94 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 196156 kb
Host smart-3b18097b-3cbf-4bb2-9387-52bee479a5e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998716988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3998716988
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1858288892
Short name T560
Test name
Test status
Simulation time 25179291688 ps
CPU time 263.88 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:32:51 PM PDT 24
Peak memory 198148 kb
Host smart-88668a85-94d2-4d60-86a3-db405c272290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858288892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1858288892
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.3184460005
Short name T489
Test name
Test status
Simulation time 41199825656 ps
CPU time 1151.2 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:47:38 PM PDT 24
Peak memory 206424 kb
Host smart-932762a1-96fd-419c-8550-404abf26b224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3184460005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.3184460005
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1065416264
Short name T688
Test name
Test status
Simulation time 22708630 ps
CPU time 0.55 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 194736 kb
Host smart-ab3db712-d1d8-4738-a895-487d974b778a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065416264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1065416264
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3850078182
Short name T499
Test name
Test status
Simulation time 48804211 ps
CPU time 0.72 seconds
Started Jun 23 05:28:24 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 194096 kb
Host smart-19a45a86-6ce9-4547-ba02-8a8ea1bca264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850078182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3850078182
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.38514873
Short name T286
Test name
Test status
Simulation time 5149172373 ps
CPU time 18.12 seconds
Started Jun 23 05:28:23 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 197020 kb
Host smart-dd02c920-1a0a-4561-bf21-25e49978e29b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38514873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stress
.38514873
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2845420539
Short name T629
Test name
Test status
Simulation time 67030986 ps
CPU time 0.95 seconds
Started Jun 23 05:28:23 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 197088 kb
Host smart-a77f782c-144e-4316-8cfe-54bc93112be3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845420539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2845420539
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3947141872
Short name T584
Test name
Test status
Simulation time 457300251 ps
CPU time 1.39 seconds
Started Jun 23 05:28:21 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 197232 kb
Host smart-1fbf5664-a572-426c-8291-5e1d6b4e6f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947141872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3947141872
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2406571365
Short name T457
Test name
Test status
Simulation time 197424211 ps
CPU time 2.52 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 198096 kb
Host smart-56ff416a-8805-45eb-91ab-caa93f2816a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406571365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2406571365
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.2983977344
Short name T446
Test name
Test status
Simulation time 32441496 ps
CPU time 0.84 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 194384 kb
Host smart-64b0dc42-608a-41ee-a393-2192b9691182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983977344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.2983977344
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2888901783
Short name T305
Test name
Test status
Simulation time 110237399 ps
CPU time 0.86 seconds
Started Jun 23 05:28:24 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 196256 kb
Host smart-2634dde2-6edd-4bb4-b0d0-74244e21e01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888901783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2888901783
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1786093414
Short name T273
Test name
Test status
Simulation time 46755827 ps
CPU time 0.98 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 195932 kb
Host smart-988c38e9-dd8c-4a2b-8105-d3635c8c630c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786093414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1786093414
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_smoke.2808735307
Short name T485
Test name
Test status
Simulation time 45983829 ps
CPU time 1.36 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 196872 kb
Host smart-52a3cef8-31d4-4a01-9c24-bb84ae08ed2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808735307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.2808735307
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.119040268
Short name T405
Test name
Test status
Simulation time 228974594 ps
CPU time 1.21 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 198208 kb
Host smart-1004992b-9665-470e-a1d3-e83c518584b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119040268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.119040268
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.602136659
Short name T559
Test name
Test status
Simulation time 38043855570 ps
CPU time 98.79 seconds
Started Jun 23 05:28:23 PM PDT 24
Finished Jun 23 05:30:03 PM PDT 24
Peak memory 198168 kb
Host smart-ccae2660-bba7-4882-a4d8-e56bd0f5652e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602136659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.602136659
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1033564035
Short name T465
Test name
Test status
Simulation time 14863359 ps
CPU time 0.57 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 194712 kb
Host smart-f765eb19-2c9e-49e1-9f48-27c4a93b41c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033564035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1033564035
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.74378484
Short name T259
Test name
Test status
Simulation time 124493027 ps
CPU time 0.82 seconds
Started Jun 23 05:28:24 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 195404 kb
Host smart-45c5615f-3aa7-4a65-9f84-8c0b7778b55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74378484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.74378484
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1187715536
Short name T194
Test name
Test status
Simulation time 431256660 ps
CPU time 9.74 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:28:40 PM PDT 24
Peak memory 196916 kb
Host smart-e1da586d-5c2d-494e-be43-a08821caf173
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187715536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1187715536
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2627021718
Short name T419
Test name
Test status
Simulation time 154956276 ps
CPU time 0.74 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 196552 kb
Host smart-92673860-e961-4116-bf19-7bc97f2a6ca3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627021718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2627021718
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.2019143378
Short name T481
Test name
Test status
Simulation time 151657526 ps
CPU time 0.82 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 195612 kb
Host smart-8831d545-3c9c-41f3-b40b-03de51dfa537
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019143378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.2019143378
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1628097050
Short name T203
Test name
Test status
Simulation time 24510015 ps
CPU time 0.97 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 196640 kb
Host smart-09a1a678-f2c9-4c1d-8455-3814331d4d28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628097050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1628097050
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.564613636
Short name T576
Test name
Test status
Simulation time 463870015 ps
CPU time 2.34 seconds
Started Jun 23 05:28:28 PM PDT 24
Finished Jun 23 05:28:31 PM PDT 24
Peak memory 197136 kb
Host smart-d5419263-435a-48ef-8486-73214f616306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564613636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
564613636
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3808755798
Short name T270
Test name
Test status
Simulation time 17804364 ps
CPU time 0.81 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 195508 kb
Host smart-7cf00c7c-3ee8-4bbd-a071-bab0a57608bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808755798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3808755798
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.1455247079
Short name T586
Test name
Test status
Simulation time 16614104 ps
CPU time 0.65 seconds
Started Jun 23 05:28:24 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 194296 kb
Host smart-a9dcf27e-8718-4d5d-a64e-ab6ac048acd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455247079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.1455247079
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2549666240
Short name T408
Test name
Test status
Simulation time 337942865 ps
CPU time 1.71 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:28:35 PM PDT 24
Peak memory 198052 kb
Host smart-3ef30507-a15d-468d-a640-ed0b18918c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549666240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2549666240
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2436506006
Short name T256
Test name
Test status
Simulation time 498651181 ps
CPU time 1.07 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 196540 kb
Host smart-445bdf49-5fa3-4696-92eb-99750fcb82f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436506006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2436506006
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2105474854
Short name T212
Test name
Test status
Simulation time 89736618 ps
CPU time 0.79 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 194832 kb
Host smart-ff27ed71-4d0b-4aae-86b8-4e118cd2d7fc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105474854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2105474854
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2550393110
Short name T649
Test name
Test status
Simulation time 55827723843 ps
CPU time 155.22 seconds
Started Jun 23 05:28:22 PM PDT 24
Finished Jun 23 05:30:59 PM PDT 24
Peak memory 198164 kb
Host smart-7ac0562a-a340-469a-bea5-a86baefa4796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550393110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2550393110
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1637655903
Short name T410
Test name
Test status
Simulation time 58395676988 ps
CPU time 213.52 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:32:00 PM PDT 24
Peak memory 206408 kb
Host smart-d2a84c0d-a2ca-4af6-8cf9-a8f3d8c9a823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1637655903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1637655903
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1735242922
Short name T635
Test name
Test status
Simulation time 30696184 ps
CPU time 0.57 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 194536 kb
Host smart-288d71f1-112f-4416-8c17-a2dc9f615bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735242922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1735242922
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.1440372142
Short name T180
Test name
Test status
Simulation time 78471740 ps
CPU time 0.73 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 194120 kb
Host smart-8bce616b-e785-46bd-9606-b217aedaa8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440372142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.1440372142
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2984045228
Short name T285
Test name
Test status
Simulation time 3362122660 ps
CPU time 23.72 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:51 PM PDT 24
Peak memory 196868 kb
Host smart-d1cda1e6-7f73-4acc-87f4-f9306c0763b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984045228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2984045228
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2379904338
Short name T433
Test name
Test status
Simulation time 27727639 ps
CPU time 0.7 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 195296 kb
Host smart-e6eb5e26-49c4-4dbe-bd12-41f8843c244d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379904338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2379904338
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3048872344
Short name T612
Test name
Test status
Simulation time 160041482 ps
CPU time 1.66 seconds
Started Jun 23 05:28:22 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 196940 kb
Host smart-4c4c2d52-d2e4-4fc5-9058-6942d5c06d40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048872344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3048872344
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3937509548
Short name T138
Test name
Test status
Simulation time 357177916 ps
CPU time 3.61 seconds
Started Jun 23 05:28:23 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 198100 kb
Host smart-73c4467a-9fb1-4a03-bbf6-82ebd0e9ff39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937509548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3937509548
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2466953295
Short name T133
Test name
Test status
Simulation time 175602344 ps
CPU time 2.63 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:31 PM PDT 24
Peak memory 197180 kb
Host smart-43913c30-c87f-4e88-b0bb-9ceafaa0c281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466953295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2466953295
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.726778559
Short name T304
Test name
Test status
Simulation time 40288065 ps
CPU time 0.92 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:28:31 PM PDT 24
Peak memory 197344 kb
Host smart-e3bfc0a4-614c-4e5a-94e1-7449e5c14238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726778559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.726778559
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.878589039
Short name T202
Test name
Test status
Simulation time 41023117 ps
CPU time 1.02 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 196896 kb
Host smart-e3682e3c-529d-4fd9-9aee-07e396cddc61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878589039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.878589039
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3284116576
Short name T651
Test name
Test status
Simulation time 89566644 ps
CPU time 1.15 seconds
Started Jun 23 05:28:28 PM PDT 24
Finished Jun 23 05:28:31 PM PDT 24
Peak memory 197984 kb
Host smart-bc74dcea-7165-406f-b747-8212962ad4e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284116576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3284116576
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1459274794
Short name T683
Test name
Test status
Simulation time 91513774 ps
CPU time 0.87 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 196356 kb
Host smart-145c1c2c-6e88-4f60-b899-de91b02bba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459274794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1459274794
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.1344119130
Short name T421
Test name
Test status
Simulation time 54625275 ps
CPU time 0.74 seconds
Started Jun 23 05:28:28 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 194036 kb
Host smart-d521bfec-1e8e-4fa8-b7a6-abc47a2b578c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344119130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.1344119130
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1202554202
Short name T152
Test name
Test status
Simulation time 10067190083 ps
CPU time 107.05 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:30:13 PM PDT 24
Peak memory 191748 kb
Host smart-7ec6f6ea-d5fe-47d3-b3bd-f3c9bf8b233d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202554202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1202554202
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3765429228
Short name T53
Test name
Test status
Simulation time 17241349905 ps
CPU time 293.82 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:33:24 PM PDT 24
Peak memory 198260 kb
Host smart-a6018d30-dc59-41b0-9abf-f424b21847b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3765429228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3765429228
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2671780005
Short name T277
Test name
Test status
Simulation time 56138562 ps
CPU time 0.61 seconds
Started Jun 23 05:28:39 PM PDT 24
Finished Jun 23 05:28:40 PM PDT 24
Peak memory 194040 kb
Host smart-3218296b-94b8-4dd2-9fe3-7bd063c2f26d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671780005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2671780005
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.615152785
Short name T109
Test name
Test status
Simulation time 66412105 ps
CPU time 0.86 seconds
Started Jun 23 05:28:24 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 195460 kb
Host smart-1b63c630-a1df-43a3-8899-460d53a02c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615152785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.615152785
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.769272215
Short name T634
Test name
Test status
Simulation time 2216477536 ps
CPU time 6.97 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:28:37 PM PDT 24
Peak memory 197020 kb
Host smart-2392fa96-3b5a-4403-9e14-93776864d047
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769272215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.769272215
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1018363231
Short name T619
Test name
Test status
Simulation time 37200661 ps
CPU time 0.74 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 195212 kb
Host smart-fa95cf93-b6a0-4b00-a216-54ed1d24f6cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018363231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1018363231
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.318721629
Short name T569
Test name
Test status
Simulation time 59390312 ps
CPU time 1.03 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 196132 kb
Host smart-209717fd-1caf-49f4-8ac2-dba05a3d6d45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318721629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.318721629
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1099369312
Short name T593
Test name
Test status
Simulation time 61904004 ps
CPU time 2.57 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:28:36 PM PDT 24
Peak memory 198096 kb
Host smart-28fef408-eb5e-4fe8-94b3-647d3d0cafdc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099369312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1099369312
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1246868
Short name T698
Test name
Test status
Simulation time 190041072 ps
CPU time 2.84 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 195840 kb
Host smart-0138a391-65d6-49e4-a92e-3821ea7f8adf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.1246868
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.4150959922
Short name T284
Test name
Test status
Simulation time 131085945 ps
CPU time 1 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:28:33 PM PDT 24
Peak memory 196040 kb
Host smart-f3d2d954-9c64-494a-abbe-eec25ff67a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150959922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.4150959922
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.4137998683
Short name T394
Test name
Test status
Simulation time 37165687 ps
CPU time 0.69 seconds
Started Jun 23 05:28:28 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 194308 kb
Host smart-6f541721-1b13-41c2-b621-82cf9f766c8f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137998683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.4137998683
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.1488923420
Short name T621
Test name
Test status
Simulation time 79244091 ps
CPU time 1.39 seconds
Started Jun 23 05:28:28 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 198040 kb
Host smart-3d1fe64f-7ae1-463c-a63a-9de236e1375d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488923420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.1488923420
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3850992988
Short name T666
Test name
Test status
Simulation time 277608350 ps
CPU time 1.07 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 196516 kb
Host smart-1d38c828-71f1-4d4e-ae2d-5f07aea6c8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850992988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3850992988
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2325150525
Short name T188
Test name
Test status
Simulation time 103097308 ps
CPU time 1.13 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:28:31 PM PDT 24
Peak memory 195896 kb
Host smart-4794692e-5978-4a34-b4b5-5e4fabab62f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325150525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2325150525
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.319466356
Short name T668
Test name
Test status
Simulation time 6271699095 ps
CPU time 65.77 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:29:41 PM PDT 24
Peak memory 198136 kb
Host smart-52c08110-64c1-4e44-bd7b-1376e54710ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319466356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.319466356
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2786422507
Short name T52
Test name
Test status
Simulation time 42589804556 ps
CPU time 997.7 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:45:11 PM PDT 24
Peak memory 198220 kb
Host smart-4a1103b5-05fc-47f6-a962-ba38bf47f20e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2786422507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2786422507
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2077137641
Short name T38
Test name
Test status
Simulation time 14533163 ps
CPU time 0.6 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 194556 kb
Host smart-8bcf7122-2a39-493a-8d4c-5c493456320a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077137641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2077137641
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1660250900
Short name T620
Test name
Test status
Simulation time 21702723 ps
CPU time 0.66 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:37 PM PDT 24
Peak memory 194708 kb
Host smart-8902826f-a0b5-4711-863e-595edf4195b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660250900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1660250900
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.1698319314
Short name T287
Test name
Test status
Simulation time 1270468358 ps
CPU time 19.23 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:56 PM PDT 24
Peak memory 197892 kb
Host smart-73e7a3e5-52db-4a7f-8d2e-94f82d06e2e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698319314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.1698319314
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.673801084
Short name T466
Test name
Test status
Simulation time 315022372 ps
CPU time 1.02 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:33 PM PDT 24
Peak memory 196520 kb
Host smart-273e4fb4-d0d9-409d-be0a-892429264dcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673801084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.673801084
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.2211377241
Short name T614
Test name
Test status
Simulation time 242569679 ps
CPU time 1.14 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:28:31 PM PDT 24
Peak memory 195972 kb
Host smart-9352ca2e-2dca-4688-bc9d-07a77f7a9077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211377241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.2211377241
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2317564871
Short name T389
Test name
Test status
Simulation time 332572595 ps
CPU time 3.51 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:28:39 PM PDT 24
Peak memory 198032 kb
Host smart-a487d756-cf41-4ed7-81c9-76565c32c432
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317564871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2317564871
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4040760916
Short name T648
Test name
Test status
Simulation time 435281529 ps
CPU time 3.19 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:35 PM PDT 24
Peak memory 198140 kb
Host smart-cc5c4901-93ca-49b5-a5bb-acecde98e9e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040760916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4040760916
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2227579159
Short name T386
Test name
Test status
Simulation time 32387409 ps
CPU time 1.14 seconds
Started Jun 23 05:28:30 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 197168 kb
Host smart-9abed455-2ea5-421f-9752-a625bba53187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227579159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2227579159
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1612758428
Short name T406
Test name
Test status
Simulation time 176849498 ps
CPU time 0.81 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:28:33 PM PDT 24
Peak memory 195556 kb
Host smart-d511851d-cab6-428d-ad53-d830099c8abd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612758428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1612758428
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1714461302
Short name T218
Test name
Test status
Simulation time 319407715 ps
CPU time 4.88 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:28:40 PM PDT 24
Peak memory 197868 kb
Host smart-9de3b5c5-1b3a-42f6-8ba0-42c78abf70cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714461302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1714461302
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3792447369
Short name T398
Test name
Test status
Simulation time 42656371 ps
CPU time 1.31 seconds
Started Jun 23 05:28:33 PM PDT 24
Finished Jun 23 05:28:35 PM PDT 24
Peak memory 196812 kb
Host smart-9464b10a-096c-4f43-97ba-339351b3fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792447369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3792447369
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.97809621
Short name T653
Test name
Test status
Simulation time 125871979 ps
CPU time 0.8 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:37 PM PDT 24
Peak memory 195320 kb
Host smart-5f609696-61da-40f9-b087-ae4aab6066ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97809621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.97809621
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3361287964
Short name T4
Test name
Test status
Simulation time 20861269839 ps
CPU time 68.29 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:29:38 PM PDT 24
Peak memory 198148 kb
Host smart-5b63acee-cb6c-453c-a8d3-ef4931708450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361287964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3361287964
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2375084321
Short name T472
Test name
Test status
Simulation time 12404738 ps
CPU time 0.58 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:41 PM PDT 24
Peak memory 194552 kb
Host smart-0ea7c399-1c4a-48fd-8768-94e9aa92f848
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375084321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2375084321
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.1197762219
Short name T400
Test name
Test status
Simulation time 25974768 ps
CPU time 0.82 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:33 PM PDT 24
Peak memory 195952 kb
Host smart-178dbcf0-fb5c-4241-837b-490f3c18f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197762219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.1197762219
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1944247393
Short name T590
Test name
Test status
Simulation time 2767107729 ps
CPU time 24.88 seconds
Started Jun 23 05:28:41 PM PDT 24
Finished Jun 23 05:29:07 PM PDT 24
Peak memory 197052 kb
Host smart-1afec857-b6ea-4654-a1b5-b73e581d565e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944247393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1944247393
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4203967820
Short name T393
Test name
Test status
Simulation time 85088608 ps
CPU time 0.95 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 196676 kb
Host smart-f0a8d2e3-851f-498c-a7d2-dcd3c054bb96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203967820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4203967820
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.2783888585
Short name T387
Test name
Test status
Simulation time 62561615 ps
CPU time 1.23 seconds
Started Jun 23 05:28:30 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 196900 kb
Host smart-24f7b300-66d4-4d04-b769-9b67fcfc6575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783888585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.2783888585
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1080534102
Short name T265
Test name
Test status
Simulation time 197046344 ps
CPU time 2.02 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:28:37 PM PDT 24
Peak memory 197924 kb
Host smart-4878a4ee-366c-4b86-a9a4-eb8766f49ad9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080534102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1080534102
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.818326228
Short name T684
Test name
Test status
Simulation time 270280065 ps
CPU time 1.55 seconds
Started Jun 23 05:28:29 PM PDT 24
Finished Jun 23 05:28:31 PM PDT 24
Peak memory 196772 kb
Host smart-71d8bafe-fa41-4a2b-aeb7-e6c63bbf412d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818326228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
818326228
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1523621582
Short name T356
Test name
Test status
Simulation time 61045990 ps
CPU time 0.94 seconds
Started Jun 23 05:28:33 PM PDT 24
Finished Jun 23 05:28:35 PM PDT 24
Peak memory 195952 kb
Host smart-340a88e8-0c7f-4718-a1d4-3798cfb29935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523621582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1523621582
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.748941120
Short name T361
Test name
Test status
Simulation time 72002166 ps
CPU time 0.72 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:28:34 PM PDT 24
Peak memory 195368 kb
Host smart-14106d3e-983e-470d-a0a3-0ffa2446c470
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748941120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.748941120
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1640059568
Short name T161
Test name
Test status
Simulation time 39313920 ps
CPU time 1.86 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:34 PM PDT 24
Peak memory 198008 kb
Host smart-58e06a2e-3558-483a-86b4-c4f972a1e2f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640059568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1640059568
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.3121331010
Short name T490
Test name
Test status
Simulation time 65379123 ps
CPU time 1.15 seconds
Started Jun 23 05:28:34 PM PDT 24
Finished Jun 23 05:28:35 PM PDT 24
Peak memory 196512 kb
Host smart-cabacea3-581b-4505-a3b7-094fbb569176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121331010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.3121331010
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.42876032
Short name T306
Test name
Test status
Simulation time 163675662 ps
CPU time 0.97 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:28:34 PM PDT 24
Peak memory 197232 kb
Host smart-99e42db2-a858-4252-8a01-ae9b0d2cf944
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42876032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.42876032
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1079794910
Short name T449
Test name
Test status
Simulation time 37111248122 ps
CPU time 66.93 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:29:43 PM PDT 24
Peak memory 198020 kb
Host smart-859abdc2-1e54-4cc0-b009-485f532c5242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079794910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1079794910
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.4263647760
Short name T291
Test name
Test status
Simulation time 23051120938 ps
CPU time 554.84 seconds
Started Jun 23 05:28:33 PM PDT 24
Finished Jun 23 05:37:48 PM PDT 24
Peak memory 198224 kb
Host smart-f230b026-8b78-482d-94ef-8ec6bb3e74bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4263647760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.4263647760
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.970443764
Short name T335
Test name
Test status
Simulation time 50329575 ps
CPU time 0.56 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:37 PM PDT 24
Peak memory 193928 kb
Host smart-a4bffbac-69fa-48d8-985f-a5a18ba85de0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970443764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.970443764
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3737006384
Short name T47
Test name
Test status
Simulation time 43406479 ps
CPU time 0.78 seconds
Started Jun 23 05:28:34 PM PDT 24
Finished Jun 23 05:28:36 PM PDT 24
Peak memory 195600 kb
Host smart-304395fb-61b7-46af-8cb2-1c12e212ab66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737006384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3737006384
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.443340141
Short name T269
Test name
Test status
Simulation time 682418189 ps
CPU time 5.08 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:28:40 PM PDT 24
Peak memory 195888 kb
Host smart-0c0b6ccf-2303-4dca-a8cb-1d8fd93ed8dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443340141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.443340141
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3214736297
Short name T346
Test name
Test status
Simulation time 60881845 ps
CPU time 0.9 seconds
Started Jun 23 05:28:43 PM PDT 24
Finished Jun 23 05:28:45 PM PDT 24
Peak memory 197092 kb
Host smart-a8283434-7690-48b4-8602-ff940ce06efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214736297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3214736297
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.1429780507
Short name T112
Test name
Test status
Simulation time 72214854 ps
CPU time 0.68 seconds
Started Jun 23 05:28:39 PM PDT 24
Finished Jun 23 05:28:41 PM PDT 24
Peak memory 194312 kb
Host smart-4c7a029d-9f6c-465d-802d-fca7a9e0fa42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429780507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.1429780507
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.457577933
Short name T105
Test name
Test status
Simulation time 89606104 ps
CPU time 1.85 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:39 PM PDT 24
Peak memory 198172 kb
Host smart-aba33447-c664-4f96-b1df-35a1b260e017
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457577933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.457577933
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.2061342307
Short name T541
Test name
Test status
Simulation time 31679177 ps
CPU time 0.93 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:37 PM PDT 24
Peak memory 194392 kb
Host smart-582ea256-2831-4b82-80d3-dabc413918bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061342307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.2061342307
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1449228476
Short name T431
Test name
Test status
Simulation time 50860046 ps
CPU time 0.98 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:32 PM PDT 24
Peak memory 196804 kb
Host smart-5d6592fc-ddc6-495d-82cd-1c35683ea7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449228476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1449228476
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.4203599137
Short name T174
Test name
Test status
Simulation time 39406540 ps
CPU time 1.02 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:28:36 PM PDT 24
Peak memory 196964 kb
Host smart-17d15a07-fa53-43df-bca6-41108bd48c1c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203599137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.4203599137
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.271169845
Short name T132
Test name
Test status
Simulation time 79503723 ps
CPU time 2 seconds
Started Jun 23 05:28:39 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 197956 kb
Host smart-f21f8ffd-ad9e-4e45-ac81-bec7eee0d6d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271169845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.271169845
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3126680817
Short name T366
Test name
Test status
Simulation time 103600625 ps
CPU time 1.04 seconds
Started Jun 23 05:28:31 PM PDT 24
Finished Jun 23 05:28:33 PM PDT 24
Peak memory 196488 kb
Host smart-30fab7cd-033b-4b24-bf9f-070af0704217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126680817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3126680817
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1563241806
Short name T422
Test name
Test status
Simulation time 106303628 ps
CPU time 1.53 seconds
Started Jun 23 05:28:32 PM PDT 24
Finished Jun 23 05:28:34 PM PDT 24
Peak memory 195564 kb
Host smart-071600d9-8050-4609-8af2-83086d836fcb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563241806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1563241806
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1277836020
Short name T519
Test name
Test status
Simulation time 18060890405 ps
CPU time 133.35 seconds
Started Jun 23 05:28:33 PM PDT 24
Finished Jun 23 05:30:47 PM PDT 24
Peak memory 198160 kb
Host smart-cedb2607-96a1-4889-a052-512ff6aa39f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277836020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1277836020
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.3269650193
Short name T56
Test name
Test status
Simulation time 52580694505 ps
CPU time 1501.16 seconds
Started Jun 23 05:28:38 PM PDT 24
Finished Jun 23 05:53:40 PM PDT 24
Peak memory 198276 kb
Host smart-0703c5ae-34f9-430f-94d9-b9e65e720749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3269650193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.3269650193
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1871324431
Short name T523
Test name
Test status
Simulation time 84199456 ps
CPU time 0.6 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:41 PM PDT 24
Peak memory 194684 kb
Host smart-fd2370c0-fb3b-4dfa-942b-741fb7455601
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871324431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1871324431
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2583749662
Short name T583
Test name
Test status
Simulation time 32297436 ps
CPU time 0.81 seconds
Started Jun 23 05:28:34 PM PDT 24
Finished Jun 23 05:28:35 PM PDT 24
Peak memory 195392 kb
Host smart-0d7b211e-1ef1-4fc7-b1db-0b710dd2d7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583749662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2583749662
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.615522512
Short name T708
Test name
Test status
Simulation time 2767773018 ps
CPU time 8.54 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:50 PM PDT 24
Peak memory 195860 kb
Host smart-b0b921c7-512b-4018-bad2-f67badf3d1f9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615522512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.615522512
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.1699552189
Short name T432
Test name
Test status
Simulation time 598062048 ps
CPU time 0.9 seconds
Started Jun 23 05:28:34 PM PDT 24
Finished Jun 23 05:28:36 PM PDT 24
Peak memory 197096 kb
Host smart-f627638e-6dce-419a-afbb-b7ee399290cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699552189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.1699552189
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.1772424879
Short name T542
Test name
Test status
Simulation time 146167340 ps
CPU time 1.09 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 196476 kb
Host smart-20a4b203-2776-4bfc-8a18-b65c9235b055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772424879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.1772424879
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1296983121
Short name T213
Test name
Test status
Simulation time 84778646 ps
CPU time 3.25 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:28:46 PM PDT 24
Peak memory 197936 kb
Host smart-1ae18abf-a0cd-4422-887a-c7c1baf48e40
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296983121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1296983121
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.992345799
Short name T567
Test name
Test status
Simulation time 592103125 ps
CPU time 3.1 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 196916 kb
Host smart-f859241c-b2e5-4d79-9c01-86f2580fb42a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992345799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
992345799
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2794857046
Short name T319
Test name
Test status
Simulation time 56401824 ps
CPU time 0.83 seconds
Started Jun 23 05:28:34 PM PDT 24
Finished Jun 23 05:28:36 PM PDT 24
Peak memory 196668 kb
Host smart-d01a93b0-86f1-4aa6-8a34-439f844e93b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794857046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2794857046
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2324811796
Short name T645
Test name
Test status
Simulation time 169559087 ps
CPU time 0.97 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:37 PM PDT 24
Peak memory 196008 kb
Host smart-c14b16ee-7f9c-42ca-9bf1-2774d128fa48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324811796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2324811796
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2428200920
Short name T588
Test name
Test status
Simulation time 2091379416 ps
CPU time 5.3 seconds
Started Jun 23 05:28:44 PM PDT 24
Finished Jun 23 05:28:50 PM PDT 24
Peak memory 197868 kb
Host smart-65002d4f-deb5-4702-aa3b-f36f4d53b224
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428200920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2428200920
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3985834516
Short name T618
Test name
Test status
Simulation time 37064320 ps
CPU time 0.85 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 196036 kb
Host smart-6ef40924-4299-460a-bce1-9e9847beecc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985834516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3985834516
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.209926315
Short name T540
Test name
Test status
Simulation time 48113814 ps
CPU time 1.3 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:38 PM PDT 24
Peak memory 196680 kb
Host smart-bac8f3e3-1dd1-4dfa-a0d7-f93093332f7d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209926315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.209926315
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3004208409
Short name T187
Test name
Test status
Simulation time 16618517217 ps
CPU time 107.32 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:30:38 PM PDT 24
Peak memory 198064 kb
Host smart-e0711649-f80f-47aa-b76a-d21ee4710d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004208409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3004208409
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3508061416
Short name T502
Test name
Test status
Simulation time 67862937 ps
CPU time 0.58 seconds
Started Jun 23 05:28:47 PM PDT 24
Finished Jun 23 05:28:48 PM PDT 24
Peak memory 193964 kb
Host smart-107a0848-8c00-4a0b-ac0e-4b231eff835d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508061416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3508061416
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3820004179
Short name T674
Test name
Test status
Simulation time 36624319 ps
CPU time 0.76 seconds
Started Jun 23 05:28:41 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 195108 kb
Host smart-f4b0e37c-9e72-4362-8528-ae24e3a0cfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820004179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3820004179
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.57636633
Short name T667
Test name
Test status
Simulation time 1828778373 ps
CPU time 28.38 seconds
Started Jun 23 05:28:46 PM PDT 24
Finished Jun 23 05:29:15 PM PDT 24
Peak memory 196212 kb
Host smart-3ed28dc9-94e4-4f69-ad5f-7cb1930c3025
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57636633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stress
.57636633
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3731801984
Short name T257
Test name
Test status
Simulation time 82628826 ps
CPU time 0.72 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 194700 kb
Host smart-1a760f33-16c5-4e57-a270-658d58668bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731801984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3731801984
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.567553963
Short name T282
Test name
Test status
Simulation time 128240567 ps
CPU time 1.3 seconds
Started Jun 23 05:28:38 PM PDT 24
Finished Jun 23 05:28:40 PM PDT 24
Peak memory 196140 kb
Host smart-1a92b5e2-3fe6-4221-b8f9-85a807234762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567553963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.567553963
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2453970950
Short name T244
Test name
Test status
Simulation time 380164462 ps
CPU time 3.29 seconds
Started Jun 23 05:28:41 PM PDT 24
Finished Jun 23 05:28:45 PM PDT 24
Peak memory 198028 kb
Host smart-a782598e-52d9-49ec-99e0-cee50b6b67cc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453970950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2453970950
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.354199232
Short name T223
Test name
Test status
Simulation time 101922347 ps
CPU time 3.19 seconds
Started Jun 23 05:28:38 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 198100 kb
Host smart-c33b9d29-40b1-4eb8-a826-1d45f13f13f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354199232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
354199232
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.656979196
Short name T652
Test name
Test status
Simulation time 330521161 ps
CPU time 1.15 seconds
Started Jun 23 05:28:39 PM PDT 24
Finished Jun 23 05:28:40 PM PDT 24
Peak memory 196068 kb
Host smart-0d205477-bae4-46e9-a2c1-f38480e46896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656979196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.656979196
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3111877739
Short name T200
Test name
Test status
Simulation time 220472255 ps
CPU time 1.09 seconds
Started Jun 23 05:28:43 PM PDT 24
Finished Jun 23 05:28:45 PM PDT 24
Peak memory 196688 kb
Host smart-879e805b-3c32-46ea-923b-49b873aeca97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111877739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3111877739
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2830039921
Short name T10
Test name
Test status
Simulation time 290162713 ps
CPU time 3.71 seconds
Started Jun 23 05:28:45 PM PDT 24
Finished Jun 23 05:28:49 PM PDT 24
Peak memory 197980 kb
Host smart-6a382b24-9380-43fa-943b-3fce66c716f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830039921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2830039921
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.145377709
Short name T154
Test name
Test status
Simulation time 42927880 ps
CPU time 0.93 seconds
Started Jun 23 05:28:35 PM PDT 24
Finished Jun 23 05:28:36 PM PDT 24
Peak memory 195680 kb
Host smart-f2ac3bcc-1ce5-47e4-bbfb-eb92fd55ce76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145377709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.145377709
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3896408835
Short name T195
Test name
Test status
Simulation time 63378772 ps
CPU time 1.11 seconds
Started Jun 23 05:28:36 PM PDT 24
Finished Jun 23 05:28:38 PM PDT 24
Peak memory 195544 kb
Host smart-b88b92c7-ab77-4d64-ae01-b66ce877e735
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896408835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3896408835
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2001596524
Short name T531
Test name
Test status
Simulation time 19054095578 ps
CPU time 179.73 seconds
Started Jun 23 05:28:38 PM PDT 24
Finished Jun 23 05:31:38 PM PDT 24
Peak memory 198180 kb
Host smart-0b5e3ce5-0a91-4bfb-8d8d-a9785352ce27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001596524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2001596524
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.3524476142
Short name T166
Test name
Test status
Simulation time 19426475 ps
CPU time 0.56 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:17 PM PDT 24
Peak memory 194540 kb
Host smart-8c3ab039-da94-4a4f-be18-3f4ba59cb89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524476142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.3524476142
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3456526218
Short name T12
Test name
Test status
Simulation time 23920161 ps
CPU time 0.74 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 194136 kb
Host smart-e301d116-34a4-4047-a827-38dcf310d15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456526218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3456526218
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1744640016
Short name T126
Test name
Test status
Simulation time 173498383 ps
CPU time 8.62 seconds
Started Jun 23 05:28:08 PM PDT 24
Finished Jun 23 05:28:17 PM PDT 24
Peak memory 197012 kb
Host smart-29222a4d-f948-47e9-97ca-4699f3fcc71d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744640016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1744640016
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2081367420
Short name T351
Test name
Test status
Simulation time 54669823 ps
CPU time 0.84 seconds
Started Jun 23 05:28:12 PM PDT 24
Finished Jun 23 05:28:13 PM PDT 24
Peak memory 196616 kb
Host smart-4d007eef-82b8-4a0a-bc54-df46314287a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081367420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2081367420
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1985088858
Short name T625
Test name
Test status
Simulation time 97673305 ps
CPU time 1.32 seconds
Started Jun 23 05:28:13 PM PDT 24
Finished Jun 23 05:28:15 PM PDT 24
Peak memory 196712 kb
Host smart-6560291f-7a2f-4224-adac-080dd820aefe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985088858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1985088858
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1544040590
Short name T610
Test name
Test status
Simulation time 1729228539 ps
CPU time 3.83 seconds
Started Jun 23 05:28:07 PM PDT 24
Finished Jun 23 05:28:12 PM PDT 24
Peak memory 198100 kb
Host smart-44308c04-1224-4608-9b4e-0ce840087652
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544040590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1544040590
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.486842329
Short name T216
Test name
Test status
Simulation time 63789860 ps
CPU time 2 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 197024 kb
Host smart-0d211fdd-2878-4afd-a412-69b7f586fb00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486842329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.486842329
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.4033608389
Short name T700
Test name
Test status
Simulation time 201954781 ps
CPU time 1.11 seconds
Started Jun 23 05:28:10 PM PDT 24
Finished Jun 23 05:28:12 PM PDT 24
Peak memory 195852 kb
Host smart-43aa6576-4746-4607-8d65-682bd626ad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033608389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.4033608389
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3581955592
Short name T113
Test name
Test status
Simulation time 22213894 ps
CPU time 0.7 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:10 PM PDT 24
Peak memory 194232 kb
Host smart-871f8243-e124-405e-8f21-ae7308dfa5b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581955592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3581955592
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1384686019
Short name T480
Test name
Test status
Simulation time 50434636 ps
CPU time 2.49 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 197988 kb
Host smart-f2db7674-6d59-4608-925e-1793f2be7e5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384686019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1384686019
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1040522364
Short name T36
Test name
Test status
Simulation time 77665012 ps
CPU time 0.94 seconds
Started Jun 23 05:28:08 PM PDT 24
Finished Jun 23 05:28:10 PM PDT 24
Peak memory 214792 kb
Host smart-5207787c-e35b-4087-99e8-0a5184ab6990
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040522364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1040522364
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2061036645
Short name T425
Test name
Test status
Simulation time 335765246 ps
CPU time 1.45 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:20 PM PDT 24
Peak memory 198008 kb
Host smart-b8dd5adc-bfb6-4417-a0e6-cf4d769150a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061036645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2061036645
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3014523488
Short name T186
Test name
Test status
Simulation time 303468664 ps
CPU time 1.52 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:12 PM PDT 24
Peak memory 198036 kb
Host smart-0d788500-998b-4eac-bd2d-1c0c12cff379
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014523488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3014523488
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.4135529872
Short name T129
Test name
Test status
Simulation time 22903516444 ps
CPU time 68.36 seconds
Started Jun 23 05:28:10 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 198140 kb
Host smart-0db084b2-9e89-4832-9065-d04691a4654e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135529872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.4135529872
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1119032310
Short name T488
Test name
Test status
Simulation time 46456121 ps
CPU time 0.59 seconds
Started Jun 23 05:28:41 PM PDT 24
Finished Jun 23 05:28:43 PM PDT 24
Peak memory 194748 kb
Host smart-3c013d62-cbd9-4081-b99a-fa97e4b17364
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119032310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1119032310
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.4225700911
Short name T654
Test name
Test status
Simulation time 14835778 ps
CPU time 0.64 seconds
Started Jun 23 05:28:41 PM PDT 24
Finished Jun 23 05:28:43 PM PDT 24
Peak memory 193912 kb
Host smart-64e12a3f-42fc-4797-a663-fb53f44f9151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225700911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.4225700911
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.2600529076
Short name T420
Test name
Test status
Simulation time 274296020 ps
CPU time 7.31 seconds
Started Jun 23 05:28:47 PM PDT 24
Finished Jun 23 05:28:54 PM PDT 24
Peak memory 196888 kb
Host smart-dd9e1598-414f-4623-9174-011f66ed6364
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600529076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.2600529076
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.3444450721
Short name T597
Test name
Test status
Simulation time 48354111 ps
CPU time 0.87 seconds
Started Jun 23 05:28:39 PM PDT 24
Finished Jun 23 05:28:40 PM PDT 24
Peak memory 196100 kb
Host smart-bfb3989d-c8a1-4a46-ba80-04fc072e67f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444450721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.3444450721
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2806717640
Short name T595
Test name
Test status
Simulation time 66846773 ps
CPU time 1.03 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 196184 kb
Host smart-a1b9d4c0-a6fa-4db6-9f34-4a7ff608e58c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806717640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2806717640
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.2026686152
Short name T181
Test name
Test status
Simulation time 180334160 ps
CPU time 2.75 seconds
Started Jun 23 05:28:52 PM PDT 24
Finished Jun 23 05:28:55 PM PDT 24
Peak memory 196392 kb
Host smart-c263194b-c816-4baa-9b4d-824e65a01386
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026686152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.2026686152
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3168868039
Short name T460
Test name
Test status
Simulation time 135607590 ps
CPU time 3.41 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 197044 kb
Host smart-39515138-02ff-4a24-8baf-4c5c91ff82c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168868039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3168868039
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.4210646287
Short name T376
Test name
Test status
Simulation time 123458194 ps
CPU time 0.83 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:41 PM PDT 24
Peak memory 197204 kb
Host smart-943e6ae0-7bf9-436f-80dd-4af205183541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210646287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.4210646287
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3866807611
Short name T418
Test name
Test status
Simulation time 22325025 ps
CPU time 0.9 seconds
Started Jun 23 05:28:48 PM PDT 24
Finished Jun 23 05:28:49 PM PDT 24
Peak memory 196692 kb
Host smart-0e0634b8-8d9f-4d24-a863-28203fc46265
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866807611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3866807611
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1981500283
Short name T416
Test name
Test status
Simulation time 385105007 ps
CPU time 4.76 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:46 PM PDT 24
Peak memory 198008 kb
Host smart-a52979d9-cea4-444f-8c48-4fa9300383f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981500283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1981500283
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.992713418
Short name T242
Test name
Test status
Simulation time 139249678 ps
CPU time 1.13 seconds
Started Jun 23 05:28:37 PM PDT 24
Finished Jun 23 05:28:39 PM PDT 24
Peak memory 195788 kb
Host smart-c06925f9-5dec-4bd6-bfb3-5739901e23d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992713418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.992713418
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3731729424
Short name T345
Test name
Test status
Simulation time 134332020 ps
CPU time 0.87 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 195312 kb
Host smart-cb031a9a-de52-4672-928c-4ec20c09207a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731729424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3731729424
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.2663258547
Short name T339
Test name
Test status
Simulation time 20458847449 ps
CPU time 139.45 seconds
Started Jun 23 05:28:46 PM PDT 24
Finished Jun 23 05:31:06 PM PDT 24
Peak memory 198156 kb
Host smart-fe9c8d6d-f677-4205-9aab-5676512e96da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663258547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.2663258547
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1860470108
Short name T686
Test name
Test status
Simulation time 286030402301 ps
CPU time 644.28 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:39:35 PM PDT 24
Peak memory 206444 kb
Host smart-045461f2-8abd-4804-b65d-2dfd5bfe908d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1860470108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1860470108
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.4172607556
Short name T638
Test name
Test status
Simulation time 23406813 ps
CPU time 0.58 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:41 PM PDT 24
Peak memory 193824 kb
Host smart-bf67eeae-476d-4a94-8180-6eee0e85b210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172607556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.4172607556
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1067503279
Short name T704
Test name
Test status
Simulation time 130395558 ps
CPU time 0.86 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 196156 kb
Host smart-242782ec-fb7d-4301-974c-681397c3f7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067503279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1067503279
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.551586326
Short name T609
Test name
Test status
Simulation time 2311375942 ps
CPU time 20.59 seconds
Started Jun 23 05:28:41 PM PDT 24
Finished Jun 23 05:29:02 PM PDT 24
Peak memory 196660 kb
Host smart-097cedd8-277d-4f94-a2cd-fdea5cf14cf8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551586326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.551586326
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.969510755
Short name T553
Test name
Test status
Simulation time 52362885 ps
CPU time 0.8 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:28:51 PM PDT 24
Peak memory 196584 kb
Host smart-6c312386-9774-485c-a666-636affa42eeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969510755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.969510755
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.72048039
Short name T404
Test name
Test status
Simulation time 465741677 ps
CPU time 0.74 seconds
Started Jun 23 05:28:38 PM PDT 24
Finished Jun 23 05:28:39 PM PDT 24
Peak memory 196192 kb
Host smart-c5efa01c-8e73-4a21-82e1-fbeddbae57da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72048039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.72048039
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.432201378
Short name T145
Test name
Test status
Simulation time 133222460 ps
CPU time 1.6 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 198176 kb
Host smart-79f2a260-6a27-4099-b360-f72ab95cb08d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432201378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.432201378
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2772654515
Short name T13
Test name
Test status
Simulation time 154415574 ps
CPU time 2.26 seconds
Started Jun 23 05:28:41 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 198136 kb
Host smart-5203095e-4545-4716-94c1-282a8655fee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772654515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2772654515
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1127300597
Short name T578
Test name
Test status
Simulation time 50400707 ps
CPU time 1.08 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 196720 kb
Host smart-2f1b0340-d0bc-4d02-94ed-92d919017cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127300597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1127300597
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3422964818
Short name T613
Test name
Test status
Simulation time 240066455 ps
CPU time 1.31 seconds
Started Jun 23 05:28:53 PM PDT 24
Finished Jun 23 05:28:55 PM PDT 24
Peak memory 195708 kb
Host smart-548405f8-79d2-4e58-a7c5-0fe1f25ca5b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422964818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3422964818
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.4023903583
Short name T19
Test name
Test status
Simulation time 2613196133 ps
CPU time 5.92 seconds
Started Jun 23 05:28:53 PM PDT 24
Finished Jun 23 05:28:59 PM PDT 24
Peak memory 197896 kb
Host smart-c7d28395-e35f-40b5-bd23-f2eb37a86063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023903583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.4023903583
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.2296301618
Short name T135
Test name
Test status
Simulation time 29664790 ps
CPU time 0.73 seconds
Started Jun 23 05:28:51 PM PDT 24
Finished Jun 23 05:28:52 PM PDT 24
Peak memory 194088 kb
Host smart-c3911702-304d-4946-be2a-b52d92b506eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296301618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.2296301618
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1568248876
Short name T423
Test name
Test status
Simulation time 52322261 ps
CPU time 1.38 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 198004 kb
Host smart-00c4df0a-d66c-4f26-87ec-ec85aca06c7b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568248876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1568248876
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2882267871
Short name T28
Test name
Test status
Simulation time 2894950489 ps
CPU time 77.54 seconds
Started Jun 23 05:28:51 PM PDT 24
Finished Jun 23 05:30:09 PM PDT 24
Peak memory 198204 kb
Host smart-7368e278-dd8e-4de5-b0a6-5e804b32f680
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882267871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2882267871
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3026029466
Short name T91
Test name
Test status
Simulation time 414541579676 ps
CPU time 1319.28 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:50:42 PM PDT 24
Peak memory 198212 kb
Host smart-f6ee17e2-e21f-4248-9476-2765e23c98b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3026029466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3026029466
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.4213808448
Short name T235
Test name
Test status
Simulation time 71614006 ps
CPU time 0.58 seconds
Started Jun 23 05:28:48 PM PDT 24
Finished Jun 23 05:28:49 PM PDT 24
Peak memory 194024 kb
Host smart-5e23dc0f-6cd3-47d3-8fad-fe4bc19dc03f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213808448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.4213808448
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2994993356
Short name T538
Test name
Test status
Simulation time 54341674 ps
CPU time 0.62 seconds
Started Jun 23 05:28:44 PM PDT 24
Finished Jun 23 05:28:45 PM PDT 24
Peak memory 193932 kb
Host smart-30e9f9cf-129d-441a-a815-a9f556452d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994993356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2994993356
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.487516038
Short name T399
Test name
Test status
Simulation time 808575936 ps
CPU time 22.72 seconds
Started Jun 23 05:28:48 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 197012 kb
Host smart-0a311042-003a-4b33-9133-ea874bf5a830
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487516038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.487516038
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2759539470
Short name T156
Test name
Test status
Simulation time 158415778 ps
CPU time 0.96 seconds
Started Jun 23 05:28:44 PM PDT 24
Finished Jun 23 05:28:45 PM PDT 24
Peak memory 197912 kb
Host smart-185e9b53-2c6a-4c91-ba9a-b7f547380cc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759539470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2759539470
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.4171205088
Short name T633
Test name
Test status
Simulation time 45203130 ps
CPU time 0.89 seconds
Started Jun 23 05:28:49 PM PDT 24
Finished Jun 23 05:28:50 PM PDT 24
Peak memory 196384 kb
Host smart-d006832a-2c0a-4545-aed0-2ad49112bb14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171205088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.4171205088
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.864838266
Short name T692
Test name
Test status
Simulation time 840069076 ps
CPU time 3.51 seconds
Started Jun 23 05:28:48 PM PDT 24
Finished Jun 23 05:28:52 PM PDT 24
Peak memory 198156 kb
Host smart-0173fb00-7ba9-41a7-8a38-dac48836858f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864838266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.864838266
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1323930307
Short name T626
Test name
Test status
Simulation time 238816616 ps
CPU time 1.35 seconds
Started Jun 23 05:28:46 PM PDT 24
Finished Jun 23 05:28:47 PM PDT 24
Peak memory 197460 kb
Host smart-c15e9973-21bd-4e22-813d-884a5aefe7b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323930307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1323930307
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2458464115
Short name T537
Test name
Test status
Simulation time 62743945 ps
CPU time 0.91 seconds
Started Jun 23 05:28:53 PM PDT 24
Finished Jun 23 05:28:54 PM PDT 24
Peak memory 195652 kb
Host smart-68515ebf-f9c1-4c3c-bb0f-884b102c05ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458464115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2458464115
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.4236654043
Short name T535
Test name
Test status
Simulation time 85413035 ps
CPU time 0.78 seconds
Started Jun 23 05:29:02 PM PDT 24
Finished Jun 23 05:29:03 PM PDT 24
Peak memory 195376 kb
Host smart-ed8f8c74-5b22-45e0-a4c6-c26e50f81ecf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236654043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.4236654043
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1837203071
Short name T550
Test name
Test status
Simulation time 632168235 ps
CPU time 3.86 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:28:55 PM PDT 24
Peak memory 197880 kb
Host smart-68d6d1fd-c5eb-4b8d-9ab0-aead460e6eb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837203071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1837203071
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2097701268
Short name T292
Test name
Test status
Simulation time 49963150 ps
CPU time 0.79 seconds
Started Jun 23 05:28:45 PM PDT 24
Finished Jun 23 05:28:47 PM PDT 24
Peak memory 195848 kb
Host smart-ddce2b5e-9ac0-446e-85c6-0d75c978d345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097701268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2097701268
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.386814380
Short name T153
Test name
Test status
Simulation time 319545317 ps
CPU time 1.21 seconds
Started Jun 23 05:28:40 PM PDT 24
Finished Jun 23 05:28:42 PM PDT 24
Peak memory 196692 kb
Host smart-0c3582ed-0939-43b5-8f0b-8e55dfa08aac
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386814380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.386814380
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2252997517
Short name T99
Test name
Test status
Simulation time 34856180645 ps
CPU time 90.73 seconds
Started Jun 23 05:28:43 PM PDT 24
Finished Jun 23 05:30:15 PM PDT 24
Peak memory 198164 kb
Host smart-a688e22d-70cc-4a1d-b8bc-96c61eb3db07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252997517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2252997517
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1606337370
Short name T575
Test name
Test status
Simulation time 45542312 ps
CPU time 0.57 seconds
Started Jun 23 05:28:57 PM PDT 24
Finished Jun 23 05:28:58 PM PDT 24
Peak memory 193784 kb
Host smart-15b8db06-5d0e-42f6-a784-d0e40529972f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606337370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1606337370
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1886331248
Short name T111
Test name
Test status
Simulation time 28627028 ps
CPU time 0.66 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:28:44 PM PDT 24
Peak memory 194080 kb
Host smart-797ac788-2114-4a0a-9492-33213574e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886331248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1886331248
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3330453018
Short name T64
Test name
Test status
Simulation time 1304671062 ps
CPU time 15.9 seconds
Started Jun 23 05:28:43 PM PDT 24
Finished Jun 23 05:28:59 PM PDT 24
Peak memory 197956 kb
Host smart-b4500fa4-190a-476c-8a81-e33e904fe880
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330453018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3330453018
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.2017039621
Short name T670
Test name
Test status
Simulation time 228089972 ps
CPU time 0.88 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:28:52 PM PDT 24
Peak memory 195972 kb
Host smart-5c86782b-55f4-4732-a34f-0bf60ced794d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017039621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.2017039621
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.3670970630
Short name T331
Test name
Test status
Simulation time 409770338 ps
CPU time 1.18 seconds
Started Jun 23 05:28:45 PM PDT 24
Finished Jun 23 05:28:47 PM PDT 24
Peak memory 196156 kb
Host smart-48ee945f-1e0a-4239-934f-01f2297830a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670970630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.3670970630
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2999340947
Short name T198
Test name
Test status
Simulation time 63033444 ps
CPU time 2.24 seconds
Started Jun 23 05:28:42 PM PDT 24
Finished Jun 23 05:28:45 PM PDT 24
Peak memory 198088 kb
Host smart-eb1e2111-82e7-4929-92fa-e8e19465fbc0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999340947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2999340947
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.66356060
Short name T601
Test name
Test status
Simulation time 412187291 ps
CPU time 3.24 seconds
Started Jun 23 05:28:43 PM PDT 24
Finished Jun 23 05:28:47 PM PDT 24
Peak memory 197332 kb
Host smart-c4f41ea7-ddf1-4b83-8613-0c8516f4166f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66356060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger.66356060
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.2474180913
Short name T11
Test name
Test status
Simulation time 171426813 ps
CPU time 1.11 seconds
Started Jun 23 05:28:49 PM PDT 24
Finished Jun 23 05:28:50 PM PDT 24
Peak memory 195956 kb
Host smart-fbb4368e-2ff0-4ea4-931b-629f93355357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474180913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.2474180913
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.676316554
Short name T663
Test name
Test status
Simulation time 30021800 ps
CPU time 0.77 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:28:51 PM PDT 24
Peak memory 196200 kb
Host smart-6b292cf5-0462-4c7c-a744-6e68390582c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676316554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.676316554
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2784006949
Short name T167
Test name
Test status
Simulation time 63293725 ps
CPU time 2.29 seconds
Started Jun 23 05:28:47 PM PDT 24
Finished Jun 23 05:28:50 PM PDT 24
Peak memory 197972 kb
Host smart-3ff36a30-5be5-4148-9c4f-677c0ff07529
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784006949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2784006949
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.934166329
Short name T252
Test name
Test status
Simulation time 33938020 ps
CPU time 1.08 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:28:51 PM PDT 24
Peak memory 195560 kb
Host smart-38eb0f92-b10a-4f5f-a5b7-9da96774c11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934166329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.934166329
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2304901049
Short name T316
Test name
Test status
Simulation time 54881332 ps
CPU time 1.31 seconds
Started Jun 23 05:28:43 PM PDT 24
Finished Jun 23 05:28:45 PM PDT 24
Peak memory 196772 kb
Host smart-53dbcc84-51b0-49c0-9e79-df703f441b12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304901049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2304901049
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2079244978
Short name T496
Test name
Test status
Simulation time 28071279578 ps
CPU time 193.94 seconds
Started Jun 23 05:29:03 PM PDT 24
Finished Jun 23 05:32:17 PM PDT 24
Peak memory 198168 kb
Host smart-0837168d-b256-434a-a27f-215df1088789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079244978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2079244978
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3909930801
Short name T326
Test name
Test status
Simulation time 16033981 ps
CPU time 0.58 seconds
Started Jun 23 05:28:50 PM PDT 24
Finished Jun 23 05:28:52 PM PDT 24
Peak memory 193824 kb
Host smart-cf3a51a6-3825-4fcb-9ed7-f4aa98c33cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909930801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3909930801
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2571873530
Short name T337
Test name
Test status
Simulation time 30108344 ps
CPU time 0.95 seconds
Started Jun 23 05:29:09 PM PDT 24
Finished Jun 23 05:29:10 PM PDT 24
Peak memory 196024 kb
Host smart-08f07549-9aee-4ac8-863a-05130b3aa612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571873530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2571873530
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.443238952
Short name T209
Test name
Test status
Simulation time 890885429 ps
CPU time 21.26 seconds
Started Jun 23 05:28:53 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 196272 kb
Host smart-cb8b6061-b4f7-47d2-ad1e-cf0b5d918c5e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443238952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.443238952
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3037795415
Short name T677
Test name
Test status
Simulation time 40347211 ps
CPU time 0.74 seconds
Started Jun 23 05:28:57 PM PDT 24
Finished Jun 23 05:28:58 PM PDT 24
Peak memory 195616 kb
Host smart-344aa496-6927-4a09-9023-36fca93a09d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037795415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3037795415
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.2247801868
Short name T179
Test name
Test status
Simulation time 106612427 ps
CPU time 1.49 seconds
Started Jun 23 05:28:55 PM PDT 24
Finished Jun 23 05:28:57 PM PDT 24
Peak memory 197260 kb
Host smart-69a6ecdc-2a65-4eb8-8121-4bc403cdc30b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247801868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.2247801868
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3731796282
Short name T250
Test name
Test status
Simulation time 188426987 ps
CPU time 1.13 seconds
Started Jun 23 05:28:55 PM PDT 24
Finished Jun 23 05:28:57 PM PDT 24
Peak memory 197048 kb
Host smart-81c96ede-88a0-449b-88e9-de5d7ce4e950
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731796282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3731796282
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.542816305
Short name T165
Test name
Test status
Simulation time 129752363 ps
CPU time 4.01 seconds
Started Jun 23 05:28:57 PM PDT 24
Finished Jun 23 05:29:02 PM PDT 24
Peak memory 198132 kb
Host smart-79226060-e8a5-4b82-a92b-479e57588855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542816305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
542816305
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.1557937697
Short name T123
Test name
Test status
Simulation time 41984880 ps
CPU time 0.97 seconds
Started Jun 23 05:28:55 PM PDT 24
Finished Jun 23 05:28:56 PM PDT 24
Peak memory 196544 kb
Host smart-4946c998-068c-4e07-98cf-6def4574f938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557937697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.1557937697
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.296442451
Short name T568
Test name
Test status
Simulation time 36546308 ps
CPU time 0.86 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:01 PM PDT 24
Peak memory 195844 kb
Host smart-6f027715-b4fb-44fd-9828-d4fc1aad4c72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296442451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.296442451
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3611637039
Short name T482
Test name
Test status
Simulation time 559593112 ps
CPU time 4.97 seconds
Started Jun 23 05:29:03 PM PDT 24
Finished Jun 23 05:29:08 PM PDT 24
Peak memory 197960 kb
Host smart-cd48b872-a4bd-41e0-9451-ec199eaff9f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611637039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3611637039
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.3847902739
Short name T299
Test name
Test status
Simulation time 1211241408 ps
CPU time 1.56 seconds
Started Jun 23 05:28:55 PM PDT 24
Finished Jun 23 05:28:58 PM PDT 24
Peak memory 196764 kb
Host smart-2b5f2b73-3f77-4aa9-bbb9-75a33dbd22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847902739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.3847902739
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2643538784
Short name T108
Test name
Test status
Simulation time 281434851 ps
CPU time 0.97 seconds
Started Jun 23 05:28:48 PM PDT 24
Finished Jun 23 05:28:49 PM PDT 24
Peak memory 195812 kb
Host smart-bb35befc-76f4-4e68-a83d-cabdc69684f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643538784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2643538784
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2380609927
Short name T136
Test name
Test status
Simulation time 10846278124 ps
CPU time 129.7 seconds
Started Jun 23 05:29:07 PM PDT 24
Finished Jun 23 05:31:17 PM PDT 24
Peak memory 198160 kb
Host smart-e5f7665e-00d4-4bc5-9d8d-14cc06d78cbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380609927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2380609927
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.1115424262
Short name T504
Test name
Test status
Simulation time 23971904874 ps
CPU time 453.88 seconds
Started Jun 23 05:28:58 PM PDT 24
Finished Jun 23 05:36:32 PM PDT 24
Peak memory 198160 kb
Host smart-24aeff26-5353-4ab7-b095-5827f1f32a21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1115424262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.1115424262
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1021962591
Short name T456
Test name
Test status
Simulation time 38204828 ps
CPU time 0.58 seconds
Started Jun 23 05:28:54 PM PDT 24
Finished Jun 23 05:28:56 PM PDT 24
Peak memory 194532 kb
Host smart-1a12b6e5-e9be-4041-91f9-de0c93de34a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021962591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1021962591
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2085883530
Short name T640
Test name
Test status
Simulation time 49933259 ps
CPU time 0.78 seconds
Started Jun 23 05:28:59 PM PDT 24
Finished Jun 23 05:29:01 PM PDT 24
Peak memory 195132 kb
Host smart-2c11aa60-2702-4e1c-a35b-208b9b652616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085883530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2085883530
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3562438655
Short name T436
Test name
Test status
Simulation time 4654094711 ps
CPU time 19.12 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:32 PM PDT 24
Peak memory 198108 kb
Host smart-4dfb9f03-2289-4d7a-951c-7827daa6a875
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562438655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3562438655
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1648006053
Short name T439
Test name
Test status
Simulation time 331103128 ps
CPU time 0.95 seconds
Started Jun 23 05:29:04 PM PDT 24
Finished Jun 23 05:29:05 PM PDT 24
Peak memory 196412 kb
Host smart-c83a022d-b225-4adc-8226-9cb47c7b2f9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648006053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1648006053
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1940565402
Short name T318
Test name
Test status
Simulation time 40534054 ps
CPU time 1.15 seconds
Started Jun 23 05:28:56 PM PDT 24
Finished Jun 23 05:28:58 PM PDT 24
Peak memory 196544 kb
Host smart-3eb9c4ce-9897-4dc7-b247-1a72d8ee0cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940565402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1940565402
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.832781815
Short name T66
Test name
Test status
Simulation time 98317613 ps
CPU time 2.31 seconds
Started Jun 23 05:28:52 PM PDT 24
Finished Jun 23 05:28:55 PM PDT 24
Peak memory 198132 kb
Host smart-c2b934f5-eacc-4a27-a519-ce107f906a89
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832781815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.832781815
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1790082829
Short name T589
Test name
Test status
Simulation time 50509031 ps
CPU time 1.73 seconds
Started Jun 23 05:29:01 PM PDT 24
Finished Jun 23 05:29:03 PM PDT 24
Peak memory 196192 kb
Host smart-31c1f295-d17b-4a97-985e-dbbb4ba700f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790082829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1790082829
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2014805139
Short name T140
Test name
Test status
Simulation time 70536384 ps
CPU time 1.31 seconds
Started Jun 23 05:29:01 PM PDT 24
Finished Jun 23 05:29:03 PM PDT 24
Peak memory 195864 kb
Host smart-84249769-a4c3-4d85-a4e7-192a127ec3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014805139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2014805139
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.21710448
Short name T571
Test name
Test status
Simulation time 19532181 ps
CPU time 0.71 seconds
Started Jun 23 05:28:55 PM PDT 24
Finished Jun 23 05:28:57 PM PDT 24
Peak memory 195452 kb
Host smart-aac84a50-7d10-4ea8-bafa-16bac3837876
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21710448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup_
pulldown.21710448
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1377067950
Short name T263
Test name
Test status
Simulation time 127549193 ps
CPU time 5.39 seconds
Started Jun 23 05:29:05 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 198072 kb
Host smart-4e5b9eec-7a34-4bc4-aca0-5cda28b23da7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377067950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1377067950
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3742094862
Short name T487
Test name
Test status
Simulation time 240006224 ps
CPU time 1.26 seconds
Started Jun 23 05:28:55 PM PDT 24
Finished Jun 23 05:28:57 PM PDT 24
Peak memory 195552 kb
Host smart-4e707973-1d31-458a-8df1-c4f86dd209b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742094862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3742094862
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1548893405
Short name T577
Test name
Test status
Simulation time 75830301 ps
CPU time 1.16 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:02 PM PDT 24
Peak memory 195840 kb
Host smart-568b16ed-1541-4492-b97c-cb2d947a6f6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548893405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1548893405
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3548166307
Short name T451
Test name
Test status
Simulation time 76909512213 ps
CPU time 208.61 seconds
Started Jun 23 05:28:54 PM PDT 24
Finished Jun 23 05:32:23 PM PDT 24
Peak memory 198136 kb
Host smart-83d27314-aa6c-49d6-bcfe-9d17022b24bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548166307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3548166307
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3862842841
Short name T55
Test name
Test status
Simulation time 28091833092 ps
CPU time 845.91 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:43:18 PM PDT 24
Peak memory 198172 kb
Host smart-1a1fddf8-c7e1-47d2-ae7c-a845e90ccb51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3862842841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3862842841
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.457165267
Short name T463
Test name
Test status
Simulation time 107605713 ps
CPU time 0.59 seconds
Started Jun 23 05:28:59 PM PDT 24
Finished Jun 23 05:29:00 PM PDT 24
Peak memory 194028 kb
Host smart-8e56b092-a2f7-4b04-b3d2-4b7c418c1117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457165267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.457165267
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3800425496
Short name T549
Test name
Test status
Simulation time 115841146 ps
CPU time 0.76 seconds
Started Jun 23 05:28:53 PM PDT 24
Finished Jun 23 05:28:55 PM PDT 24
Peak memory 195888 kb
Host smart-7b9e9904-e9ac-43ce-a0a7-f01d7fc7f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800425496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3800425496
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2448662678
Short name T226
Test name
Test status
Simulation time 1007790856 ps
CPU time 7.31 seconds
Started Jun 23 05:28:56 PM PDT 24
Finished Jun 23 05:29:04 PM PDT 24
Peak memory 197612 kb
Host smart-4121fa67-2638-400f-b3da-30bfa15d1f20
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448662678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2448662678
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2421076627
Short name T608
Test name
Test status
Simulation time 93977971 ps
CPU time 0.99 seconds
Started Jun 23 05:28:56 PM PDT 24
Finished Jun 23 05:28:58 PM PDT 24
Peak memory 196560 kb
Host smart-ed098522-f3a6-4025-afe2-961ab7e1fad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421076627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2421076627
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.424848532
Short name T127
Test name
Test status
Simulation time 85050281 ps
CPU time 1.18 seconds
Started Jun 23 05:29:05 PM PDT 24
Finished Jun 23 05:29:07 PM PDT 24
Peak memory 196132 kb
Host smart-37b694b9-abb8-413f-9354-fd6accfd8c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424848532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.424848532
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1584328916
Short name T106
Test name
Test status
Simulation time 278350645 ps
CPU time 2.89 seconds
Started Jun 23 05:28:56 PM PDT 24
Finished Jun 23 05:28:59 PM PDT 24
Peak memory 197560 kb
Host smart-6e680626-92ae-49aa-a813-9ebe49d1ee4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584328916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1584328916
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.164545054
Short name T484
Test name
Test status
Simulation time 299177900 ps
CPU time 1.69 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 196216 kb
Host smart-629d0fe2-6d03-45d0-9d1d-2954de089bf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164545054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
164545054
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1449429434
Short name T293
Test name
Test status
Simulation time 24760098 ps
CPU time 0.91 seconds
Started Jun 23 05:28:55 PM PDT 24
Finished Jun 23 05:28:57 PM PDT 24
Peak memory 196092 kb
Host smart-a8456f8c-a81f-4007-9266-d65a57a39613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449429434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1449429434
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2280893087
Short name T709
Test name
Test status
Simulation time 104166208 ps
CPU time 0.83 seconds
Started Jun 23 05:28:53 PM PDT 24
Finished Jun 23 05:28:54 PM PDT 24
Peak memory 196432 kb
Host smart-5ef22282-a729-447c-ac29-6832f0ecd83f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280893087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2280893087
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.888757289
Short name T308
Test name
Test status
Simulation time 231268393 ps
CPU time 1.72 seconds
Started Jun 23 05:28:59 PM PDT 24
Finished Jun 23 05:29:01 PM PDT 24
Peak memory 197992 kb
Host smart-77074c22-1320-40a5-95e3-bfe002bec635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888757289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.888757289
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.508853208
Short name T357
Test name
Test status
Simulation time 49444258 ps
CPU time 1.31 seconds
Started Jun 23 05:28:57 PM PDT 24
Finished Jun 23 05:28:59 PM PDT 24
Peak memory 197952 kb
Host smart-250ca423-d6ba-417e-abbd-3cae434ffcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508853208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.508853208
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.825855325
Short name T296
Test name
Test status
Simulation time 49924541 ps
CPU time 1.09 seconds
Started Jun 23 05:29:09 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 196480 kb
Host smart-1b0e380e-4d62-4b68-b786-cb23102d7418
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825855325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.825855325
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2216102303
Short name T580
Test name
Test status
Simulation time 8671816836 ps
CPU time 141.73 seconds
Started Jun 23 05:28:58 PM PDT 24
Finished Jun 23 05:31:20 PM PDT 24
Peak memory 198132 kb
Host smart-5b1ded4c-e92a-40f9-81b4-b0df9650a86b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216102303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2216102303
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.983390219
Short name T710
Test name
Test status
Simulation time 395178190950 ps
CPU time 359.42 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:35:11 PM PDT 24
Peak memory 206364 kb
Host smart-8c8ffaa8-9698-4931-adac-512595cf476d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=983390219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.983390219
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.2278505989
Short name T417
Test name
Test status
Simulation time 86843305 ps
CPU time 0.58 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:15 PM PDT 24
Peak memory 194004 kb
Host smart-33fa0cb7-c66e-49e8-9dbc-2c85c7724902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278505989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.2278505989
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2116328071
Short name T327
Test name
Test status
Simulation time 37421882 ps
CPU time 0.78 seconds
Started Jun 23 05:28:56 PM PDT 24
Finished Jun 23 05:28:58 PM PDT 24
Peak memory 195940 kb
Host smart-360222f9-7faa-4c65-898e-bc366975f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116328071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2116328071
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.394175352
Short name T448
Test name
Test status
Simulation time 2866308510 ps
CPU time 22.44 seconds
Started Jun 23 05:28:56 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 197612 kb
Host smart-fe8a7d50-dd99-439f-a6c9-48f93e36e77b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394175352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.394175352
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.517385720
Short name T414
Test name
Test status
Simulation time 81650410 ps
CPU time 0.67 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 194480 kb
Host smart-db7e16d2-62ac-4d7f-ab1a-e0a256be8cd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517385720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.517385720
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.409087232
Short name T342
Test name
Test status
Simulation time 105323158 ps
CPU time 1.2 seconds
Started Jun 23 05:29:07 PM PDT 24
Finished Jun 23 05:29:09 PM PDT 24
Peak memory 196136 kb
Host smart-b82503d4-7e9c-4329-9aa8-75c7ff7222c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409087232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.409087232
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1366183463
Short name T193
Test name
Test status
Simulation time 296878291 ps
CPU time 3.12 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 196476 kb
Host smart-167ac8a4-ea23-4c51-ad00-37547dc01e25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366183463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1366183463
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3324220577
Short name T383
Test name
Test status
Simulation time 267948335 ps
CPU time 2.27 seconds
Started Jun 23 05:29:02 PM PDT 24
Finished Jun 23 05:29:05 PM PDT 24
Peak memory 196968 kb
Host smart-93c994b5-37a1-4b56-b13d-645da34712b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324220577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3324220577
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1844674881
Short name T25
Test name
Test status
Simulation time 34210281 ps
CPU time 0.94 seconds
Started Jun 23 05:28:54 PM PDT 24
Finished Jun 23 05:28:56 PM PDT 24
Peak memory 196000 kb
Host smart-f1187c58-6adb-4885-9035-16491609d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844674881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1844674881
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.1571365920
Short name T631
Test name
Test status
Simulation time 29948795 ps
CPU time 0.68 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:12 PM PDT 24
Peak memory 195080 kb
Host smart-13451a05-94df-452a-b87e-a4eaf55ab6e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571365920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.1571365920
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1229169248
Short name T464
Test name
Test status
Simulation time 147368661 ps
CPU time 3.49 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:04 PM PDT 24
Peak memory 197972 kb
Host smart-54d42ff6-5c07-46ea-9c78-bb838e34c857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229169248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1229169248
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3906820184
Short name T693
Test name
Test status
Simulation time 51702962 ps
CPU time 1.06 seconds
Started Jun 23 05:28:56 PM PDT 24
Finished Jun 23 05:28:58 PM PDT 24
Peak memory 195540 kb
Host smart-b0db2ca7-355f-4928-9cc1-2becc0317eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906820184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3906820184
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3161557110
Short name T622
Test name
Test status
Simulation time 134717845 ps
CPU time 1.17 seconds
Started Jun 23 05:29:07 PM PDT 24
Finished Jun 23 05:29:09 PM PDT 24
Peak memory 195608 kb
Host smart-6a523564-94eb-418e-833c-c52df9c82bca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161557110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3161557110
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.4030786054
Short name T563
Test name
Test status
Simulation time 5904221555 ps
CPU time 74.49 seconds
Started Jun 23 05:29:02 PM PDT 24
Finished Jun 23 05:30:17 PM PDT 24
Peak memory 198108 kb
Host smart-fb0a2a24-07af-4114-8b98-d247e8d4ca18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030786054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.4030786054
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.1262231045
Short name T675
Test name
Test status
Simulation time 14584192 ps
CPU time 0.62 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 193860 kb
Host smart-1df99fc2-9a75-4072-b53e-f2baf452aad9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262231045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.1262231045
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1008842590
Short name T240
Test name
Test status
Simulation time 14084878 ps
CPU time 0.65 seconds
Started Jun 23 05:29:05 PM PDT 24
Finished Jun 23 05:29:06 PM PDT 24
Peak memory 193884 kb
Host smart-dbbfb6bb-8d81-4be4-a48d-d1283afb994d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008842590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1008842590
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.821181268
Short name T661
Test name
Test status
Simulation time 3021693535 ps
CPU time 23.53 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:36 PM PDT 24
Peak memory 198080 kb
Host smart-483b1f7d-2d56-458e-968e-5bd07999ba1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821181268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.821181268
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.388678582
Short name T685
Test name
Test status
Simulation time 37589974 ps
CPU time 0.74 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 195748 kb
Host smart-d81a8177-2427-4291-a8a9-c27c7e416302
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388678582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.388678582
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.631774006
Short name T137
Test name
Test status
Simulation time 22524520 ps
CPU time 0.86 seconds
Started Jun 23 05:29:05 PM PDT 24
Finished Jun 23 05:29:06 PM PDT 24
Peak memory 195576 kb
Host smart-c60dc203-d178-48e1-be33-16fc434239e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631774006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.631774006
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.4185353458
Short name T121
Test name
Test status
Simulation time 188169874 ps
CPU time 3.91 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:04 PM PDT 24
Peak memory 198088 kb
Host smart-f39c1c80-e0cd-428c-9e45-81774e595e05
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185353458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.4185353458
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3043475602
Short name T128
Test name
Test status
Simulation time 95643259 ps
CPU time 1.65 seconds
Started Jun 23 05:29:02 PM PDT 24
Finished Jun 23 05:29:04 PM PDT 24
Peak memory 196832 kb
Host smart-35e2c07c-c028-4717-a661-537e4e6da908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043475602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3043475602
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.4130259282
Short name T94
Test name
Test status
Simulation time 69623488 ps
CPU time 0.7 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 194332 kb
Host smart-f42e788d-86dd-46d9-93c3-4db3c359e343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130259282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.4130259282
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2744720452
Short name T474
Test name
Test status
Simulation time 30157395 ps
CPU time 1.1 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 196852 kb
Host smart-6d8d0bcf-cc77-4e92-9fed-341bb42d40ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744720452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2744720452
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.768543558
Short name T264
Test name
Test status
Simulation time 152642209 ps
CPU time 1.63 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:02 PM PDT 24
Peak memory 197992 kb
Host smart-58f438ff-1214-4eef-9c60-e31611dd8451
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768543558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ran
dom_long_reg_writes_reg_reads.768543558
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1241689090
Short name T183
Test name
Test status
Simulation time 149784908 ps
CPU time 1.13 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 196432 kb
Host smart-f717d09d-cf69-4b47-aac6-ff1db02106da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241689090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1241689090
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1723465253
Short name T272
Test name
Test status
Simulation time 84699299 ps
CPU time 1.32 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:12 PM PDT 24
Peak memory 196472 kb
Host smart-f4891766-9921-4fb5-80c8-c296ab098de0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723465253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1723465253
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3836823668
Short name T644
Test name
Test status
Simulation time 11458142230 ps
CPU time 156.71 seconds
Started Jun 23 05:29:05 PM PDT 24
Finished Jun 23 05:31:43 PM PDT 24
Peak memory 198208 kb
Host smart-d5fc455c-eb95-4d65-816b-540596b15c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836823668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3836823668
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2328459827
Short name T301
Test name
Test status
Simulation time 122582913 ps
CPU time 0.58 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 193860 kb
Host smart-9fa82f1b-0150-4704-9270-01b4951ebc7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328459827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2328459827
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.702982302
Short name T114
Test name
Test status
Simulation time 29506995 ps
CPU time 0.8 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 195472 kb
Host smart-4b0ae5a2-ec69-4ab0-b4dd-d0958d38a19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702982302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.702982302
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3525716556
Short name T707
Test name
Test status
Simulation time 3782541713 ps
CPU time 24.74 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:25 PM PDT 24
Peak memory 198164 kb
Host smart-7ab6395f-06ea-4cf4-a1aa-e8f75396d141
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525716556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3525716556
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.619805018
Short name T358
Test name
Test status
Simulation time 57978559 ps
CPU time 0.92 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:12 PM PDT 24
Peak memory 196136 kb
Host smart-2d6b3682-1e3d-462a-af82-c93251e0ff44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619805018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.619805018
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2212955692
Short name T367
Test name
Test status
Simulation time 79231900 ps
CPU time 1.22 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195868 kb
Host smart-7a5ce51a-29f6-4b23-8c34-1fdb9aaef43a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212955692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2212955692
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.3704464394
Short name T364
Test name
Test status
Simulation time 87145049 ps
CPU time 3.59 seconds
Started Jun 23 05:29:04 PM PDT 24
Finished Jun 23 05:29:09 PM PDT 24
Peak memory 198096 kb
Host smart-119693f4-ac02-49d6-981c-f5a03b41c27a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704464394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.3704464394
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.439289216
Short name T534
Test name
Test status
Simulation time 401610916 ps
CPU time 3.29 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 196740 kb
Host smart-50bdfbe4-8622-4449-bf34-e82aa4518ef5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439289216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger.
439289216
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.722632741
Short name T703
Test name
Test status
Simulation time 44856593 ps
CPU time 0.97 seconds
Started Jun 23 05:29:09 PM PDT 24
Finished Jun 23 05:29:10 PM PDT 24
Peak memory 196836 kb
Host smart-b20c57aa-c4c2-4bb9-8bc6-3e5a0a0eec3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722632741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.722632741
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3289314333
Short name T217
Test name
Test status
Simulation time 27211746 ps
CPU time 0.75 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 195380 kb
Host smart-7868a18f-b928-4235-9713-ecac68f421a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289314333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3289314333
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.982732642
Short name T3
Test name
Test status
Simulation time 512403852 ps
CPU time 1.68 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:03 PM PDT 24
Peak memory 197992 kb
Host smart-35ae5c34-10d8-46cd-967d-8288d3f7dcbe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982732642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ran
dom_long_reg_writes_reg_reads.982732642
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.532756022
Short name T424
Test name
Test status
Simulation time 194642655 ps
CPU time 1.05 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 195640 kb
Host smart-6322a9f7-d7be-4a5e-ad15-2de27bd685ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532756022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.532756022
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.302886687
Short name T374
Test name
Test status
Simulation time 176902433 ps
CPU time 1.32 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:12 PM PDT 24
Peak memory 195568 kb
Host smart-44d66e2f-dd03-4492-8e98-225478f34d24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302886687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.302886687
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1412969784
Short name T372
Test name
Test status
Simulation time 5310265548 ps
CPU time 138.27 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:31:30 PM PDT 24
Peak memory 198160 kb
Host smart-b42629cf-c6d9-4ca5-9dd8-65d0f6e8a12c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412969784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1412969784
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1571054829
Short name T246
Test name
Test status
Simulation time 41684432 ps
CPU time 0.6 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:10 PM PDT 24
Peak memory 194740 kb
Host smart-21297b75-8592-48a0-85b7-065afaf11c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571054829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1571054829
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.113783050
Short name T402
Test name
Test status
Simulation time 35183340 ps
CPU time 0.81 seconds
Started Jun 23 05:28:21 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 195360 kb
Host smart-5f5f7460-b4f1-400c-be5a-acc770eeab7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113783050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.113783050
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.217364451
Short name T134
Test name
Test status
Simulation time 821560974 ps
CPU time 10.39 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 197044 kb
Host smart-5f08673c-0f39-4dd6-87be-daf0212d162d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217364451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stress
.217364451
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3887885308
Short name T498
Test name
Test status
Simulation time 94628630 ps
CPU time 1.17 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:11 PM PDT 24
Peak memory 198076 kb
Host smart-2e388bcc-8a78-46d2-8009-df06f44bff73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887885308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3887885308
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2803697305
Short name T274
Test name
Test status
Simulation time 47591563 ps
CPU time 1.43 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:11 PM PDT 24
Peak memory 196584 kb
Host smart-ccce0c36-14a6-43c5-a040-8e1f1ab92c03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803697305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2803697305
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.4266057106
Short name T276
Test name
Test status
Simulation time 48910801 ps
CPU time 1.5 seconds
Started Jun 23 05:28:10 PM PDT 24
Finished Jun 23 05:28:12 PM PDT 24
Peak memory 196364 kb
Host smart-454d9361-c81d-40f3-a9f0-6f703cbf924b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266057106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.4266057106
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2968132688
Short name T599
Test name
Test status
Simulation time 630205776 ps
CPU time 3.6 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:13 PM PDT 24
Peak memory 196528 kb
Host smart-9ec40ba2-38cc-498e-b020-7c3573c469a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968132688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2968132688
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1586310039
Short name T348
Test name
Test status
Simulation time 60910077 ps
CPU time 1.33 seconds
Started Jun 23 05:28:07 PM PDT 24
Finished Jun 23 05:28:09 PM PDT 24
Peak memory 196980 kb
Host smart-17bcf80e-4be3-4d5d-bdc0-2b0160f3d031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586310039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1586310039
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.3876094924
Short name T415
Test name
Test status
Simulation time 28043977 ps
CPU time 0.97 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 196096 kb
Host smart-ca55d80d-1d57-45a1-89dc-fec55e4eafd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876094924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.3876094924
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2928796690
Short name T7
Test name
Test status
Simulation time 822206163 ps
CPU time 3.82 seconds
Started Jun 23 05:28:13 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 197980 kb
Host smart-f406b118-f6a4-41e3-a311-8d53f4e0aea6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928796690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2928796690
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.146561639
Short name T46
Test name
Test status
Simulation time 364157376 ps
CPU time 0.97 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 214796 kb
Host smart-ab804e54-ccfa-49c2-871b-c99a8ac93192
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146561639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.146561639
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.1016470875
Short name T219
Test name
Test status
Simulation time 125310693 ps
CPU time 0.98 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:17 PM PDT 24
Peak memory 195544 kb
Host smart-abef16d4-d0c1-4530-ab6e-00cd75482505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016470875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.1016470875
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1400208379
Short name T427
Test name
Test status
Simulation time 45223885 ps
CPU time 1.17 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:11 PM PDT 24
Peak memory 195720 kb
Host smart-2809c732-2162-4d8b-b290-f682f7218266
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400208379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1400208379
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2153923534
Short name T450
Test name
Test status
Simulation time 42773484798 ps
CPU time 135.03 seconds
Started Jun 23 05:28:10 PM PDT 24
Finished Jun 23 05:30:26 PM PDT 24
Peak memory 197992 kb
Host smart-adbd61ae-273f-4645-b3f2-ddc27da25687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153923534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2153923534
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3767647681
Short name T543
Test name
Test status
Simulation time 32551741 ps
CPU time 0.56 seconds
Started Jun 23 05:29:07 PM PDT 24
Finished Jun 23 05:29:08 PM PDT 24
Peak memory 194532 kb
Host smart-c2861838-59d9-4457-ba4d-2fc4f3e968c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767647681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3767647681
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.3772048189
Short name T714
Test name
Test status
Simulation time 55549835 ps
CPU time 0.67 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 193860 kb
Host smart-ade464a2-bcea-421f-a492-e15209df03fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772048189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.3772048189
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.528413872
Short name T23
Test name
Test status
Simulation time 1596616746 ps
CPU time 12.51 seconds
Started Jun 23 05:29:07 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 196308 kb
Host smart-dc98345e-a763-4f10-94cc-1fa426b90019
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528413872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.528413872
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2726870958
Short name T532
Test name
Test status
Simulation time 604069180 ps
CPU time 0.98 seconds
Started Jun 23 05:29:05 PM PDT 24
Finished Jun 23 05:29:06 PM PDT 24
Peak memory 196688 kb
Host smart-59581344-d431-4da3-aab8-ed7c1b7afc14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726870958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2726870958
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3965426147
Short name T513
Test name
Test status
Simulation time 24056009 ps
CPU time 0.94 seconds
Started Jun 23 05:29:03 PM PDT 24
Finished Jun 23 05:29:04 PM PDT 24
Peak memory 196556 kb
Host smart-0adef567-293c-4aef-992f-9b73cb538cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965426147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3965426147
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4219210599
Short name T155
Test name
Test status
Simulation time 65766997 ps
CPU time 2.52 seconds
Started Jun 23 05:29:09 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 198176 kb
Host smart-2dd1f89b-48d3-40a9-bb1f-4c1eee43a574
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219210599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4219210599
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3362556884
Short name T479
Test name
Test status
Simulation time 196984653 ps
CPU time 2.73 seconds
Started Jun 23 05:29:04 PM PDT 24
Finished Jun 23 05:29:08 PM PDT 24
Peak memory 196964 kb
Host smart-03ba81b2-4433-40f7-9fcd-c21f22d5060a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362556884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3362556884
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.310838832
Short name T96
Test name
Test status
Simulation time 80351921 ps
CPU time 1.29 seconds
Started Jun 23 05:29:01 PM PDT 24
Finished Jun 23 05:29:03 PM PDT 24
Peak memory 197144 kb
Host smart-f3313386-c928-4785-bee0-ac85674fe0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310838832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.310838832
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3422115175
Short name T169
Test name
Test status
Simulation time 154402891 ps
CPU time 0.97 seconds
Started Jun 23 05:29:02 PM PDT 24
Finished Jun 23 05:29:03 PM PDT 24
Peak memory 196004 kb
Host smart-c410f3e0-4048-4256-b425-838ef74b827a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422115175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3422115175
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.232541738
Short name T598
Test name
Test status
Simulation time 39603288 ps
CPU time 1.92 seconds
Started Jun 23 05:29:02 PM PDT 24
Finished Jun 23 05:29:04 PM PDT 24
Peak memory 198056 kb
Host smart-49b089bc-d609-40e9-823c-416c34d741ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232541738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ran
dom_long_reg_writes_reg_reads.232541738
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.492865162
Short name T627
Test name
Test status
Simulation time 139306103 ps
CPU time 1.12 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 195884 kb
Host smart-da629f84-3617-4095-bd0e-b1adf5705261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492865162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.492865162
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3336619283
Short name T131
Test name
Test status
Simulation time 108170441 ps
CPU time 1.08 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 196340 kb
Host smart-2dc1477c-8655-49e3-94ab-5e5341ff00d4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336619283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3336619283
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.219814836
Short name T8
Test name
Test status
Simulation time 228663935148 ps
CPU time 366.55 seconds
Started Jun 23 05:29:09 PM PDT 24
Finished Jun 23 05:35:16 PM PDT 24
Peak memory 198180 kb
Host smart-b6404f22-ff9b-4b0b-bfb8-ec7122a8fb0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=219814836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.219814836
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.501403693
Short name T655
Test name
Test status
Simulation time 13998199 ps
CPU time 0.56 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 193844 kb
Host smart-cfb00dfd-a2ba-46c8-b511-6f55d59db70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501403693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.501403693
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3930291960
Short name T150
Test name
Test status
Simulation time 38102145 ps
CPU time 0.68 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:01 PM PDT 24
Peak memory 194800 kb
Host smart-641102dd-9531-4e35-b9b8-f6900f65995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930291960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3930291960
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3759526153
Short name T58
Test name
Test status
Simulation time 1416559986 ps
CPU time 13.16 seconds
Started Jun 23 05:29:08 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196320 kb
Host smart-05014b9f-3123-4e76-8c49-72a39f7b7bc0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759526153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3759526153
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.4140780082
Short name T247
Test name
Test status
Simulation time 233822152 ps
CPU time 0.84 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 196648 kb
Host smart-d49e6444-d1a0-4fd1-80e6-20bd86c680a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140780082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.4140780082
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2420706309
Short name T297
Test name
Test status
Simulation time 34540226 ps
CPU time 0.87 seconds
Started Jun 23 05:29:03 PM PDT 24
Finished Jun 23 05:29:04 PM PDT 24
Peak memory 196096 kb
Host smart-e23bf38a-5dce-4e94-996b-8c6dc11746eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420706309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2420706309
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2802633562
Short name T696
Test name
Test status
Simulation time 50777840 ps
CPU time 1.91 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:15 PM PDT 24
Peak memory 196540 kb
Host smart-e1156bb7-64d7-45d5-9b13-6636b19f68fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802633562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2802633562
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.293083905
Short name T676
Test name
Test status
Simulation time 34600317 ps
CPU time 1.15 seconds
Started Jun 23 05:28:58 PM PDT 24
Finished Jun 23 05:29:00 PM PDT 24
Peak memory 196500 kb
Host smart-bdfef0b1-0793-4c9e-885d-f13647c4745b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293083905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
293083905
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.2819877364
Short name T311
Test name
Test status
Simulation time 28676269 ps
CPU time 0.84 seconds
Started Jun 23 05:29:07 PM PDT 24
Finished Jun 23 05:29:09 PM PDT 24
Peak memory 196632 kb
Host smart-2a201223-1443-4179-a2f9-39ca3e7f831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819877364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.2819877364
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3791220099
Short name T473
Test name
Test status
Simulation time 66670727 ps
CPU time 1.13 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:11 PM PDT 24
Peak memory 196704 kb
Host smart-3ea4e197-eae4-454f-9e9f-793db54d0cdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791220099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3791220099
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1942112903
Short name T214
Test name
Test status
Simulation time 230563784 ps
CPU time 1.34 seconds
Started Jun 23 05:29:10 PM PDT 24
Finished Jun 23 05:29:12 PM PDT 24
Peak memory 197816 kb
Host smart-9b5a2110-8466-43b6-8e30-d9764cebf3ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942112903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1942112903
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3934302416
Short name T536
Test name
Test status
Simulation time 54400182 ps
CPU time 1.06 seconds
Started Jun 23 05:29:08 PM PDT 24
Finished Jun 23 05:29:09 PM PDT 24
Peak memory 195716 kb
Host smart-9908144e-9794-475c-89b0-f8fd107f07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934302416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3934302416
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2736874866
Short name T600
Test name
Test status
Simulation time 53546541 ps
CPU time 0.99 seconds
Started Jun 23 05:29:00 PM PDT 24
Finished Jun 23 05:29:02 PM PDT 24
Peak memory 197088 kb
Host smart-faac2888-0dea-420f-9ca7-9a6972e20f52
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736874866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2736874866
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.1570497651
Short name T434
Test name
Test status
Simulation time 21070047259 ps
CPU time 77.62 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:30:37 PM PDT 24
Peak memory 198208 kb
Host smart-6c48c805-15eb-4667-9712-829e334a38a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570497651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.1570497651
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1785742386
Short name T243
Test name
Test status
Simulation time 25495470 ps
CPU time 0.58 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 193804 kb
Host smart-f1323ac8-ecc8-40b1-a1d9-3ec39fc8cd7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785742386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1785742386
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1064522629
Short name T454
Test name
Test status
Simulation time 41051982 ps
CPU time 0.76 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 195164 kb
Host smart-fd98f864-9464-4454-b4d4-bf928dd03066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064522629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1064522629
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3588606501
Short name T239
Test name
Test status
Simulation time 195132401 ps
CPU time 6.96 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 196860 kb
Host smart-543a63b6-0232-4167-95b1-d90a0825caaa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588606501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3588606501
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.230876081
Short name T579
Test name
Test status
Simulation time 145724508 ps
CPU time 0.74 seconds
Started Jun 23 05:29:24 PM PDT 24
Finished Jun 23 05:29:25 PM PDT 24
Peak memory 195800 kb
Host smart-9d6b9a16-5abe-42ae-841a-4e2552fceb6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230876081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.230876081
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.1303320565
Short name T61
Test name
Test status
Simulation time 127504240 ps
CPU time 0.77 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195444 kb
Host smart-dde53b51-c609-41b6-ae42-459f96eebdcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303320565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.1303320565
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.244738307
Short name T701
Test name
Test status
Simulation time 159833082 ps
CPU time 3.17 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 198052 kb
Host smart-08175d7f-5aac-4d64-b667-ffb50f445508
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244738307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.244738307
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1419359765
Short name T660
Test name
Test status
Simulation time 1886771572 ps
CPU time 2.79 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 197236 kb
Host smart-22e03fa5-ea40-40b2-bd96-7b9db398f10d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419359765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1419359765
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.446805982
Short name T469
Test name
Test status
Simulation time 121126679 ps
CPU time 0.85 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 195472 kb
Host smart-ad6adbb4-be62-4101-9041-f12f1514b51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446805982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.446805982
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.31459302
Short name T146
Test name
Test status
Simulation time 38274896 ps
CPU time 1.25 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 197016 kb
Host smart-3c11ad11-92e1-4554-a644-6b59fd8c9487
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31459302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup_
pulldown.31459302
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1847352563
Short name T125
Test name
Test status
Simulation time 442506786 ps
CPU time 5.76 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 198008 kb
Host smart-267ad08a-dde3-44d7-a6ff-b89f7220ee32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847352563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1847352563
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2552358686
Short name T205
Test name
Test status
Simulation time 212359775 ps
CPU time 0.94 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 195724 kb
Host smart-3f19b1e9-cfac-4c4c-9a4d-09124b06447c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552358686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2552358686
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.840548128
Short name T115
Test name
Test status
Simulation time 25861049 ps
CPU time 0.89 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 196420 kb
Host smart-ab852740-fe2c-495f-b72a-0f3e5d540b32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840548128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.840548128
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4101970444
Short name T148
Test name
Test status
Simulation time 10963972591 ps
CPU time 151.19 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:31:44 PM PDT 24
Peak memory 198168 kb
Host smart-5b884df1-e266-411a-bdbf-93abefd0ad64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101970444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4101970444
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1857433104
Short name T379
Test name
Test status
Simulation time 193840413273 ps
CPU time 1146.91 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:48:21 PM PDT 24
Peak memory 198160 kb
Host smart-a2f0373b-8710-4135-aaa9-dbd4a2d380c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1857433104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1857433104
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3551618683
Short name T248
Test name
Test status
Simulation time 13195869 ps
CPU time 0.57 seconds
Started Jun 23 05:29:37 PM PDT 24
Finished Jun 23 05:29:37 PM PDT 24
Peak memory 193840 kb
Host smart-8d873119-6507-4828-a8df-c93896c9e13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551618683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3551618683
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2647436817
Short name T507
Test name
Test status
Simulation time 19382064 ps
CPU time 0.63 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 194044 kb
Host smart-319f2e7a-ab7f-4748-8756-e09fce43a618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647436817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2647436817
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3589619214
Short name T548
Test name
Test status
Simulation time 1168837406 ps
CPU time 15.31 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 197220 kb
Host smart-24a41516-5e36-4074-b9e7-efec5b896894
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589619214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3589619214
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2502571670
Short name T401
Test name
Test status
Simulation time 88636970 ps
CPU time 1.08 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 197732 kb
Host smart-d097c377-f3c4-422f-8522-44419a20bc7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502571670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2502571670
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.981286987
Short name T503
Test name
Test status
Simulation time 55399456 ps
CPU time 0.96 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 195992 kb
Host smart-cc0da4f3-01e0-4812-95cd-7eb87d0ecb57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981286987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.981286987
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.2236650231
Short name T611
Test name
Test status
Simulation time 234009816 ps
CPU time 2.65 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 198172 kb
Host smart-f995cad0-641b-456b-9b9f-28b9c7090320
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236650231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.2236650231
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2665567601
Short name T237
Test name
Test status
Simulation time 543503174 ps
CPU time 3.03 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 197360 kb
Host smart-1fd6dd64-62be-4cd6-835e-3a67467eaf11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665567601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.2665567601
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.2343490393
Short name T516
Test name
Test status
Simulation time 31077134 ps
CPU time 0.95 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 196188 kb
Host smart-841e9a8e-4068-4a9e-a1ad-9223cc7cc74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343490393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.2343490393
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.4243083544
Short name T60
Test name
Test status
Simulation time 28122305 ps
CPU time 1.13 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 196144 kb
Host smart-77a7ee0c-776e-49d4-a8e8-852ca909dcb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243083544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.4243083544
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.233599384
Short name T445
Test name
Test status
Simulation time 544949219 ps
CPU time 6.61 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 198024 kb
Host smart-58956c11-f266-4156-ab97-f6abfec20119
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233599384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.233599384
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.999233914
Short name T656
Test name
Test status
Simulation time 187459645 ps
CPU time 1.09 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 195876 kb
Host smart-53c1ba36-35bd-432a-bfc5-725877e1cec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999233914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.999233914
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.112402727
Short name T116
Test name
Test status
Simulation time 71826682 ps
CPU time 1.3 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 196892 kb
Host smart-4248ec49-50f6-4a11-8737-76bfe677b086
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112402727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.112402727
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4155056762
Short name T396
Test name
Test status
Simulation time 51733903776 ps
CPU time 136.72 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:31:38 PM PDT 24
Peak memory 198148 kb
Host smart-67752296-89b2-4a78-8325-ad8b97da028a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155056762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4155056762
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.1252617269
Short name T295
Test name
Test status
Simulation time 59057297681 ps
CPU time 688.77 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:40:52 PM PDT 24
Peak memory 198200 kb
Host smart-b0ca7587-f985-46b0-8954-a51460bb53d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1252617269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.1252617269
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.567749430
Short name T409
Test name
Test status
Simulation time 16756936 ps
CPU time 0.56 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 194804 kb
Host smart-93cf50eb-d669-4d3a-b6e5-cd7fd668f0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567749430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.567749430
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2734327018
Short name T573
Test name
Test status
Simulation time 20181856 ps
CPU time 0.81 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 194084 kb
Host smart-1a7003fb-9b41-43d4-82c6-7e6007b78943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734327018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2734327018
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1962073580
Short name T564
Test name
Test status
Simulation time 410624789 ps
CPU time 21.54 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:36 PM PDT 24
Peak memory 196328 kb
Host smart-29553972-fe77-4b0d-bef7-1d9c81eab65d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962073580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1962073580
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.405603337
Short name T520
Test name
Test status
Simulation time 201955841 ps
CPU time 0.95 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196636 kb
Host smart-280b9453-01e8-4b33-8479-f87dff940c28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405603337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.405603337
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.195607541
Short name T381
Test name
Test status
Simulation time 142915566 ps
CPU time 0.84 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 195548 kb
Host smart-bdbc9ae9-22c6-4860-abfd-5b1b06ed330d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195607541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.195607541
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1829750292
Short name T483
Test name
Test status
Simulation time 29657924 ps
CPU time 1.05 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 196084 kb
Host smart-61120209-a2db-4d4d-9db9-e135e8fe66a5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829750292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1829750292
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1447933904
Short name T328
Test name
Test status
Simulation time 264962672 ps
CPU time 2.19 seconds
Started Jun 23 05:29:21 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 196556 kb
Host smart-afee7ec6-8933-4b60-91bb-dac498c74485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447933904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1447933904
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.301953770
Short name T672
Test name
Test status
Simulation time 530227055 ps
CPU time 1.11 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 196616 kb
Host smart-41b5bdb6-b0da-47dd-94c6-b7771c18f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301953770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.301953770
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.983384042
Short name T430
Test name
Test status
Simulation time 20873467 ps
CPU time 0.82 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195852 kb
Host smart-206c88be-e517-4ad6-8ea0-4d7ceddc2328
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983384042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.983384042
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3486321602
Short name T403
Test name
Test status
Simulation time 3370731835 ps
CPU time 3.28 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 198120 kb
Host smart-dc125070-e6dc-470d-9620-7a6e97ac8788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486321602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3486321602
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3238437036
Short name T117
Test name
Test status
Simulation time 185638326 ps
CPU time 1.44 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 196296 kb
Host smart-d297ca6c-aef5-4fbf-837e-d0fc01e223e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238437036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3238437036
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2260229482
Short name T624
Test name
Test status
Simulation time 224503455 ps
CPU time 1.32 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 196684 kb
Host smart-f6e51e13-0b7a-43ed-9497-491050420afc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260229482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2260229482
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.726926619
Short name T158
Test name
Test status
Simulation time 2809184577 ps
CPU time 33.15 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:52 PM PDT 24
Peak memory 198156 kb
Host smart-fdaf4208-a294-48b6-b837-d0fa6d1849e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726926619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.726926619
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3463713042
Short name T317
Test name
Test status
Simulation time 43024813 ps
CPU time 0.58 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 194772 kb
Host smart-2d2c54d4-e0f1-4e21-9cec-a8f64c9e8da8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463713042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3463713042
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.1398116704
Short name T199
Test name
Test status
Simulation time 65155849 ps
CPU time 0.76 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195908 kb
Host smart-df352ef8-e9b6-4199-89ea-90c2c2179091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398116704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.1398116704
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2310828247
Short name T705
Test name
Test status
Simulation time 2627219156 ps
CPU time 10.7 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:29:30 PM PDT 24
Peak memory 197492 kb
Host smart-d00aba9f-d025-4df2-bd57-99aa101766b4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310828247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2310828247
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2883480885
Short name T680
Test name
Test status
Simulation time 22997632 ps
CPU time 0.62 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 194320 kb
Host smart-09185a27-9d87-4bb0-bfe1-bf3baac4db50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883480885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2883480885
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3876511564
Short name T190
Test name
Test status
Simulation time 122262289 ps
CPU time 1.39 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 197068 kb
Host smart-d5298331-173f-46da-a68a-bc4e9ab1a1e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876511564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3876511564
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1658460223
Short name T455
Test name
Test status
Simulation time 37639657 ps
CPU time 0.98 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 196216 kb
Host smart-375c4b7a-a9b6-437f-a6bd-6049eac3d685
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658460223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1658460223
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1367720625
Short name T678
Test name
Test status
Simulation time 262239667 ps
CPU time 3.49 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 197392 kb
Host smart-977fadf5-2eaa-4178-a964-4b03ccd2f414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367720625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1367720625
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.300581144
Short name T207
Test name
Test status
Simulation time 21247307 ps
CPU time 0.83 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 196616 kb
Host smart-124a7c7e-a32a-44bb-bba7-21f92b5486c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300581144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.300581144
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3530099856
Short name T682
Test name
Test status
Simulation time 25655347 ps
CPU time 0.74 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 195460 kb
Host smart-7dce6d20-77dd-49cc-a35e-be95b4328366
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530099856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3530099856
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.619980472
Short name T355
Test name
Test status
Simulation time 156657331 ps
CPU time 2.78 seconds
Started Jun 23 05:29:11 PM PDT 24
Finished Jun 23 05:29:15 PM PDT 24
Peak memory 197892 kb
Host smart-a42b10e7-ccfa-492c-8209-399a2c216e91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619980472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.619980472
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3135246157
Short name T616
Test name
Test status
Simulation time 148591529 ps
CPU time 1.41 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 195776 kb
Host smart-27c38751-02a6-415b-b08b-eeadc86999fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135246157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3135246157
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1876947359
Short name T697
Test name
Test status
Simulation time 56426498 ps
CPU time 1.23 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195856 kb
Host smart-ddbebea3-d555-469e-96ac-0fe9185633cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876947359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1876947359
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.915450711
Short name T206
Test name
Test status
Simulation time 11945420393 ps
CPU time 156.75 seconds
Started Jun 23 05:29:21 PM PDT 24
Finished Jun 23 05:31:59 PM PDT 24
Peak memory 198164 kb
Host smart-4c98e4f1-6e74-4686-8d70-8fef6d4fd08d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915450711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.915450711
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.909007201
Short name T572
Test name
Test status
Simulation time 419745934047 ps
CPU time 780.65 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:42:18 PM PDT 24
Peak memory 198220 kb
Host smart-d1cdedd2-16e5-4285-8978-d1ee98c4166f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=909007201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.909007201
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1621684710
Short name T147
Test name
Test status
Simulation time 10620341 ps
CPU time 0.61 seconds
Started Jun 23 05:29:12 PM PDT 24
Finished Jun 23 05:29:14 PM PDT 24
Peak memory 193868 kb
Host smart-1d39d4c8-20ee-4192-a74c-9d2b364d896c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621684710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1621684710
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3123288929
Short name T522
Test name
Test status
Simulation time 74887292 ps
CPU time 0.75 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:15 PM PDT 24
Peak memory 195896 kb
Host smart-c129de74-a791-4dbf-a6a6-f2161f7d59bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123288929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3123288929
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2443920396
Short name T440
Test name
Test status
Simulation time 2942622399 ps
CPU time 20.43 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:43 PM PDT 24
Peak memory 197516 kb
Host smart-751ba4c1-ad8e-4e1e-a2db-74a7c41b1a98
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443920396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2443920396
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3565562894
Short name T278
Test name
Test status
Simulation time 149812948 ps
CPU time 0.77 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 195668 kb
Host smart-a55896b9-26d0-4f4a-88d1-cd8310a671d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565562894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3565562894
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3014583261
Short name T468
Test name
Test status
Simulation time 84434431 ps
CPU time 1.41 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196616 kb
Host smart-8e52cf6c-4e11-4942-bb32-cfc00555ea0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014583261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3014583261
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.3411481321
Short name T582
Test name
Test status
Simulation time 122617384 ps
CPU time 2.71 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:21 PM PDT 24
Peak memory 198172 kb
Host smart-d53a4966-bce0-462d-af7f-e66e4f322d3f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411481321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.3411481321
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2404117511
Short name T184
Test name
Test status
Simulation time 474127252 ps
CPU time 3.37 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196860 kb
Host smart-6e580212-3316-4878-a1d4-1a4e62149c39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404117511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2404117511
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.4224487980
Short name T594
Test name
Test status
Simulation time 49681619 ps
CPU time 1.08 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 196668 kb
Host smart-17953664-5452-44a6-877f-c889a53a335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224487980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.4224487980
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.22100931
Short name T173
Test name
Test status
Simulation time 29792465 ps
CPU time 1.13 seconds
Started Jun 23 05:29:24 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 196536 kb
Host smart-cfe981c5-3cfc-46f0-a4cb-29320e0bd177
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22100931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup_
pulldown.22100931
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3513209264
Short name T352
Test name
Test status
Simulation time 91681248 ps
CPU time 1.4 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 197940 kb
Host smart-54407cd7-634f-48af-b372-4c399873a43d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513209264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3513209264
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.406764225
Short name T232
Test name
Test status
Simulation time 99086417 ps
CPU time 0.88 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 196972 kb
Host smart-b394fd89-6dcf-4e87-85a1-55866a50d91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406764225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.406764225
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.257079636
Short name T691
Test name
Test status
Simulation time 43099491 ps
CPU time 1.19 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 195860 kb
Host smart-eb792766-462c-4485-884e-0630c82398e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257079636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.257079636
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.114134462
Short name T642
Test name
Test status
Simulation time 73808714881 ps
CPU time 238.09 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:33:16 PM PDT 24
Peak memory 198112 kb
Host smart-09aee2e5-b6e9-496b-8f05-2d2d59bf31c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114134462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.114134462
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.30179955
Short name T650
Test name
Test status
Simulation time 31683809 ps
CPU time 0.55 seconds
Started Jun 23 05:29:13 PM PDT 24
Finished Jun 23 05:29:15 PM PDT 24
Peak memory 193856 kb
Host smart-ec1ceedd-2caf-4f79-9234-28e50b35741d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30179955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.30179955
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.47671720
Short name T229
Test name
Test status
Simulation time 254013691 ps
CPU time 0.77 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 196080 kb
Host smart-e707a7f0-e162-4372-9eb8-6eccd098be25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47671720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.47671720
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2541166121
Short name T566
Test name
Test status
Simulation time 602416939 ps
CPU time 5.44 seconds
Started Jun 23 05:29:21 PM PDT 24
Finished Jun 23 05:29:27 PM PDT 24
Peak memory 196808 kb
Host smart-75ead461-997a-463b-83ec-552aa13d7906
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541166121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2541166121
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3222276226
Short name T192
Test name
Test status
Simulation time 115473958 ps
CPU time 0.65 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195208 kb
Host smart-386dd190-5cee-4869-bb31-e3d69ad07fc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222276226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3222276226
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.3810671831
Short name T493
Test name
Test status
Simulation time 205092794 ps
CPU time 1.42 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 197220 kb
Host smart-a5a06f29-ef09-423e-87cf-ca45c47d7831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810671831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.3810671831
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4005956547
Short name T290
Test name
Test status
Simulation time 108975830 ps
CPU time 1.29 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 198116 kb
Host smart-ac9665a9-5c4b-4ca6-9864-a26bc43545dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005956547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4005956547
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1699797671
Short name T119
Test name
Test status
Simulation time 50628142 ps
CPU time 0.9 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:16 PM PDT 24
Peak memory 194308 kb
Host smart-60c168df-19b4-46fd-8332-7d7248f77efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699797671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1699797671
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.857730524
Short name T495
Test name
Test status
Simulation time 57607584 ps
CPU time 1.12 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195908 kb
Host smart-cd493c28-f731-413d-82ce-82cb90ed05ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857730524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.857730524
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.4288316434
Short name T341
Test name
Test status
Simulation time 49350762 ps
CPU time 1.14 seconds
Started Jun 23 05:29:14 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 195964 kb
Host smart-6a3c098f-3ffd-4910-8b95-1533c131db25
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288316434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.4288316434
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1718093148
Short name T669
Test name
Test status
Simulation time 107875238 ps
CPU time 1.89 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 197820 kb
Host smart-ee5cd053-e2b5-4c06-9429-38c78c6c4e9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718093148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1718093148
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2028827682
Short name T143
Test name
Test status
Simulation time 138008939 ps
CPU time 1.07 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195584 kb
Host smart-295a8422-3656-47c4-ba69-b55166a53da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028827682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2028827682
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2715548287
Short name T533
Test name
Test status
Simulation time 117605152 ps
CPU time 1.07 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 195552 kb
Host smart-a5df30fd-3f4b-40cb-a599-3f30c345c0fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715548287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2715548287
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3699774096
Short name T215
Test name
Test status
Simulation time 26091936295 ps
CPU time 210.97 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:32:51 PM PDT 24
Peak memory 198132 kb
Host smart-a3e9aea0-ea6b-4f9e-b108-99bf64144ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699774096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3699774096
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3874984635
Short name T32
Test name
Test status
Simulation time 216870294263 ps
CPU time 1638.24 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:56:42 PM PDT 24
Peak memory 198136 kb
Host smart-c7fc70ab-5739-49bd-be1f-fbaedda00c01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3874984635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3874984635
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.796624481
Short name T368
Test name
Test status
Simulation time 34205981 ps
CPU time 0.59 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 194752 kb
Host smart-7949398d-6984-4fcf-b04c-28a313de03ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796624481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.796624481
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1265924459
Short name T711
Test name
Test status
Simulation time 173281858 ps
CPU time 0.85 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 195808 kb
Host smart-57596246-1402-4a3c-b3a0-b634e2984765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265924459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1265924459
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3831454717
Short name T699
Test name
Test status
Simulation time 1290295991 ps
CPU time 5.83 seconds
Started Jun 23 05:29:17 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 198004 kb
Host smart-590c00d5-8aca-4a54-887a-28e83db9421f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831454717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3831454717
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3018551922
Short name T384
Test name
Test status
Simulation time 46636428 ps
CPU time 0.73 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 195760 kb
Host smart-eb6a6de6-cea5-4966-a756-b75d145f9f85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018551922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3018551922
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1510548397
Short name T289
Test name
Test status
Simulation time 82724855 ps
CPU time 1.2 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196008 kb
Host smart-bc10da8e-97f3-4720-b881-7f9a1f50c64e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510548397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1510548397
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.446088844
Short name T320
Test name
Test status
Simulation time 155776344 ps
CPU time 2.97 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:21 PM PDT 24
Peak memory 197956 kb
Host smart-4c3d8e35-2f7c-4b62-9c3d-24263e840a00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446088844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.446088844
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2299191472
Short name T50
Test name
Test status
Simulation time 145289123 ps
CPU time 3.11 seconds
Started Jun 23 05:29:29 PM PDT 24
Finished Jun 23 05:29:33 PM PDT 24
Peak memory 195928 kb
Host smart-b912a491-1a93-4194-8f3e-2bd50deaf068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299191472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2299191472
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.675084626
Short name T585
Test name
Test status
Simulation time 47629326 ps
CPU time 1.08 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:18 PM PDT 24
Peak memory 196040 kb
Host smart-f42c03e2-7c20-4b3b-affc-9cdb35d10e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675084626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.675084626
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2142059697
Short name T330
Test name
Test status
Simulation time 43736790 ps
CPU time 0.7 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:29:17 PM PDT 24
Peak memory 194364 kb
Host smart-21dfb6a4-df02-41ea-a7d7-fb9d055d2e2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142059697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2142059697
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1800044653
Short name T208
Test name
Test status
Simulation time 93852409 ps
CPU time 4.25 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 198048 kb
Host smart-8b1a7f80-49bf-4062-8402-3aee2f4fc3e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800044653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1800044653
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.3663737302
Short name T681
Test name
Test status
Simulation time 42870068 ps
CPU time 1.17 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 195796 kb
Host smart-287f1f12-5ccb-4fc4-9b7b-cf7ec854d47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663737302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.3663737302
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2028478646
Short name T647
Test name
Test status
Simulation time 218635692 ps
CPU time 1.07 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 195744 kb
Host smart-05cefe56-679c-4855-a2c8-2c979a38916e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028478646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2028478646
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1306464018
Short name T9
Test name
Test status
Simulation time 28053810931 ps
CPU time 153.78 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:31:53 PM PDT 24
Peak memory 198208 kb
Host smart-cf5c93f5-4dc4-4482-8146-a35cc5283e1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306464018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1306464018
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1308676570
Short name T31
Test name
Test status
Simulation time 139732589170 ps
CPU time 1338.57 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:51:47 PM PDT 24
Peak memory 198264 kb
Host smart-c1517539-a34c-48b2-aba2-691add9e0e3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1308676570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1308676570
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2389084295
Short name T492
Test name
Test status
Simulation time 36476727 ps
CPU time 0.58 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 194512 kb
Host smart-362c5c52-0fde-43ba-b5a0-17d38b282cd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389084295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2389084295
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.3559325983
Short name T603
Test name
Test status
Simulation time 53509821 ps
CPU time 0.65 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 194040 kb
Host smart-426a3b6b-9b7c-4e76-b869-02889e3f3a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559325983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.3559325983
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3220461242
Short name T309
Test name
Test status
Simulation time 71427722 ps
CPU time 3.77 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:25 PM PDT 24
Peak memory 196720 kb
Host smart-35c6b9fc-1969-45d2-860f-3b3d7364404b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220461242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3220461242
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.4013113562
Short name T22
Test name
Test status
Simulation time 140324016 ps
CPU time 0.83 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 195884 kb
Host smart-b554eb9d-f4b8-4655-86b6-2f7ce2aacec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013113562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.4013113562
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2208998944
Short name T486
Test name
Test status
Simulation time 71391735 ps
CPU time 1.29 seconds
Started Jun 23 05:29:21 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 196492 kb
Host smart-f854e720-749d-48a4-ba91-6f38b053e894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208998944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2208998944
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2955382123
Short name T375
Test name
Test status
Simulation time 346299890 ps
CPU time 3.52 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:25 PM PDT 24
Peak memory 198064 kb
Host smart-67537e07-252d-4e37-88f8-20f5beb70cba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955382123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2955382123
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3061233710
Short name T321
Test name
Test status
Simulation time 45536894 ps
CPU time 0.99 seconds
Started Jun 23 05:29:29 PM PDT 24
Finished Jun 23 05:29:31 PM PDT 24
Peak memory 195376 kb
Host smart-80101b75-c934-4bab-9b8f-150174baccb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061233710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3061233710
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.4077089998
Short name T340
Test name
Test status
Simulation time 82260074 ps
CPU time 0.98 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:29:21 PM PDT 24
Peak memory 196052 kb
Host smart-181f5689-c32f-47cb-847d-53e1b1552061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077089998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.4077089998
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2227836840
Short name T176
Test name
Test status
Simulation time 122239853 ps
CPU time 1.25 seconds
Started Jun 23 05:29:28 PM PDT 24
Finished Jun 23 05:29:30 PM PDT 24
Peak memory 197076 kb
Host smart-46706aa3-31eb-4b3d-8fb2-d8856e159cf4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227836840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2227836840
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1883743703
Short name T558
Test name
Test status
Simulation time 439590564 ps
CPU time 5.05 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 198040 kb
Host smart-d2519cf6-3a58-4d5b-b2e9-b9d3bccef8e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883743703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1883743703
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2815945551
Short name T501
Test name
Test status
Simulation time 96932554 ps
CPU time 1.01 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 195756 kb
Host smart-8e6c2ea7-9a9f-4171-9f32-1a8b32684af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815945551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2815945551
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1264821209
Short name T373
Test name
Test status
Simulation time 404663614 ps
CPU time 1.18 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196428 kb
Host smart-bf656118-2006-41b8-8136-b58145043852
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264821209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1264821209
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1464939960
Short name T497
Test name
Test status
Simulation time 16317493748 ps
CPU time 108.55 seconds
Started Jun 23 05:29:15 PM PDT 24
Finished Jun 23 05:31:06 PM PDT 24
Peak memory 198048 kb
Host smart-c4ddd5cb-2e94-49eb-be6f-82154dd0fd27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464939960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1464939960
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1185580043
Short name T279
Test name
Test status
Simulation time 30062228 ps
CPU time 0.61 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:15 PM PDT 24
Peak memory 194076 kb
Host smart-252d02ab-96b4-441f-adb5-8c8e1c5761db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185580043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1185580043
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2623950785
Short name T225
Test name
Test status
Simulation time 84512533 ps
CPU time 0.73 seconds
Started Jun 23 05:28:10 PM PDT 24
Finished Jun 23 05:28:11 PM PDT 24
Peak memory 195316 kb
Host smart-df4f5e4c-25df-4257-bba6-e6278c89d672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623950785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2623950785
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3914968376
Short name T275
Test name
Test status
Simulation time 327428641 ps
CPU time 16.55 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:38 PM PDT 24
Peak memory 195576 kb
Host smart-03284bc3-0be4-4928-b876-de85eebc0458
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914968376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3914968376
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1252434475
Short name T494
Test name
Test status
Simulation time 21419139 ps
CPU time 0.62 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 194920 kb
Host smart-b2d16231-25a9-415d-88c9-949fba3f76c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252434475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1252434475
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2350126118
Short name T51
Test name
Test status
Simulation time 46098504 ps
CPU time 0.87 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:11 PM PDT 24
Peak memory 196608 kb
Host smart-a21b342f-1662-44f5-aa7a-5bab36bbf9c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350126118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2350126118
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1810387433
Short name T509
Test name
Test status
Simulation time 242428442 ps
CPU time 2.57 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 198176 kb
Host smart-62101331-de7c-4f50-ade1-7779378249d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810387433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1810387433
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.589962439
Short name T17
Test name
Test status
Simulation time 41109225 ps
CPU time 1.33 seconds
Started Jun 23 05:28:23 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 195856 kb
Host smart-0b30a664-098f-4ea5-8f2e-d02c1b00e676
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589962439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.589962439
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.4048446010
Short name T435
Test name
Test status
Simulation time 137644770 ps
CPU time 1.28 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 196984 kb
Host smart-dc93a127-131b-46ea-9d4a-246e5ee81acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048446010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.4048446010
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2241867214
Short name T514
Test name
Test status
Simulation time 52133705 ps
CPU time 1 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 195808 kb
Host smart-61fe545c-0a6b-4330-aea2-86f9e14d8440
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241867214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2241867214
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.3573061410
Short name T62
Test name
Test status
Simulation time 316996842 ps
CPU time 3.52 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 198008 kb
Host smart-471ee485-7e48-4b50-b9f1-adc0940a42d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573061410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.3573061410
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.446078816
Short name T37
Test name
Test status
Simulation time 222816057 ps
CPU time 0.83 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:21 PM PDT 24
Peak memory 213660 kb
Host smart-4ceeb775-19e7-4e66-a39b-fdb2ef231295
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446078816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.446078816
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4133324432
Short name T353
Test name
Test status
Simulation time 32648243 ps
CPU time 0.88 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 195216 kb
Host smart-156bf12e-ca32-4f6a-9493-9b20a0a4bc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133324432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4133324432
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3315378675
Short name T344
Test name
Test status
Simulation time 109446689 ps
CPU time 1.41 seconds
Started Jun 23 05:28:09 PM PDT 24
Finished Jun 23 05:28:11 PM PDT 24
Peak memory 196752 kb
Host smart-98c35a7d-9b9a-432a-8d8c-488fedc8092c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315378675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3315378675
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.3498407371
Short name T315
Test name
Test status
Simulation time 7059763257 ps
CPU time 49.59 seconds
Started Jun 23 05:28:22 PM PDT 24
Finished Jun 23 05:29:13 PM PDT 24
Peak memory 198156 kb
Host smart-20daf6cc-698f-4556-9d29-35acf14318c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498407371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.3498407371
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1742669031
Short name T177
Test name
Test status
Simulation time 12396383 ps
CPU time 0.56 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 194472 kb
Host smart-3b682ea3-a364-4434-b7fa-33bb71bd2f35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742669031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1742669031
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3387560482
Short name T245
Test name
Test status
Simulation time 39083842 ps
CPU time 0.78 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 195416 kb
Host smart-02669ff4-6296-4238-9e5d-75a029fdf1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387560482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3387560482
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.77253631
Short name T623
Test name
Test status
Simulation time 632638709 ps
CPU time 15.6 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:43 PM PDT 24
Peak memory 198052 kb
Host smart-a4cfff53-22f5-4d48-a1ed-cf907a5f09a4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77253631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stress
.77253631
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2224751401
Short name T92
Test name
Test status
Simulation time 956345248 ps
CPU time 0.88 seconds
Started Jun 23 05:29:16 PM PDT 24
Finished Jun 23 05:29:19 PM PDT 24
Peak memory 196256 kb
Host smart-9cc20845-453b-4262-9a70-915798fa3256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224751401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2224751401
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1533618742
Short name T442
Test name
Test status
Simulation time 33746344 ps
CPU time 0.81 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 196076 kb
Host smart-2723550d-3b68-445f-869b-570866ec1def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533618742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1533618742
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.960741745
Short name T429
Test name
Test status
Simulation time 60336163 ps
CPU time 2.52 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 198148 kb
Host smart-e4ea5eff-ba60-4b05-b3a6-3c9be72014df
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960741745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.960741745
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2486306308
Short name T395
Test name
Test status
Simulation time 602676034 ps
CPU time 3.48 seconds
Started Jun 23 05:29:29 PM PDT 24
Finished Jun 23 05:29:33 PM PDT 24
Peak memory 197148 kb
Host smart-aa255c42-a9b2-4fdd-b0d9-1aa69948326c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486306308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2486306308
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.4133994922
Short name T249
Test name
Test status
Simulation time 61267067 ps
CPU time 1.35 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 197012 kb
Host smart-cbfba051-0a01-4413-b089-8c92bf9c48c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133994922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.4133994922
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3776501379
Short name T591
Test name
Test status
Simulation time 70386420 ps
CPU time 0.85 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196596 kb
Host smart-c1cc7022-7084-409a-884f-c917b7851d5f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776501379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3776501379
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.111509388
Short name T124
Test name
Test status
Simulation time 93044628 ps
CPU time 3.98 seconds
Started Jun 23 05:29:21 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 197724 kb
Host smart-f024e19c-88e5-4c1a-9e68-924dcce683f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111509388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.111509388
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2040862472
Short name T370
Test name
Test status
Simulation time 300966423 ps
CPU time 1.32 seconds
Started Jun 23 05:29:29 PM PDT 24
Finished Jun 23 05:29:31 PM PDT 24
Peak memory 195612 kb
Host smart-037ad6e7-9292-4d68-884b-97d1066817fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040862472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2040862472
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.674286698
Short name T646
Test name
Test status
Simulation time 527516465 ps
CPU time 1.51 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 196712 kb
Host smart-462391d4-692c-47a7-b5d6-c935715a677e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674286698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.674286698
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2918140701
Short name T234
Test name
Test status
Simulation time 22916125385 ps
CPU time 147.81 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:31:51 PM PDT 24
Peak memory 198204 kb
Host smart-7c2b0031-4560-4122-a221-a39fea6f33c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918140701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2918140701
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.810385748
Short name T267
Test name
Test status
Simulation time 24101031 ps
CPU time 0.59 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 194224 kb
Host smart-4d069c77-05a5-4dc0-afe0-8fcdc86b6a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810385748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.810385748
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1311653139
Short name T478
Test name
Test status
Simulation time 84826758 ps
CPU time 0.64 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 194048 kb
Host smart-3b41b198-abc6-4c5e-8ba4-fff6fc6951e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311653139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1311653139
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.812264254
Short name T371
Test name
Test status
Simulation time 719425549 ps
CPU time 10.42 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:38 PM PDT 24
Peak memory 198020 kb
Host smart-e10ae22a-69c8-41ad-9820-d2a705c5a986
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812264254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.812264254
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.162348180
Short name T545
Test name
Test status
Simulation time 92477847 ps
CPU time 0.73 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:21 PM PDT 24
Peak memory 194492 kb
Host smart-9a47144c-9da0-43c6-8705-2ce86a37a2be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162348180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.162348180
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.217666334
Short name T695
Test name
Test status
Simulation time 65501644 ps
CPU time 1.27 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196196 kb
Host smart-7d6ddda4-303c-4f85-b567-4c9ceb030890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217666334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.217666334
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1653132316
Short name T29
Test name
Test status
Simulation time 136491728 ps
CPU time 1.51 seconds
Started Jun 23 05:29:21 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 196720 kb
Host smart-08985197-20dd-4200-b13f-3f4893b38ac2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653132316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1653132316
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3236445300
Short name T659
Test name
Test status
Simulation time 203385531 ps
CPU time 1.93 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 195968 kb
Host smart-b4b6974c-4e43-4636-8e86-d839909a9431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236445300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3236445300
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2032829615
Short name T220
Test name
Test status
Simulation time 23683205 ps
CPU time 0.69 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 194280 kb
Host smart-e452d8ac-9631-4b60-aee2-367c02bf464b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032829615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2032829615
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3644442077
Short name T334
Test name
Test status
Simulation time 60808665 ps
CPU time 1.14 seconds
Started Jun 23 05:29:24 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 196096 kb
Host smart-27b2e330-8bfc-4a19-a3d8-b906d0b2e061
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644442077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3644442077
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.259466601
Short name T310
Test name
Test status
Simulation time 466891160 ps
CPU time 1.57 seconds
Started Jun 23 05:29:23 PM PDT 24
Finished Jun 23 05:29:25 PM PDT 24
Peak memory 197992 kb
Host smart-60424e6b-fc47-40a8-9d13-8b2d7310b766
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259466601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.259466601
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2495917532
Short name T544
Test name
Test status
Simulation time 553226056 ps
CPU time 1.29 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 195880 kb
Host smart-0b0f0074-e43a-45e6-a1de-e2dd91b59e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495917532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2495917532
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3413483488
Short name T706
Test name
Test status
Simulation time 144320193 ps
CPU time 1.48 seconds
Started Jun 23 05:29:24 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 196872 kb
Host smart-086bc081-2543-4183-9b3a-397f352b31ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413483488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3413483488
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2108250194
Short name T477
Test name
Test status
Simulation time 6045113373 ps
CPU time 34.75 seconds
Started Jun 23 05:29:18 PM PDT 24
Finished Jun 23 05:29:54 PM PDT 24
Peak memory 198148 kb
Host smart-1dd51645-cfb2-4828-bdc8-b01531324597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108250194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2108250194
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.1579781197
Short name T471
Test name
Test status
Simulation time 11486486 ps
CPU time 0.58 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 194536 kb
Host smart-8da844bf-6141-42dd-8951-6bff961f34b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579781197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.1579781197
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3046432328
Short name T365
Test name
Test status
Simulation time 51598520 ps
CPU time 0.63 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 194036 kb
Host smart-b1267f62-7360-487e-a078-7b9b0efed41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046432328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3046432328
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.346254702
Short name T162
Test name
Test status
Simulation time 419676290 ps
CPU time 3.85 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:32 PM PDT 24
Peak memory 195772 kb
Host smart-e2fb3542-6d55-4841-8d18-93a4323414ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346254702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.346254702
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.1858922932
Short name T6
Test name
Test status
Simulation time 361905776 ps
CPU time 0.97 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:23 PM PDT 24
Peak memory 196984 kb
Host smart-9792d016-9fc8-43bb-88a2-8cd0b261a11a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858922932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.1858922932
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.1153848565
Short name T172
Test name
Test status
Simulation time 64128390 ps
CPU time 0.77 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:27 PM PDT 24
Peak memory 195540 kb
Host smart-ab763664-5598-4236-802f-9f6bc4c39cb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153848565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.1153848565
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3014981983
Short name T322
Test name
Test status
Simulation time 267022181 ps
CPU time 2.9 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 198176 kb
Host smart-e2430840-41e4-4793-b928-268ab5376c80
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014981983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3014981983
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1860400220
Short name T517
Test name
Test status
Simulation time 112328291 ps
CPU time 1.74 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:29:21 PM PDT 24
Peak memory 196748 kb
Host smart-60736798-e399-431b-9bd5-99720b3e3aca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860400220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1860400220
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2594890767
Short name T65
Test name
Test status
Simulation time 15683158 ps
CPU time 0.65 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:29:20 PM PDT 24
Peak memory 194220 kb
Host smart-6a388b11-cf45-4a34-9a22-2b055d68af7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594890767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2594890767
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1376555314
Short name T377
Test name
Test status
Simulation time 126722656 ps
CPU time 1.22 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 197012 kb
Host smart-b8414478-2052-48ca-8e5f-d9f9c69e939a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376555314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1376555314
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2375955385
Short name T554
Test name
Test status
Simulation time 5685871033 ps
CPU time 5.24 seconds
Started Jun 23 05:29:19 PM PDT 24
Finished Jun 23 05:29:25 PM PDT 24
Peak memory 198000 kb
Host smart-3b75487b-247d-4ca1-aecf-ab044cff9060
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375955385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2375955385
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1541677555
Short name T444
Test name
Test status
Simulation time 52967152 ps
CPU time 1.07 seconds
Started Jun 23 05:29:22 PM PDT 24
Finished Jun 23 05:29:24 PM PDT 24
Peak memory 195796 kb
Host smart-1a2113f2-61a4-466e-9435-42afe869fbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541677555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1541677555
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.4035010873
Short name T461
Test name
Test status
Simulation time 63077404 ps
CPU time 1.08 seconds
Started Jun 23 05:29:20 PM PDT 24
Finished Jun 23 05:29:22 PM PDT 24
Peak memory 196548 kb
Host smart-c6be2ef0-1094-4b78-bf2a-51463625f749
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035010873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.4035010873
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1655046934
Short name T191
Test name
Test status
Simulation time 46128500139 ps
CPU time 150.87 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:31:59 PM PDT 24
Peak memory 198120 kb
Host smart-0bf8bc72-2eeb-49dd-8dba-f3e99c3e14c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655046934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1655046934
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1177987315
Short name T476
Test name
Test status
Simulation time 28417151 ps
CPU time 0.58 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 193848 kb
Host smart-e4928ca1-2e7f-4759-9ada-43b21f58edb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177987315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1177987315
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2340152649
Short name T231
Test name
Test status
Simulation time 80679079 ps
CPU time 0.64 seconds
Started Jun 23 05:29:28 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 194080 kb
Host smart-297c870e-e8f0-4bc4-8ad0-1a85f179d698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340152649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2340152649
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.2707147013
Short name T338
Test name
Test status
Simulation time 574885831 ps
CPU time 10.37 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:37 PM PDT 24
Peak memory 196724 kb
Host smart-48578c9f-95a1-4bff-9a61-4b52c0b0ab07
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707147013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.2707147013
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3559537014
Short name T602
Test name
Test status
Simulation time 101617683 ps
CPU time 1.2 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 196552 kb
Host smart-9a208df8-1fba-4e55-8905-7fc54eb9e1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559537014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3559537014
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2087848165
Short name T665
Test name
Test status
Simulation time 93635782 ps
CPU time 1.37 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 196132 kb
Host smart-cef15b53-cd00-4bb1-886a-88da08fefdad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087848165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2087848165
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.1145597707
Short name T95
Test name
Test status
Simulation time 76650789 ps
CPU time 2.87 seconds
Started Jun 23 05:29:24 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 198072 kb
Host smart-5b1f5ff1-a50e-4254-be2f-2fd29f09ed4b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145597707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.1145597707
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2439745409
Short name T605
Test name
Test status
Simulation time 303973352 ps
CPU time 2.23 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 195844 kb
Host smart-2890d03a-2513-4ccb-8d32-3e0507d6616d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439745409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2439745409
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4190236338
Short name T280
Test name
Test status
Simulation time 113511111 ps
CPU time 1.21 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 195976 kb
Host smart-858c667b-b6ed-4656-ac79-bfaa7a9b793d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190236338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4190236338
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3395272913
Short name T141
Test name
Test status
Simulation time 58303374 ps
CPU time 1.21 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:27 PM PDT 24
Peak memory 196948 kb
Host smart-d6cd17c8-78ea-430e-bf13-317f73dd2e5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395272913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3395272913
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3417435977
Short name T196
Test name
Test status
Simulation time 29714689 ps
CPU time 1.39 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:27 PM PDT 24
Peak memory 197852 kb
Host smart-4eb3657a-c491-4975-acbb-6f2ab990829c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417435977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3417435977
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2303107861
Short name T369
Test name
Test status
Simulation time 45111190 ps
CPU time 1 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:28 PM PDT 24
Peak memory 195628 kb
Host smart-96040547-5d63-45c7-befe-59c1621dd341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303107861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2303107861
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3147159580
Short name T552
Test name
Test status
Simulation time 44694944 ps
CPU time 1.2 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 195568 kb
Host smart-55367b8b-3722-464b-9d39-83b12d30ad69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147159580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3147159580
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.3539275919
Short name T20
Test name
Test status
Simulation time 14895566812 ps
CPU time 159.28 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:32:07 PM PDT 24
Peak memory 198160 kb
Host smart-22970a5b-6e4d-4d95-9200-cd58d2a26279
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539275919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.3539275919
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3082189427
Short name T39
Test name
Test status
Simulation time 60902846 ps
CPU time 0.57 seconds
Started Jun 23 05:29:30 PM PDT 24
Finished Jun 23 05:29:31 PM PDT 24
Peak memory 194728 kb
Host smart-bb721bac-631a-47c7-82f4-a82473341e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082189427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3082189427
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2938438352
Short name T528
Test name
Test status
Simulation time 60821650 ps
CPU time 0.79 seconds
Started Jun 23 05:29:31 PM PDT 24
Finished Jun 23 05:29:32 PM PDT 24
Peak memory 195300 kb
Host smart-24ab776c-f1f4-40ad-aac5-6893f2361d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938438352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2938438352
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2051251215
Short name T426
Test name
Test status
Simulation time 8087827968 ps
CPU time 26 seconds
Started Jun 23 05:29:32 PM PDT 24
Finished Jun 23 05:29:59 PM PDT 24
Peak memory 196692 kb
Host smart-9be96e68-0078-4137-977b-791e977842da
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051251215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2051251215
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.2449613126
Short name T354
Test name
Test status
Simulation time 224119322 ps
CPU time 0.67 seconds
Started Jun 23 05:29:30 PM PDT 24
Finished Jun 23 05:29:31 PM PDT 24
Peak memory 194688 kb
Host smart-62bf5b38-0ee4-4b2a-9914-09cca3eaa446
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449613126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.2449613126
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3727039105
Short name T27
Test name
Test status
Simulation time 83481097 ps
CPU time 1.21 seconds
Started Jun 23 05:29:29 PM PDT 24
Finished Jun 23 05:29:30 PM PDT 24
Peak memory 195872 kb
Host smart-32020c23-2ac9-45d3-8aef-b671629a531b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727039105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3727039105
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.2736153064
Short name T122
Test name
Test status
Simulation time 31450010 ps
CPU time 1.42 seconds
Started Jun 23 05:29:31 PM PDT 24
Finished Jun 23 05:29:33 PM PDT 24
Peak memory 197844 kb
Host smart-69002941-d187-4fa2-b03e-50eab2a6897b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736153064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.2736153064
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.106456664
Short name T557
Test name
Test status
Simulation time 290003516 ps
CPU time 1.78 seconds
Started Jun 23 05:29:29 PM PDT 24
Finished Jun 23 05:29:32 PM PDT 24
Peak memory 195984 kb
Host smart-d9b5b52f-5312-475e-b00b-15008e5febe3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106456664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
106456664
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1991032187
Short name T467
Test name
Test status
Simulation time 42807751 ps
CPU time 0.71 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 194284 kb
Host smart-20e6d476-53d2-4b57-88f2-389a3ba96b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991032187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1991032187
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1271271069
Short name T160
Test name
Test status
Simulation time 189747461 ps
CPU time 1.18 seconds
Started Jun 23 05:29:27 PM PDT 24
Finished Jun 23 05:29:29 PM PDT 24
Peak memory 195872 kb
Host smart-95a8acc8-aa74-4f5c-ac0f-a22a7018abf5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271271069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1271271069
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1218796397
Short name T48
Test name
Test status
Simulation time 21681262 ps
CPU time 0.97 seconds
Started Jun 23 05:29:30 PM PDT 24
Finished Jun 23 05:29:32 PM PDT 24
Peak memory 196532 kb
Host smart-6f1f730a-4aff-4afc-8afa-ff4f2455c7e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218796397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1218796397
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1005668488
Short name T604
Test name
Test status
Simulation time 322278872 ps
CPU time 1.3 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:27 PM PDT 24
Peak memory 196924 kb
Host smart-8a2ecd6f-81ea-440e-a03a-7f68ff4a6326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005668488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1005668488
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3812351818
Short name T49
Test name
Test status
Simulation time 29822751 ps
CPU time 0.78 seconds
Started Jun 23 05:29:25 PM PDT 24
Finished Jun 23 05:29:26 PM PDT 24
Peak memory 195116 kb
Host smart-6a5ef0c2-3cc7-43f2-ae3c-33fb4322c33b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812351818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3812351818
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2028843583
Short name T197
Test name
Test status
Simulation time 197374022552 ps
CPU time 176.88 seconds
Started Jun 23 05:29:31 PM PDT 24
Finished Jun 23 05:32:28 PM PDT 24
Peak memory 198204 kb
Host smart-aef6952e-2349-4a7e-9e11-515b88b8dce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028843583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2028843583
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3508829
Short name T690
Test name
Test status
Simulation time 17589992 ps
CPU time 0.54 seconds
Started Jun 23 05:29:35 PM PDT 24
Finished Jun 23 05:29:36 PM PDT 24
Peak memory 192716 kb
Host smart-60919988-afd0-4b29-bd9d-609bbafe2f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3508829
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1573889116
Short name T458
Test name
Test status
Simulation time 32896455 ps
CPU time 0.94 seconds
Started Jun 23 05:29:30 PM PDT 24
Finished Jun 23 05:29:31 PM PDT 24
Peak memory 196004 kb
Host smart-3ac1344a-8ecd-4623-b784-28324c0a18f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573889116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1573889116
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2098096395
Short name T283
Test name
Test status
Simulation time 801099967 ps
CPU time 26.24 seconds
Started Jun 23 05:29:30 PM PDT 24
Finished Jun 23 05:29:57 PM PDT 24
Peak memory 196968 kb
Host smart-d70e53ca-f751-488e-83f8-3a2f02f37efe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098096395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2098096395
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.469407551
Short name T447
Test name
Test status
Simulation time 233752855 ps
CPU time 0.74 seconds
Started Jun 23 05:29:29 PM PDT 24
Finished Jun 23 05:29:30 PM PDT 24
Peak memory 194844 kb
Host smart-628e50ef-cc62-4784-a4e4-f7635c7e021e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469407551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.469407551
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1085268547
Short name T182
Test name
Test status
Simulation time 84522008 ps
CPU time 1.19 seconds
Started Jun 23 05:29:30 PM PDT 24
Finished Jun 23 05:29:32 PM PDT 24
Peak memory 196140 kb
Host smart-8c326d15-bfde-4614-9fb9-9f467751063d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085268547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1085268547
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.378523796
Short name T452
Test name
Test status
Simulation time 110609883 ps
CPU time 2.25 seconds
Started Jun 23 05:29:31 PM PDT 24
Finished Jun 23 05:29:34 PM PDT 24
Peak memory 198156 kb
Host smart-8df6426f-c1f4-4e41-a093-74d28bb104a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378523796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.378523796
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1583203265
Short name T525
Test name
Test status
Simulation time 524285961 ps
CPU time 2.49 seconds
Started Jun 23 05:29:26 PM PDT 24
Finished Jun 23 05:29:30 PM PDT 24
Peak memory 196368 kb
Host smart-80cf6797-a6be-412d-b538-1568fb7d0beb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583203265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1583203265
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.860619845
Short name T224
Test name
Test status
Simulation time 36834675 ps
CPU time 0.99 seconds
Started Jun 23 05:29:33 PM PDT 24
Finished Jun 23 05:29:34 PM PDT 24
Peak memory 196420 kb
Host smart-15fefa96-b3d0-4bc8-a92d-0abea40da90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860619845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.860619845
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.766716453
Short name T294
Test name
Test status
Simulation time 55582664 ps
CPU time 1.07 seconds
Started Jun 23 05:29:30 PM PDT 24
Finished Jun 23 05:29:31 PM PDT 24
Peak memory 195976 kb
Host smart-50261442-234c-4d9c-94ef-9b53d5ccb4e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766716453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.766716453
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.4064123814
Short name T505
Test name
Test status
Simulation time 766871066 ps
CPU time 2.49 seconds
Started Jun 23 05:29:33 PM PDT 24
Finished Jun 23 05:29:35 PM PDT 24
Peak memory 197904 kb
Host smart-569092f5-005d-4abc-9f6c-bc558a6260f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064123814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.4064123814
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.401900343
Short name T441
Test name
Test status
Simulation time 264423222 ps
CPU time 1.26 seconds
Started Jun 23 05:29:31 PM PDT 24
Finished Jun 23 05:29:33 PM PDT 24
Peak memory 196468 kb
Host smart-17b037a8-fdb0-476a-b3e0-07d8d99b1578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401900343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.401900343
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.528712889
Short name T157
Test name
Test status
Simulation time 158291187 ps
CPU time 1.22 seconds
Started Jun 23 05:29:28 PM PDT 24
Finished Jun 23 05:29:30 PM PDT 24
Peak memory 195736 kb
Host smart-46fe731b-6731-428f-be21-3ed818b48dfd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528712889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.528712889
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1405426293
Short name T551
Test name
Test status
Simulation time 5821520494 ps
CPU time 65.58 seconds
Started Jun 23 05:29:36 PM PDT 24
Finished Jun 23 05:30:42 PM PDT 24
Peak memory 198088 kb
Host smart-a6e6257e-1097-4529-8eae-ca138eeff64e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405426293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1405426293
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2226556098
Short name T142
Test name
Test status
Simulation time 13898835 ps
CPU time 0.57 seconds
Started Jun 23 05:29:35 PM PDT 24
Finished Jun 23 05:29:36 PM PDT 24
Peak memory 193844 kb
Host smart-e3cf23f1-eb85-4308-9a6f-5d81c6775d2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226556098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2226556098
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3155056810
Short name T679
Test name
Test status
Simulation time 181475760 ps
CPU time 0.92 seconds
Started Jun 23 05:29:37 PM PDT 24
Finished Jun 23 05:29:38 PM PDT 24
Peak memory 196676 kb
Host smart-308c82b1-ee90-4016-83d8-c56ed175d3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155056810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3155056810
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.270621834
Short name T555
Test name
Test status
Simulation time 175911503 ps
CPU time 6.38 seconds
Started Jun 23 05:29:37 PM PDT 24
Finished Jun 23 05:29:44 PM PDT 24
Peak memory 198024 kb
Host smart-45ad7cce-dbd0-4442-9fff-8c2870a4804b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270621834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.270621834
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.2802554629
Short name T512
Test name
Test status
Simulation time 224311625 ps
CPU time 0.8 seconds
Started Jun 23 05:29:36 PM PDT 24
Finished Jun 23 05:29:37 PM PDT 24
Peak memory 195880 kb
Host smart-0d5a1277-a60b-4f3d-bc96-29ebfeac1428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802554629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.2802554629
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2838172411
Short name T97
Test name
Test status
Simulation time 41325630 ps
CPU time 0.85 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:40 PM PDT 24
Peak memory 195504 kb
Host smart-f3b2e902-5c33-475a-a162-ad92b46b0c36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838172411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2838172411
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.387637205
Short name T662
Test name
Test status
Simulation time 249628348 ps
CPU time 3.61 seconds
Started Jun 23 05:29:34 PM PDT 24
Finished Jun 23 05:29:38 PM PDT 24
Peak memory 198132 kb
Host smart-fb756d26-8ac7-43b8-a7d8-df712ca5a486
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387637205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 46.gpio_intr_with_filter_rand_intr_event.387637205
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1406522359
Short name T632
Test name
Test status
Simulation time 204712779 ps
CPU time 2.98 seconds
Started Jun 23 05:29:35 PM PDT 24
Finished Jun 23 05:29:39 PM PDT 24
Peak memory 197164 kb
Host smart-7090359d-6adc-42cb-9cb0-d25b1a836df5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406522359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1406522359
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3227635015
Short name T130
Test name
Test status
Simulation time 21367646 ps
CPU time 0.69 seconds
Started Jun 23 05:29:37 PM PDT 24
Finished Jun 23 05:29:38 PM PDT 24
Peak memory 194264 kb
Host smart-de2f785c-5275-4a81-aa38-c9462d78074e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227635015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3227635015
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2157724344
Short name T359
Test name
Test status
Simulation time 123359246 ps
CPU time 1.01 seconds
Started Jun 23 05:29:35 PM PDT 24
Finished Jun 23 05:29:36 PM PDT 24
Peak memory 196104 kb
Host smart-169b9048-90e7-4d95-8adf-1a37935a7bd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157724344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2157724344
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.1771647125
Short name T592
Test name
Test status
Simulation time 245260717 ps
CPU time 3.29 seconds
Started Jun 23 05:29:35 PM PDT 24
Finished Jun 23 05:29:39 PM PDT 24
Peak memory 198024 kb
Host smart-d02739f7-de41-42ce-9eec-43c463ca5967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771647125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.1771647125
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3153329160
Short name T570
Test name
Test status
Simulation time 93766852 ps
CPU time 1.23 seconds
Started Jun 23 05:29:34 PM PDT 24
Finished Jun 23 05:29:36 PM PDT 24
Peak memory 195856 kb
Host smart-ebd5d5b6-2db6-43c3-98e3-cc1dd67afe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153329160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3153329160
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.415224590
Short name T323
Test name
Test status
Simulation time 38824453 ps
CPU time 1.06 seconds
Started Jun 23 05:29:38 PM PDT 24
Finished Jun 23 05:29:39 PM PDT 24
Peak memory 195640 kb
Host smart-99620a15-1277-4127-98fe-2cefc4b260a2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415224590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.415224590
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.712809260
Short name T324
Test name
Test status
Simulation time 18169617857 ps
CPU time 125.67 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:31:45 PM PDT 24
Peak memory 198144 kb
Host smart-44a03c99-245c-4aeb-931a-db12382da7eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712809260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.712809260
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.4243197732
Short name T168
Test name
Test status
Simulation time 40841292 ps
CPU time 0.56 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:40 PM PDT 24
Peak memory 194544 kb
Host smart-d78dab27-e99f-4bb1-8bae-51eab800337d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243197732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.4243197732
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.3830940911
Short name T628
Test name
Test status
Simulation time 39958078 ps
CPU time 0.79 seconds
Started Jun 23 05:29:38 PM PDT 24
Finished Jun 23 05:29:39 PM PDT 24
Peak memory 195252 kb
Host smart-60db2d40-dbcc-4558-83c3-e37a5af6cf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830940911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.3830940911
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2029851580
Short name T204
Test name
Test status
Simulation time 1717243416 ps
CPU time 11.93 seconds
Started Jun 23 05:29:40 PM PDT 24
Finished Jun 23 05:29:52 PM PDT 24
Peak memory 196796 kb
Host smart-64888b3f-d8ab-4438-8377-5c09b4b4df22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029851580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2029851580
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2884108401
Short name T163
Test name
Test status
Simulation time 272204849 ps
CPU time 0.96 seconds
Started Jun 23 05:29:42 PM PDT 24
Finished Jun 23 05:29:44 PM PDT 24
Peak memory 197112 kb
Host smart-db50692b-24c0-4cbe-bd34-9adc1dafd031
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884108401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2884108401
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.662632820
Short name T526
Test name
Test status
Simulation time 83987026 ps
CPU time 0.71 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:40 PM PDT 24
Peak memory 194364 kb
Host smart-0a578778-1549-4d49-a9a6-cf42ce39c764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662632820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.662632820
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3534686638
Short name T491
Test name
Test status
Simulation time 110686045 ps
CPU time 3.36 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:43 PM PDT 24
Peak memory 198116 kb
Host smart-ed2e6905-5f4d-48f0-b0df-412c6adc8416
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534686638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3534686638
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3517081168
Short name T641
Test name
Test status
Simulation time 195505094 ps
CPU time 1.45 seconds
Started Jun 23 05:29:34 PM PDT 24
Finished Jun 23 05:29:36 PM PDT 24
Peak memory 196072 kb
Host smart-1c5f4932-09b3-4e62-8033-ca418f24cb52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517081168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3517081168
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.783352412
Short name T164
Test name
Test status
Simulation time 115525751 ps
CPU time 0.81 seconds
Started Jun 23 05:29:37 PM PDT 24
Finished Jun 23 05:29:38 PM PDT 24
Peak memory 196616 kb
Host smart-9993a97f-c075-4d3e-9fa9-d729a6cf096e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783352412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.783352412
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.3186971847
Short name T565
Test name
Test status
Simulation time 20290428 ps
CPU time 0.86 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:41 PM PDT 24
Peak memory 196092 kb
Host smart-b88d8e0e-38c7-4d02-b6ef-67217e843006
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186971847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.3186971847
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.3484078977
Short name T671
Test name
Test status
Simulation time 471644007 ps
CPU time 5.34 seconds
Started Jun 23 05:29:38 PM PDT 24
Finished Jun 23 05:29:44 PM PDT 24
Peak memory 198040 kb
Host smart-6e5b9ea4-18a8-4630-85a2-d04dd83b657e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484078977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.3484078977
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3995389728
Short name T175
Test name
Test status
Simulation time 81052078 ps
CPU time 1.3 seconds
Started Jun 23 05:29:34 PM PDT 24
Finished Jun 23 05:29:35 PM PDT 24
Peak memory 197904 kb
Host smart-3f00bf72-ac7d-4c59-ae7a-1e96838df59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995389728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3995389728
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.265203971
Short name T300
Test name
Test status
Simulation time 320027024 ps
CPU time 1.19 seconds
Started Jun 23 05:29:36 PM PDT 24
Finished Jun 23 05:29:38 PM PDT 24
Peak memory 195756 kb
Host smart-8c1cbde0-301e-459b-9cfb-c735ab201063
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265203971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.265203971
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.299356903
Short name T151
Test name
Test status
Simulation time 17031437677 ps
CPU time 189.88 seconds
Started Jun 23 05:29:41 PM PDT 24
Finished Jun 23 05:32:51 PM PDT 24
Peak memory 198212 kb
Host smart-bb1bb3b3-4a00-4403-a3b2-56c7763fb603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299356903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.299356903
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3884782063
Short name T562
Test name
Test status
Simulation time 562473144552 ps
CPU time 406.17 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:36:26 PM PDT 24
Peak memory 198228 kb
Host smart-ba7769af-19b4-4d64-be2b-a544802d583c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3884782063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3884782063
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1035901741
Short name T288
Test name
Test status
Simulation time 13841235 ps
CPU time 0.57 seconds
Started Jun 23 05:29:40 PM PDT 24
Finished Jun 23 05:29:41 PM PDT 24
Peak memory 193752 kb
Host smart-e0327b4c-e53c-4a0f-a42c-60ac69117f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035901741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1035901741
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1940708370
Short name T221
Test name
Test status
Simulation time 37131823 ps
CPU time 0.88 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:41 PM PDT 24
Peak memory 195376 kb
Host smart-81ba9ab8-9416-4754-968b-1547467b97b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940708370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1940708370
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.4202073685
Short name T527
Test name
Test status
Simulation time 433437238 ps
CPU time 15.38 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:55 PM PDT 24
Peak memory 196504 kb
Host smart-c2daffa1-2e46-4fba-9125-14af074508fe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202073685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.4202073685
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3933040447
Short name T561
Test name
Test status
Simulation time 45906633 ps
CPU time 0.9 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:41 PM PDT 24
Peak memory 196788 kb
Host smart-7175a339-a5ec-41cc-abe8-96e04fdd02bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933040447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3933040447
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3143159699
Short name T178
Test name
Test status
Simulation time 62729768 ps
CPU time 1.24 seconds
Started Jun 23 05:29:40 PM PDT 24
Finished Jun 23 05:29:42 PM PDT 24
Peak memory 196868 kb
Host smart-99fc2692-0f6d-436a-8609-9195db819e12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143159699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3143159699
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.778464098
Short name T254
Test name
Test status
Simulation time 281613032 ps
CPU time 3.01 seconds
Started Jun 23 05:29:38 PM PDT 24
Finished Jun 23 05:29:42 PM PDT 24
Peak memory 197216 kb
Host smart-982ddbc6-5716-4165-9263-8dc881c2fed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778464098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger.
778464098
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.4099165071
Short name T547
Test name
Test status
Simulation time 64744102 ps
CPU time 1.29 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:41 PM PDT 24
Peak memory 197080 kb
Host smart-ac63619f-4482-479e-80d0-a2df914014d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099165071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.4099165071
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4177749606
Short name T546
Test name
Test status
Simulation time 21761603 ps
CPU time 0.76 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:40 PM PDT 24
Peak memory 195376 kb
Host smart-e0447198-3a3a-428b-b9cf-6708fe0798fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177749606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4177749606
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.177672435
Short name T462
Test name
Test status
Simulation time 217636311 ps
CPU time 3.74 seconds
Started Jun 23 05:29:40 PM PDT 24
Finished Jun 23 05:29:45 PM PDT 24
Peak memory 197976 kb
Host smart-4cb0871e-30e7-486d-b548-880f4e91b615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177672435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.177672435
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.613753031
Short name T636
Test name
Test status
Simulation time 202053118 ps
CPU time 1.13 seconds
Started Jun 23 05:29:44 PM PDT 24
Finished Jun 23 05:29:46 PM PDT 24
Peak memory 195560 kb
Host smart-094f1dc0-a2ac-4e7d-a83a-9aee6fd0271e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613753031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.613753031
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.4121120375
Short name T302
Test name
Test status
Simulation time 201065844 ps
CPU time 1.03 seconds
Started Jun 23 05:29:38 PM PDT 24
Finished Jun 23 05:29:39 PM PDT 24
Peak memory 195788 kb
Host smart-116fb16b-b04d-4817-a44b-980f8835a820
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121120375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.4121120375
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2844506344
Short name T413
Test name
Test status
Simulation time 17372405366 ps
CPU time 105.95 seconds
Started Jun 23 05:29:40 PM PDT 24
Finished Jun 23 05:31:26 PM PDT 24
Peak memory 198184 kb
Host smart-ec85ad81-f2d1-4f98-ba4c-0d1e7b934ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844506344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2844506344
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.3295865989
Short name T57
Test name
Test status
Simulation time 84706194085 ps
CPU time 577.35 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:39:17 PM PDT 24
Peak memory 198224 kb
Host smart-828f7342-58ab-41a3-98fb-96ce22d3d85c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3295865989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.3295865989
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2189577225
Short name T524
Test name
Test status
Simulation time 22637494 ps
CPU time 0.59 seconds
Started Jun 23 05:29:45 PM PDT 24
Finished Jun 23 05:29:46 PM PDT 24
Peak memory 194868 kb
Host smart-645ed346-b354-4d33-8459-f4210f9d20d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189577225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2189577225
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1352454689
Short name T702
Test name
Test status
Simulation time 29195368 ps
CPU time 0.81 seconds
Started Jun 23 05:29:43 PM PDT 24
Finished Jun 23 05:29:45 PM PDT 24
Peak memory 196316 kb
Host smart-cc1535ab-d2c6-4fc6-ad2f-a439271ea16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352454689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1352454689
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.2884131118
Short name T453
Test name
Test status
Simulation time 927149723 ps
CPU time 25.61 seconds
Started Jun 23 05:29:42 PM PDT 24
Finished Jun 23 05:30:08 PM PDT 24
Peak memory 197160 kb
Host smart-b4675597-a34a-447c-8bcf-95bc0d650fdf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884131118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.2884131118
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1500369309
Short name T343
Test name
Test status
Simulation time 344323157 ps
CPU time 1.01 seconds
Started Jun 23 05:29:52 PM PDT 24
Finished Jun 23 05:29:54 PM PDT 24
Peak memory 196600 kb
Host smart-2657e22d-3599-4c1e-886c-b2fc2e79f39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500369309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1500369309
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1212436367
Short name T336
Test name
Test status
Simulation time 47920699 ps
CPU time 1.21 seconds
Started Jun 23 05:29:45 PM PDT 24
Finished Jun 23 05:29:47 PM PDT 24
Peak memory 197088 kb
Host smart-a2d89fba-94f0-4048-a99d-66fbd8db1173
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212436367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1212436367
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3318397238
Short name T362
Test name
Test status
Simulation time 939857368 ps
CPU time 3.59 seconds
Started Jun 23 05:29:48 PM PDT 24
Finished Jun 23 05:29:52 PM PDT 24
Peak memory 198156 kb
Host smart-1e9b10fd-5dc0-4c6d-851d-5c6eebbdda39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318397238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3318397238
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.2003546833
Short name T107
Test name
Test status
Simulation time 151767095 ps
CPU time 2.6 seconds
Started Jun 23 05:29:45 PM PDT 24
Finished Jun 23 05:29:48 PM PDT 24
Peak memory 196960 kb
Host smart-587e6d75-c304-49a5-83fc-2e819f37a1c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003546833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.2003546833
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1853730859
Short name T159
Test name
Test status
Simulation time 372519095 ps
CPU time 1.34 seconds
Started Jun 23 05:29:40 PM PDT 24
Finished Jun 23 05:29:42 PM PDT 24
Peak memory 197088 kb
Host smart-79f2da11-ac38-4881-95ed-a7d086acfb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853730859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1853730859
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1032642857
Short name T581
Test name
Test status
Simulation time 35615840 ps
CPU time 1.34 seconds
Started Jun 23 05:29:44 PM PDT 24
Finished Jun 23 05:29:45 PM PDT 24
Peak memory 198112 kb
Host smart-451cf79e-8044-4c75-80d2-e2f4e39e44b9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032642857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1032642857
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3891498834
Short name T185
Test name
Test status
Simulation time 817293812 ps
CPU time 3.55 seconds
Started Jun 23 05:29:46 PM PDT 24
Finished Jun 23 05:29:50 PM PDT 24
Peak memory 197992 kb
Host smart-e13dbf1d-bd6d-4878-8c1e-59e2e8e1f47e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891498834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3891498834
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3990173196
Short name T350
Test name
Test status
Simulation time 42722769 ps
CPU time 1.21 seconds
Started Jun 23 05:29:39 PM PDT 24
Finished Jun 23 05:29:41 PM PDT 24
Peak memory 195588 kb
Host smart-3d263f74-dd0c-499f-b3a1-6d24d785f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990173196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3990173196
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3702319272
Short name T385
Test name
Test status
Simulation time 76108532 ps
CPU time 1.34 seconds
Started Jun 23 05:29:41 PM PDT 24
Finished Jun 23 05:29:43 PM PDT 24
Peak memory 196224 kb
Host smart-da998873-4d10-4cb0-8b3c-8981fa29e3d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702319272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3702319272
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2904999919
Short name T349
Test name
Test status
Simulation time 5037551662 ps
CPU time 124.73 seconds
Started Jun 23 05:29:45 PM PDT 24
Finished Jun 23 05:31:50 PM PDT 24
Peak memory 198184 kb
Host smart-741f1e2d-5286-4b14-a8a8-ab8a077c6cd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904999919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2904999919
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1508377697
Short name T144
Test name
Test status
Simulation time 49659369 ps
CPU time 0.65 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 193960 kb
Host smart-2db8d2d7-fc18-4c82-b572-33200f92f592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508377697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1508377697
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2191870568
Short name T329
Test name
Test status
Simulation time 51098306 ps
CPU time 0.94 seconds
Started Jun 23 05:28:12 PM PDT 24
Finished Jun 23 05:28:14 PM PDT 24
Peak memory 195748 kb
Host smart-bb1d5a96-1aa6-4795-b27a-b3c4d41b00a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191870568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2191870568
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3757077277
Short name T511
Test name
Test status
Simulation time 386819758 ps
CPU time 20.82 seconds
Started Jun 23 05:28:13 PM PDT 24
Finished Jun 23 05:28:34 PM PDT 24
Peak memory 196876 kb
Host smart-ca6853ad-35f5-4603-98a1-d5cc0f17d92b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757077277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3757077277
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3920015894
Short name T210
Test name
Test status
Simulation time 45940130 ps
CPU time 0.66 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 195224 kb
Host smart-26f4d7f9-d30e-4a97-9889-7b96bd70f9ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920015894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3920015894
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3759634863
Short name T390
Test name
Test status
Simulation time 58996941 ps
CPU time 1.09 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 196192 kb
Host smart-5aebc2f0-8e44-4859-bf28-273b548c4acc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759634863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3759634863
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.722570288
Short name T313
Test name
Test status
Simulation time 188692935 ps
CPU time 2.7 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 198132 kb
Host smart-4a5c8104-9ee5-4ad7-8f30-507a4d543106
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722570288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.722570288
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.3188743734
Short name T170
Test name
Test status
Simulation time 51081759 ps
CPU time 1.31 seconds
Started Jun 23 05:28:12 PM PDT 24
Finished Jun 23 05:28:14 PM PDT 24
Peak memory 196788 kb
Host smart-9adea57a-cc67-4c11-880b-91f6485eaf74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188743734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
3188743734
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1454681161
Short name T713
Test name
Test status
Simulation time 63685471 ps
CPU time 1.36 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 198024 kb
Host smart-f71c9d20-9ba9-4484-a612-8db1e9e20cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454681161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1454681161
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4214619888
Short name T518
Test name
Test status
Simulation time 35398926 ps
CPU time 0.65 seconds
Started Jun 23 05:28:22 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 194280 kb
Host smart-acfce9d2-c21f-4552-be7f-3489e831d4f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214619888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4214619888
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3755393625
Short name T266
Test name
Test status
Simulation time 1288083500 ps
CPU time 5.58 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 197972 kb
Host smart-64ac4c61-d324-4050-9eab-0efd2f743f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755393625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3755393625
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2591238834
Short name T363
Test name
Test status
Simulation time 42574227 ps
CPU time 0.97 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:16 PM PDT 24
Peak memory 196888 kb
Host smart-9a917527-a4b0-4578-be23-04aeee9efb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591238834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2591238834
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1560488392
Short name T253
Test name
Test status
Simulation time 75258639 ps
CPU time 1.22 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:20 PM PDT 24
Peak memory 195552 kb
Host smart-5af278a3-c6c6-4d6f-abd7-7d0a1e554cf8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560488392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1560488392
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2049432237
Short name T139
Test name
Test status
Simulation time 14358626182 ps
CPU time 195.01 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:31:31 PM PDT 24
Peak memory 198160 kb
Host smart-4b601b80-5405-4f18-ae34-db32d0c7df61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049432237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2049432237
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.262480724
Short name T325
Test name
Test status
Simulation time 14220391 ps
CPU time 0.6 seconds
Started Jun 23 05:28:13 PM PDT 24
Finished Jun 23 05:28:14 PM PDT 24
Peak memory 194544 kb
Host smart-d0035791-6937-4a3e-8dde-e2affca7c56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262480724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.262480724
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1992063471
Short name T333
Test name
Test status
Simulation time 45235128 ps
CPU time 0.86 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 195160 kb
Host smart-2472a37f-8c2d-4a20-8c42-881f0f223ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992063471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1992063471
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.399294743
Short name T93
Test name
Test status
Simulation time 594243006 ps
CPU time 7.79 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 197160 kb
Host smart-deff41df-dd4d-40db-b5c0-78b3669ccf6e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399294743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.399294743
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2943739282
Short name T5
Test name
Test status
Simulation time 126976246 ps
CPU time 0.85 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 196856 kb
Host smart-313f3a5c-bb37-4ca0-bf2e-a513259cc157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943739282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2943739282
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.212674412
Short name T110
Test name
Test status
Simulation time 125208511 ps
CPU time 1.4 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 196864 kb
Host smart-22d9d673-fdc0-49b1-a4c2-4190ca12c904
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212674412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.212674412
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3791901603
Short name T630
Test name
Test status
Simulation time 21339625 ps
CPU time 0.98 seconds
Started Jun 23 05:28:13 PM PDT 24
Finished Jun 23 05:28:14 PM PDT 24
Peak memory 196720 kb
Host smart-834f7ffb-2611-4491-bc55-f546e342e8b0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791901603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3791901603
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3750498284
Short name T380
Test name
Test status
Simulation time 103378360 ps
CPU time 3.33 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 197176 kb
Host smart-969f1603-a1a1-4cb4-a975-88b357c1bcfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750498284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3750498284
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3326137525
Short name T15
Test name
Test status
Simulation time 174247516 ps
CPU time 0.82 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 196064 kb
Host smart-250bed8c-099b-4aca-9427-0899c25596f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326137525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3326137525
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.429332529
Short name T617
Test name
Test status
Simulation time 32481559 ps
CPU time 0.92 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 197340 kb
Host smart-9a423fcf-aafd-45bc-a4f9-00a14b496c62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429332529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.429332529
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3473536492
Short name T378
Test name
Test status
Simulation time 809812267 ps
CPU time 3.44 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 197860 kb
Host smart-4daba035-febf-4218-a858-a00dc96cba07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473536492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3473536492
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1462469133
Short name T230
Test name
Test status
Simulation time 48779391 ps
CPU time 1.01 seconds
Started Jun 23 05:28:24 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 196432 kb
Host smart-5eb9b30e-782b-47a7-980c-e675ba7aebdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462469133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1462469133
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.4076150038
Short name T510
Test name
Test status
Simulation time 76750827 ps
CPU time 1.01 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:16 PM PDT 24
Peak memory 195832 kb
Host smart-188402f5-fce9-40cf-b924-bb5508aa3177
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076150038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.4076150038
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1687369939
Short name T21
Test name
Test status
Simulation time 216792054879 ps
CPU time 149.38 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:30:52 PM PDT 24
Peak memory 198164 kb
Host smart-c4bf5eba-4d2e-49d6-8d3b-b18fa7640218
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687369939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1687369939
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.10406598
Short name T258
Test name
Test status
Simulation time 45444725 ps
CPU time 0.6 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:21 PM PDT 24
Peak memory 194048 kb
Host smart-414969af-9d6e-473f-a856-a9b6ac9749a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10406598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.10406598
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1250766968
Short name T236
Test name
Test status
Simulation time 32849087 ps
CPU time 0.81 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 195880 kb
Host smart-5d10a8a4-6890-4bbd-b45b-bff7830a6819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250766968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1250766968
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3225091735
Short name T388
Test name
Test status
Simulation time 749900440 ps
CPU time 15.95 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:38 PM PDT 24
Peak memory 197996 kb
Host smart-b38141a6-9c43-44d6-9f82-e218f02de284
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225091735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3225091735
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.4194536127
Short name T470
Test name
Test status
Simulation time 53268898 ps
CPU time 0.9 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 196072 kb
Host smart-7fd6ead1-aee2-49f3-b0bf-b7ee7b4bbf8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194536127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.4194536127
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.715631020
Short name T556
Test name
Test status
Simulation time 66717003 ps
CPU time 0.87 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 195632 kb
Host smart-d5e34f0f-6629-442e-b0ff-8bdedf14f9e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715631020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.715631020
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.569458902
Short name T391
Test name
Test status
Simulation time 27273270 ps
CPU time 1.13 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 197492 kb
Host smart-444c5518-98ba-4fd2-b69e-63ed61389b62
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569458902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.gpio_intr_with_filter_rand_intr_event.569458902
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.4112958617
Short name T530
Test name
Test status
Simulation time 379539141 ps
CPU time 3.51 seconds
Started Jun 23 05:28:22 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 197212 kb
Host smart-3c23eedd-9aa5-4b6e-b301-4b798b737622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112958617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
4112958617
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2043739508
Short name T255
Test name
Test status
Simulation time 20231618 ps
CPU time 0.82 seconds
Started Jun 23 05:28:13 PM PDT 24
Finished Jun 23 05:28:14 PM PDT 24
Peak memory 195524 kb
Host smart-82ee9b4a-a575-4a5e-b12e-894b9bac294e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043739508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2043739508
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3769212520
Short name T443
Test name
Test status
Simulation time 259852629 ps
CPU time 1.39 seconds
Started Jun 23 05:28:22 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 197128 kb
Host smart-4c6331d7-888e-43ca-b17e-521d2ab50cf3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769212520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3769212520
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3312678982
Short name T120
Test name
Test status
Simulation time 155395768 ps
CPU time 2.3 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 198032 kb
Host smart-5af7ddb3-e51e-412d-9cc5-bcb1afee2889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312678982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3312678982
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3401441603
Short name T643
Test name
Test status
Simulation time 75778899 ps
CPU time 1.41 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 196512 kb
Host smart-a5d36f44-5ebb-400f-b53a-42fb39231ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401441603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3401441603
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2907831931
Short name T307
Test name
Test status
Simulation time 78973962 ps
CPU time 1.17 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:21 PM PDT 24
Peak memory 196772 kb
Host smart-2d0a859b-ca80-4c4f-ac93-a7a8df1c0a0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907831931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2907831931
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.397500225
Short name T149
Test name
Test status
Simulation time 4390190900 ps
CPU time 103.25 seconds
Started Jun 23 05:28:22 PM PDT 24
Finished Jun 23 05:30:07 PM PDT 24
Peak memory 198208 kb
Host smart-85af3e9c-c00a-411f-bfe0-6f1c42734a70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397500225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gp
io_stress_all.397500225
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1733898427
Short name T347
Test name
Test status
Simulation time 129947119642 ps
CPU time 881.91 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:43:10 PM PDT 24
Peak memory 206424 kb
Host smart-380787b0-3bd4-4fdf-aa86-6949534af591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1733898427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1733898427
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2365896993
Short name T40
Test name
Test status
Simulation time 11913026 ps
CPU time 0.59 seconds
Started Jun 23 05:28:25 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 193836 kb
Host smart-a3f065ac-8ca4-4e62-a0c3-3918cfed5569
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365896993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2365896993
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2724904833
Short name T18
Test name
Test status
Simulation time 121376835 ps
CPU time 0.86 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 195248 kb
Host smart-77593344-66fc-4c6b-a734-f4fca2f2de37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724904833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2724904833
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1885281314
Short name T664
Test name
Test status
Simulation time 1186319205 ps
CPU time 9.71 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 196304 kb
Host smart-32ab4c04-674d-45a8-92ed-539da5273e5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885281314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1885281314
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3455460550
Short name T227
Test name
Test status
Simulation time 547035948 ps
CPU time 0.82 seconds
Started Jun 23 05:28:21 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 195788 kb
Host smart-d3cd1969-5bb1-4e82-b4b5-c0e6fb90ea6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455460550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3455460550
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3005094493
Short name T529
Test name
Test status
Simulation time 95792015 ps
CPU time 1.35 seconds
Started Jun 23 05:28:20 PM PDT 24
Finished Jun 23 05:28:24 PM PDT 24
Peak memory 196732 kb
Host smart-062202f9-6db5-4356-8fbf-61bc44a067e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005094493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3005094493
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1541740251
Short name T407
Test name
Test status
Simulation time 179703598 ps
CPU time 1.9 seconds
Started Jun 23 05:28:21 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 196388 kb
Host smart-0ba078f5-7c5f-4825-952b-4d496a4990d0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541740251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1541740251
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.381087828
Short name T673
Test name
Test status
Simulation time 95477051 ps
CPU time 2.13 seconds
Started Jun 23 05:28:12 PM PDT 24
Finished Jun 23 05:28:15 PM PDT 24
Peak memory 196124 kb
Host smart-934f8a91-0c36-47f4-bed6-a1b50227df2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381087828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.381087828
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2309406511
Short name T500
Test name
Test status
Simulation time 15514840 ps
CPU time 0.71 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:21 PM PDT 24
Peak memory 194284 kb
Host smart-409cee92-22fb-4fa0-bac3-479b6a98dedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309406511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2309406511
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.309945409
Short name T521
Test name
Test status
Simulation time 54889651 ps
CPU time 0.74 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 195420 kb
Host smart-601d8e02-752a-48bb-b2f8-bbd2697bf61d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309945409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.309945409
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.372269473
Short name T222
Test name
Test status
Simulation time 286827834 ps
CPU time 3.58 seconds
Started Jun 23 05:28:21 PM PDT 24
Finished Jun 23 05:28:26 PM PDT 24
Peak memory 198012 kb
Host smart-811a84e8-b925-4668-9054-882bde748bc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372269473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand
om_long_reg_writes_reg_reads.372269473
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2528223607
Short name T687
Test name
Test status
Simulation time 209414946 ps
CPU time 1.15 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 195748 kb
Host smart-3047de96-9358-4e22-bc0d-73ab73906d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528223607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2528223607
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.42294912
Short name T241
Test name
Test status
Simulation time 20541224 ps
CPU time 0.82 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 196032 kb
Host smart-8e6cb415-75b6-4c3e-ad95-f2879112eb14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42294912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.42294912
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.2758800466
Short name T360
Test name
Test status
Simulation time 4997331170 ps
CPU time 29.32 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:49 PM PDT 24
Peak memory 198132 kb
Host smart-4d6f302e-d631-4849-805d-113f2115526a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758800466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.2758800466
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.2832665290
Short name T54
Test name
Test status
Simulation time 247398152171 ps
CPU time 2259.64 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 06:06:01 PM PDT 24
Peak memory 198192 kb
Host smart-3e827947-8413-4ab1-ac83-8332910e25e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2832665290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.2832665290
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.1191223637
Short name T312
Test name
Test status
Simulation time 37188081 ps
CPU time 0.58 seconds
Started Jun 23 05:28:28 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 194512 kb
Host smart-3780e704-6a2c-4334-8d98-dceb2adbbcc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191223637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.1191223637
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1049095956
Short name T261
Test name
Test status
Simulation time 57552374 ps
CPU time 0.89 seconds
Started Jun 23 05:28:19 PM PDT 24
Finished Jun 23 05:28:23 PM PDT 24
Peak memory 196280 kb
Host smart-cbf723cd-7a42-4340-951a-6973005dec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049095956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1049095956
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.673661584
Short name T268
Test name
Test status
Simulation time 163380381 ps
CPU time 8.12 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:36 PM PDT 24
Peak memory 198048 kb
Host smart-df14b136-7dd8-417c-9fe7-a2d10ca2bde8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673661584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.673661584
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2052906040
Short name T637
Test name
Test status
Simulation time 107981228 ps
CPU time 0.74 seconds
Started Jun 23 05:28:26 PM PDT 24
Finished Jun 23 05:28:28 PM PDT 24
Peak memory 194624 kb
Host smart-b18fec26-997e-44bd-a0c5-499a1f9656af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052906040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2052906040
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.75840753
Short name T201
Test name
Test status
Simulation time 31036657 ps
CPU time 0.77 seconds
Started Jun 23 05:28:23 PM PDT 24
Finished Jun 23 05:28:25 PM PDT 24
Peak memory 194372 kb
Host smart-93a6ed05-7cb4-4666-adad-83f37421fdaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75840753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.75840753
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2684803063
Short name T262
Test name
Test status
Simulation time 348160396 ps
CPU time 3.62 seconds
Started Jun 23 05:28:21 PM PDT 24
Finished Jun 23 05:28:27 PM PDT 24
Peak memory 198152 kb
Host smart-0e5ff79f-e07b-4323-bddd-b9e597c9d848
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684803063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2684803063
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.421434390
Short name T607
Test name
Test status
Simulation time 109461803 ps
CPU time 1.03 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 195668 kb
Host smart-63ad1235-f197-400d-b219-e34d1f055dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421434390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.421434390
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.132774833
Short name T694
Test name
Test status
Simulation time 209400265 ps
CPU time 0.93 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 195852 kb
Host smart-9674c263-fa71-4215-9675-99af372b73ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132774833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.132774833
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.1315782082
Short name T574
Test name
Test status
Simulation time 149938362 ps
CPU time 1.05 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:28:30 PM PDT 24
Peak memory 195936 kb
Host smart-ea27a529-03bc-4aef-9a05-076a64aeb2e8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315782082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.1315782082
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.300181224
Short name T639
Test name
Test status
Simulation time 834160650 ps
CPU time 4.27 seconds
Started Jun 23 05:28:23 PM PDT 24
Finished Jun 23 05:28:29 PM PDT 24
Peak memory 198028 kb
Host smart-32e04176-ab44-4627-94ed-4336a1a0217a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300181224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.300181224
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1683253805
Short name T412
Test name
Test status
Simulation time 48519996 ps
CPU time 0.85 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 196032 kb
Host smart-39263f61-da19-484e-be70-f2aff1775d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683253805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1683253805
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1218366831
Short name T411
Test name
Test status
Simulation time 101204954 ps
CPU time 1.02 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 05:28:22 PM PDT 24
Peak memory 196380 kb
Host smart-4ec6e3be-bbd1-43cd-a1fb-7c561fb60da1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218366831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1218366831
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3099079309
Short name T171
Test name
Test status
Simulation time 44292012763 ps
CPU time 146.03 seconds
Started Jun 23 05:28:18 PM PDT 24
Finished Jun 23 05:30:47 PM PDT 24
Peak memory 198056 kb
Host smart-ea9c0345-f707-4cf4-af0b-f68fd026ca34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099079309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3099079309
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2850044288
Short name T515
Test name
Test status
Simulation time 85069477229 ps
CPU time 630.12 seconds
Started Jun 23 05:28:27 PM PDT 24
Finished Jun 23 05:38:59 PM PDT 24
Peak memory 198392 kb
Host smart-54d54a19-40c8-45fa-9473-5588d6fc9df9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2850044288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2850044288
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2509516270
Short name T892
Test name
Test status
Simulation time 33736684 ps
CPU time 0.98 seconds
Started Jun 23 05:27:56 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 196356 kb
Host smart-58ebb9dc-4bd7-42b6-9db8-b4040265ca9d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2509516270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2509516270
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1217969297
Short name T871
Test name
Test status
Simulation time 103333725 ps
CPU time 1.56 seconds
Started Jun 23 05:27:50 PM PDT 24
Finished Jun 23 05:27:52 PM PDT 24
Peak memory 196732 kb
Host smart-3de8e4c6-c365-48bd-8c3f-73cc8a8447ea
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217969297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1217969297
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2520568961
Short name T856
Test name
Test status
Simulation time 33056285 ps
CPU time 1.15 seconds
Started Jun 23 05:27:56 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 196208 kb
Host smart-a5ec791d-80b5-4a29-8a90-a6c8fd68cbcb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2520568961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2520568961
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3520134116
Short name T854
Test name
Test status
Simulation time 95785382 ps
CPU time 1.65 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196484 kb
Host smart-cb3148e2-ac27-465a-b654-88c7f3d9099d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520134116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3520134116
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1442020026
Short name T916
Test name
Test status
Simulation time 108034944 ps
CPU time 0.99 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:53 PM PDT 24
Peak memory 197876 kb
Host smart-7719d0c0-a754-4392-a307-7e63a263c0c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1442020026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1442020026
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3354396214
Short name T862
Test name
Test status
Simulation time 59195564 ps
CPU time 1.12 seconds
Started Jun 23 05:27:57 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 195700 kb
Host smart-f65ed07e-e428-4c91-87f0-b1652bc86f5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354396214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3354396214
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.3855449633
Short name T917
Test name
Test status
Simulation time 303541235 ps
CPU time 1.22 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:53 PM PDT 24
Peak memory 196508 kb
Host smart-b1f70b00-a424-4acd-9646-311396c4ea63
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3855449633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.3855449633
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.198175723
Short name T890
Test name
Test status
Simulation time 506597959 ps
CPU time 1.47 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:51 PM PDT 24
Peak memory 196416 kb
Host smart-f3a3e631-5895-49fa-b827-503526638c87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198175723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.198175723
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.738026548
Short name T943
Test name
Test status
Simulation time 71068300 ps
CPU time 0.74 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:50 PM PDT 24
Peak memory 196028 kb
Host smart-a5fde6e5-fd39-4a67-8a0b-fa3c5cbb2e91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=738026548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.738026548
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1642646542
Short name T865
Test name
Test status
Simulation time 87945945 ps
CPU time 1.33 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196188 kb
Host smart-cb98e027-e728-463c-9cf5-116b0d38bdf0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642646542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1642646542
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.81555940
Short name T936
Test name
Test status
Simulation time 32635229 ps
CPU time 1.18 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:55 PM PDT 24
Peak memory 197232 kb
Host smart-d69d23d5-1d52-449d-bd04-d277db98bc15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=81555940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.81555940
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1550096185
Short name T919
Test name
Test status
Simulation time 74638559 ps
CPU time 1.28 seconds
Started Jun 23 05:27:55 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 197860 kb
Host smart-0ab76b22-8fdb-4304-b4bd-2e4a8b001908
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550096185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1550096185
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2310976953
Short name T846
Test name
Test status
Simulation time 307174157 ps
CPU time 1.48 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196476 kb
Host smart-32f8b1af-1359-48d6-97a4-fb492ca7f211
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2310976953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2310976953
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1949171403
Short name T876
Test name
Test status
Simulation time 347449959 ps
CPU time 1.25 seconds
Started Jun 23 05:27:55 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 195600 kb
Host smart-15b583ae-460f-46f5-b0e3-a7a2ca1b0441
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949171403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1949171403
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2623832666
Short name T903
Test name
Test status
Simulation time 109054560 ps
CPU time 1.06 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:54 PM PDT 24
Peak memory 196564 kb
Host smart-1bc58975-08d9-497b-98d5-009cf3a6bfd8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2623832666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2623832666
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1489983299
Short name T925
Test name
Test status
Simulation time 135605917 ps
CPU time 1.31 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 197848 kb
Host smart-533ea73b-1af7-458f-a50b-1ffa73b0f775
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489983299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1489983299
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.1510210457
Short name T898
Test name
Test status
Simulation time 273965728 ps
CPU time 1.12 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196756 kb
Host smart-7353b8e3-12b2-4cc7-b50d-7c2028aa1c30
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1510210457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.1510210457
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.675315401
Short name T885
Test name
Test status
Simulation time 108810528 ps
CPU time 0.81 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:53 PM PDT 24
Peak memory 194312 kb
Host smart-886886ca-06fc-4932-aa55-99f6a5770d06
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675315401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.675315401
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.307517390
Short name T929
Test name
Test status
Simulation time 169114000 ps
CPU time 1.29 seconds
Started Jun 23 05:27:55 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 197876 kb
Host smart-e902958a-fba8-4b77-8a8e-bee92135d1c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=307517390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.307517390
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.440833149
Short name T941
Test name
Test status
Simulation time 32569591 ps
CPU time 1.02 seconds
Started Jun 23 05:27:53 PM PDT 24
Finished Jun 23 05:27:54 PM PDT 24
Peak memory 196328 kb
Host smart-e3cad059-8e1f-455a-bcfe-24bb986a6dc6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440833149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.440833149
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1778669746
Short name T893
Test name
Test status
Simulation time 27356181 ps
CPU time 0.82 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:54 PM PDT 24
Peak memory 195404 kb
Host smart-c981567b-9980-4893-9f53-db7f4f3b7b0c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1778669746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1778669746
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2780722834
Short name T859
Test name
Test status
Simulation time 200622534 ps
CPU time 1.1 seconds
Started Jun 23 05:27:57 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 197748 kb
Host smart-b304f7c2-ed39-4951-b533-9584ac28243d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780722834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2780722834
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1614794579
Short name T915
Test name
Test status
Simulation time 21592126 ps
CPU time 0.76 seconds
Started Jun 23 05:27:56 PM PDT 24
Finished Jun 23 05:27:57 PM PDT 24
Peak memory 195020 kb
Host smart-c1527b2f-f000-401a-9fe6-05d2a074274b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1614794579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1614794579
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.170075043
Short name T922
Test name
Test status
Simulation time 108347247 ps
CPU time 1.36 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:54 PM PDT 24
Peak memory 196428 kb
Host smart-925bd8b5-763c-49ba-9512-f7199a198ad3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170075043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.170075043
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.2435451671
Short name T905
Test name
Test status
Simulation time 162553966 ps
CPU time 1 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:51 PM PDT 24
Peak memory 195264 kb
Host smart-554e8a0a-9305-49ce-b9ac-235f136a262e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2435451671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.2435451671
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3637266914
Short name T895
Test name
Test status
Simulation time 327242046 ps
CPU time 1.32 seconds
Started Jun 23 05:27:50 PM PDT 24
Finished Jun 23 05:27:52 PM PDT 24
Peak memory 196852 kb
Host smart-24265e47-8903-4e9e-8c8f-779e659d2440
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637266914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3637266914
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3323837423
Short name T855
Test name
Test status
Simulation time 106625654 ps
CPU time 1.06 seconds
Started Jun 23 05:27:53 PM PDT 24
Finished Jun 23 05:27:55 PM PDT 24
Peak memory 196424 kb
Host smart-40a97445-ba18-4ba9-aded-2925e3fb0973
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3323837423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3323837423
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3882813825
Short name T886
Test name
Test status
Simulation time 63352231 ps
CPU time 1.25 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:54 PM PDT 24
Peak memory 195828 kb
Host smart-88eabb76-3a7d-4aaa-931f-4ababe1ec2a4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882813825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3882813825
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1431817393
Short name T932
Test name
Test status
Simulation time 264456673 ps
CPU time 1.37 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196672 kb
Host smart-a2423ac1-582e-4aa8-9fea-84993a8cfc82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1431817393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1431817393
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3116107203
Short name T870
Test name
Test status
Simulation time 237337949 ps
CPU time 1.35 seconds
Started Jun 23 05:27:53 PM PDT 24
Finished Jun 23 05:27:55 PM PDT 24
Peak memory 196708 kb
Host smart-604ef877-923a-4af6-8a7a-318bd52ae71d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116107203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3116107203
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1232298068
Short name T924
Test name
Test status
Simulation time 196560547 ps
CPU time 1.06 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:54 PM PDT 24
Peak memory 195872 kb
Host smart-83eebf87-8650-4282-95af-43e7b5c1bfe1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1232298068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1232298068
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.68520360
Short name T881
Test name
Test status
Simulation time 190653836 ps
CPU time 1.19 seconds
Started Jun 23 05:27:52 PM PDT 24
Finished Jun 23 05:27:54 PM PDT 24
Peak memory 196420 kb
Host smart-36707dd8-34a2-4680-be6c-13bffa778ee7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68520360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.68520360
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1782815100
Short name T874
Test name
Test status
Simulation time 46428661 ps
CPU time 0.82 seconds
Started Jun 23 05:27:57 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 195248 kb
Host smart-b8396260-9940-4be2-8c04-fce6455ab4fe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1782815100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1782815100
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3545233315
Short name T873
Test name
Test status
Simulation time 102759735 ps
CPU time 0.89 seconds
Started Jun 23 05:27:55 PM PDT 24
Finished Jun 23 05:27:57 PM PDT 24
Peak memory 196348 kb
Host smart-9496e09a-224f-430a-9c76-b26e4a64a348
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545233315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3545233315
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.564128402
Short name T847
Test name
Test status
Simulation time 45510166 ps
CPU time 1.16 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196524 kb
Host smart-30d01bdb-ddfb-4db9-abb9-7ce572cf25de
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=564128402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.564128402
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.360180188
Short name T914
Test name
Test status
Simulation time 438864500 ps
CPU time 1.23 seconds
Started Jun 23 05:27:58 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 195564 kb
Host smart-391950c5-d809-440b-b234-ae08f62ed3ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360180188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.360180188
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.174541808
Short name T933
Test name
Test status
Simulation time 63197131 ps
CPU time 1.15 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:02 PM PDT 24
Peak memory 196400 kb
Host smart-ede63bcd-88e6-4b46-b2e9-c91c6d1773d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=174541808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.174541808
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.526780431
Short name T923
Test name
Test status
Simulation time 91666041 ps
CPU time 1.06 seconds
Started Jun 23 05:28:01 PM PDT 24
Finished Jun 23 05:28:03 PM PDT 24
Peak memory 195760 kb
Host smart-4d2f5abf-029d-4908-aa02-fde4d25d1db4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526780431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.526780431
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1207754655
Short name T918
Test name
Test status
Simulation time 44712315 ps
CPU time 0.97 seconds
Started Jun 23 05:27:58 PM PDT 24
Finished Jun 23 05:27:59 PM PDT 24
Peak memory 195612 kb
Host smart-7e5534c2-6e4c-48e4-9cd5-e8be54c28e32
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1207754655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1207754655
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1739764536
Short name T894
Test name
Test status
Simulation time 102796959 ps
CPU time 1.44 seconds
Started Jun 23 05:27:58 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 196692 kb
Host smart-3a069ca3-daa5-44e5-bc46-b8665e6c409f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739764536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1739764536
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2320184678
Short name T849
Test name
Test status
Simulation time 91720261 ps
CPU time 1.51 seconds
Started Jun 23 05:27:59 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 196820 kb
Host smart-c79351af-4bf5-40f5-96a3-503961454d4f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2320184678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2320184678
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2522424502
Short name T868
Test name
Test status
Simulation time 28611373 ps
CPU time 0.86 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 195452 kb
Host smart-ff11756b-1502-466e-a1cb-aea9997f8fee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522424502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2522424502
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2477174424
Short name T940
Test name
Test status
Simulation time 43114415 ps
CPU time 1.04 seconds
Started Jun 23 05:27:57 PM PDT 24
Finished Jun 23 05:27:59 PM PDT 24
Peak memory 196692 kb
Host smart-e6e4571f-cf0f-41dc-aa72-d0468adf442f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2477174424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2477174424
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4185024534
Short name T926
Test name
Test status
Simulation time 153394286 ps
CPU time 1.7 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:03 PM PDT 24
Peak memory 196848 kb
Host smart-74cb0267-4e57-412d-82ae-78a77a2755e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185024534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4185024534
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.1417753292
Short name T864
Test name
Test status
Simulation time 285231895 ps
CPU time 1.17 seconds
Started Jun 23 05:27:59 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 197904 kb
Host smart-f8b1e89e-df04-4dc6-bf3d-a51046ae6b1e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1417753292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.1417753292
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3833792561
Short name T863
Test name
Test status
Simulation time 86828724 ps
CPU time 0.85 seconds
Started Jun 23 05:27:58 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 197296 kb
Host smart-fef6ff95-1d2c-43bf-9d0c-9d75e196df37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833792561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3833792561
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.163472679
Short name T910
Test name
Test status
Simulation time 56029372 ps
CPU time 0.95 seconds
Started Jun 23 05:27:56 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 197696 kb
Host smart-983de599-9191-42cb-9cab-6b7524507e6b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=163472679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.163472679
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.488642363
Short name T884
Test name
Test status
Simulation time 276203471 ps
CPU time 1.39 seconds
Started Jun 23 05:27:48 PM PDT 24
Finished Jun 23 05:27:50 PM PDT 24
Peak memory 197244 kb
Host smart-3bda1745-d27a-448a-ad6a-0761b6cb4b5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488642363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.488642363
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1261651131
Short name T867
Test name
Test status
Simulation time 93447438 ps
CPU time 1.69 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:03 PM PDT 24
Peak memory 197888 kb
Host smart-de614455-9e4b-4c2c-8f34-09f2bd609048
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1261651131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1261651131
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2274021344
Short name T930
Test name
Test status
Simulation time 182580984 ps
CPU time 1.16 seconds
Started Jun 23 05:27:57 PM PDT 24
Finished Jun 23 05:27:59 PM PDT 24
Peak memory 195736 kb
Host smart-6f3c6a5c-2ff0-4f9c-babd-1f928e5f6345
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274021344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2274021344
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2606168350
Short name T851
Test name
Test status
Simulation time 56667840 ps
CPU time 1.15 seconds
Started Jun 23 05:28:01 PM PDT 24
Finished Jun 23 05:28:03 PM PDT 24
Peak memory 197352 kb
Host smart-531b3c49-652f-40f3-b101-765b84cd768e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2606168350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2606168350
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4062384077
Short name T882
Test name
Test status
Simulation time 39171257 ps
CPU time 1.17 seconds
Started Jun 23 05:27:58 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 196388 kb
Host smart-3ed9f468-3b01-41fb-83f7-29141687bd68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062384077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4062384077
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1589914373
Short name T908
Test name
Test status
Simulation time 76309019 ps
CPU time 1.21 seconds
Started Jun 23 05:27:58 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 197900 kb
Host smart-15750928-e154-4647-bcc5-18cdc40c911f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1589914373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1589914373
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3509061690
Short name T872
Test name
Test status
Simulation time 276362517 ps
CPU time 1.4 seconds
Started Jun 23 05:28:01 PM PDT 24
Finished Jun 23 05:28:03 PM PDT 24
Peak memory 197884 kb
Host smart-b3f02945-23ce-4922-b8cc-c90ddebabadf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509061690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3509061690
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.4050216603
Short name T878
Test name
Test status
Simulation time 159981007 ps
CPU time 1.15 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 195824 kb
Host smart-4104bd85-692d-4bcd-b567-62b0833d787f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4050216603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.4050216603
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2488744654
Short name T866
Test name
Test status
Simulation time 183834175 ps
CPU time 1.29 seconds
Started Jun 23 05:28:02 PM PDT 24
Finished Jun 23 05:28:03 PM PDT 24
Peak memory 197892 kb
Host smart-f2fdaeac-d833-4550-8443-e689e346530c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488744654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2488744654
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.2042493932
Short name T889
Test name
Test status
Simulation time 218795143 ps
CPU time 1.28 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:02 PM PDT 24
Peak memory 196540 kb
Host smart-36a5742d-f771-4947-80f4-9644b9eecdbf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2042493932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.2042493932
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3280865511
Short name T927
Test name
Test status
Simulation time 425387215 ps
CPU time 1.02 seconds
Started Jun 23 05:27:57 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 196492 kb
Host smart-03cb9021-f9f9-4617-9dea-035e683e96a1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280865511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3280865511
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2260561390
Short name T880
Test name
Test status
Simulation time 64216602 ps
CPU time 1.23 seconds
Started Jun 23 05:28:03 PM PDT 24
Finished Jun 23 05:28:04 PM PDT 24
Peak memory 196996 kb
Host smart-2a44417b-13ba-4a6d-8d61-ef11ad3f35d6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2260561390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2260561390
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2700193099
Short name T939
Test name
Test status
Simulation time 77876588 ps
CPU time 1.31 seconds
Started Jun 23 05:27:59 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 197912 kb
Host smart-f5150a99-ee46-4db8-808e-2c0ef6232b67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700193099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2700193099
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.1192231967
Short name T877
Test name
Test status
Simulation time 117359982 ps
CPU time 0.96 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 195360 kb
Host smart-df104404-b841-485a-bef1-34f97bbf5e16
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1192231967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.1192231967
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4100029681
Short name T906
Test name
Test status
Simulation time 86913082 ps
CPU time 1.03 seconds
Started Jun 23 05:28:00 PM PDT 24
Finished Jun 23 05:28:02 PM PDT 24
Peak memory 196352 kb
Host smart-b55a3009-01fb-4add-9163-76e17111ee01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100029681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4100029681
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.3116091131
Short name T891
Test name
Test status
Simulation time 28046318 ps
CPU time 0.81 seconds
Started Jun 23 05:27:59 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 195196 kb
Host smart-bbdfbeee-ec11-482b-b73a-92b923b7a5bf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3116091131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.3116091131
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3713931516
Short name T875
Test name
Test status
Simulation time 86501473 ps
CPU time 0.86 seconds
Started Jun 23 05:27:59 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 196348 kb
Host smart-d19eaa4f-0376-4a8c-beda-75f2bf9d1e39
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713931516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3713931516
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.4097061941
Short name T853
Test name
Test status
Simulation time 565892165 ps
CPU time 1.04 seconds
Started Jun 23 05:27:59 PM PDT 24
Finished Jun 23 05:28:01 PM PDT 24
Peak memory 196372 kb
Host smart-ef079ea7-c854-45a7-adea-d4281aaee706
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4097061941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.4097061941
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2104890625
Short name T896
Test name
Test status
Simulation time 68588638 ps
CPU time 1.2 seconds
Started Jun 23 05:27:58 PM PDT 24
Finished Jun 23 05:28:00 PM PDT 24
Peak memory 197820 kb
Host smart-09f59afd-22e8-4eb6-b717-a3d58928bf61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104890625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2104890625
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1247085399
Short name T944
Test name
Test status
Simulation time 24163558 ps
CPU time 0.82 seconds
Started Jun 23 05:28:01 PM PDT 24
Finished Jun 23 05:28:03 PM PDT 24
Peak memory 195388 kb
Host smart-83c4f7e2-a857-4127-b7fb-eade2d98b031
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1247085399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1247085399
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.465977418
Short name T861
Test name
Test status
Simulation time 68198318 ps
CPU time 1.24 seconds
Started Jun 23 05:28:05 PM PDT 24
Finished Jun 23 05:28:07 PM PDT 24
Peak memory 196308 kb
Host smart-b8440ebb-15d2-4d40-a26b-d6673f924be4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465977418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.465977418
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.89521900
Short name T897
Test name
Test status
Simulation time 1258578324 ps
CPU time 1.18 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 196536 kb
Host smart-6c87876e-599d-4a52-921e-15e073eb244c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=89521900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.89521900
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3018681516
Short name T913
Test name
Test status
Simulation time 474419023 ps
CPU time 1.4 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:51 PM PDT 24
Peak memory 196432 kb
Host smart-2d429e5d-6250-4879-8c97-60a225d4cc9a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018681516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3018681516
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.2768508156
Short name T900
Test name
Test status
Simulation time 88480305 ps
CPU time 0.91 seconds
Started Jun 23 05:28:06 PM PDT 24
Finished Jun 23 05:28:08 PM PDT 24
Peak memory 195448 kb
Host smart-1df9ae35-779c-4234-999a-fd02a335e757
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2768508156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.2768508156
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.448965680
Short name T912
Test name
Test status
Simulation time 42078136 ps
CPU time 1.31 seconds
Started Jun 23 05:28:07 PM PDT 24
Finished Jun 23 05:28:09 PM PDT 24
Peak memory 197800 kb
Host smart-99e1e6d7-51e6-4ed3-86ac-9ffa887336c9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448965680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.448965680
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3569767648
Short name T887
Test name
Test status
Simulation time 38905434 ps
CPU time 1.09 seconds
Started Jun 23 05:28:08 PM PDT 24
Finished Jun 23 05:28:09 PM PDT 24
Peak memory 195788 kb
Host smart-eebbcce2-c5fb-4cb8-9e3e-56621ab75bd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3569767648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3569767648
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2099093460
Short name T888
Test name
Test status
Simulation time 392679406 ps
CPU time 1.49 seconds
Started Jun 23 05:28:03 PM PDT 24
Finished Jun 23 05:28:04 PM PDT 24
Peak memory 196592 kb
Host smart-42aaf0ec-fdf2-4b19-8c3a-0b4944f161dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099093460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2099093460
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.72498078
Short name T902
Test name
Test status
Simulation time 90282143 ps
CPU time 1.34 seconds
Started Jun 23 05:28:05 PM PDT 24
Finished Jun 23 05:28:07 PM PDT 24
Peak memory 196752 kb
Host smart-41bdcbe1-3ebb-483a-9771-1370f55a81b7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=72498078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.72498078
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.466574272
Short name T904
Test name
Test status
Simulation time 282781686 ps
CPU time 0.85 seconds
Started Jun 23 05:28:03 PM PDT 24
Finished Jun 23 05:28:04 PM PDT 24
Peak memory 196496 kb
Host smart-43681ac3-4e0a-45b3-861a-d68cb3376958
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466574272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.466574272
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3946236392
Short name T858
Test name
Test status
Simulation time 229495065 ps
CPU time 1.36 seconds
Started Jun 23 05:28:08 PM PDT 24
Finished Jun 23 05:28:10 PM PDT 24
Peak memory 196740 kb
Host smart-82bcf18b-d329-486a-bcaf-1c04dc72dd28
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3946236392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3946236392
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2477769625
Short name T909
Test name
Test status
Simulation time 205739607 ps
CPU time 1.06 seconds
Started Jun 23 05:28:17 PM PDT 24
Finished Jun 23 05:28:21 PM PDT 24
Peak memory 196232 kb
Host smart-32b565b6-f1ec-4efb-a677-502356d9cfc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477769625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2477769625
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3955133056
Short name T860
Test name
Test status
Simulation time 49704673 ps
CPU time 1.2 seconds
Started Jun 23 05:28:08 PM PDT 24
Finished Jun 23 05:28:10 PM PDT 24
Peak memory 197428 kb
Host smart-b45aeb44-28e4-423d-9b5d-ce231447ba47
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3955133056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3955133056
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.754633349
Short name T845
Test name
Test status
Simulation time 79610868 ps
CPU time 1.13 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:17 PM PDT 24
Peak memory 195520 kb
Host smart-4bdb1033-bf20-4243-80f4-e595d6b9b2f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754633349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.754633349
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.3051317117
Short name T899
Test name
Test status
Simulation time 30301806 ps
CPU time 0.91 seconds
Started Jun 23 05:28:06 PM PDT 24
Finished Jun 23 05:28:07 PM PDT 24
Peak memory 196300 kb
Host smart-1338cfe0-8b6e-47f5-9880-5775bf8ae68a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3051317117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.3051317117
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.571616316
Short name T934
Test name
Test status
Simulation time 72221091 ps
CPU time 1.07 seconds
Started Jun 23 05:28:13 PM PDT 24
Finished Jun 23 05:28:14 PM PDT 24
Peak memory 195516 kb
Host smart-45863e63-a6b0-463e-b3aa-c77b1d861eb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571616316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.571616316
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1350908343
Short name T920
Test name
Test status
Simulation time 242114550 ps
CPU time 1.19 seconds
Started Jun 23 05:28:04 PM PDT 24
Finished Jun 23 05:28:05 PM PDT 24
Peak memory 196564 kb
Host smart-ea34c795-ea3f-4af7-9f1d-c4cfafb417f3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1350908343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1350908343
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.44452934
Short name T869
Test name
Test status
Simulation time 71838272 ps
CPU time 1.48 seconds
Started Jun 23 05:28:04 PM PDT 24
Finished Jun 23 05:28:06 PM PDT 24
Peak memory 197872 kb
Host smart-d87f58bf-f3c0-4816-89b7-4c20f29f938b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44452934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.44452934
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.1300779009
Short name T883
Test name
Test status
Simulation time 76938217 ps
CPU time 1.29 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:19 PM PDT 24
Peak memory 196876 kb
Host smart-6c1de3dd-13aa-4231-a5ff-be46665815a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1300779009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.1300779009
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1046889168
Short name T937
Test name
Test status
Simulation time 78752016 ps
CPU time 0.96 seconds
Started Jun 23 05:28:14 PM PDT 24
Finished Jun 23 05:28:15 PM PDT 24
Peak memory 197840 kb
Host smart-6e690f78-d9c3-4416-a1cd-e290ae8a30b7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046889168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1046889168
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4260552062
Short name T935
Test name
Test status
Simulation time 28084880 ps
CPU time 0.93 seconds
Started Jun 23 05:28:04 PM PDT 24
Finished Jun 23 05:28:05 PM PDT 24
Peak memory 195268 kb
Host smart-7abdf535-03b0-4725-9aa4-7abe6f0d8d68
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4260552062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4260552062
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2897132784
Short name T931
Test name
Test status
Simulation time 77443581 ps
CPU time 1.31 seconds
Started Jun 23 05:28:15 PM PDT 24
Finished Jun 23 05:28:18 PM PDT 24
Peak memory 195532 kb
Host smart-64319c0b-12e3-46ce-9176-3343127d5308
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897132784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2897132784
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3998020744
Short name T901
Test name
Test status
Simulation time 75059009 ps
CPU time 1.24 seconds
Started Jun 23 05:28:06 PM PDT 24
Finished Jun 23 05:28:08 PM PDT 24
Peak memory 196408 kb
Host smart-1d7203da-e29c-4417-8330-b5eddadd4399
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3998020744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3998020744
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3341582863
Short name T850
Test name
Test status
Simulation time 45225148 ps
CPU time 1.2 seconds
Started Jun 23 05:28:16 PM PDT 24
Finished Jun 23 05:28:20 PM PDT 24
Peak memory 196428 kb
Host smart-42ccad4d-c148-49cd-820b-db043a954b51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341582863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3341582863
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3170917991
Short name T938
Test name
Test status
Simulation time 34737795 ps
CPU time 0.74 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:53 PM PDT 24
Peak memory 195292 kb
Host smart-4ffa2fce-b23f-45b9-9c33-b3ec085e88df
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3170917991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3170917991
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.35330966
Short name T857
Test name
Test status
Simulation time 144832486 ps
CPU time 1.33 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196564 kb
Host smart-1c82b65a-64a4-4149-a74f-3baa8bbb65e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35330966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.35330966
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3657774853
Short name T852
Test name
Test status
Simulation time 174287364 ps
CPU time 1.37 seconds
Started Jun 23 05:27:48 PM PDT 24
Finished Jun 23 05:27:50 PM PDT 24
Peak memory 195708 kb
Host smart-e2519915-829d-49ea-aca7-fbf6214f8e97
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3657774853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3657774853
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2842784251
Short name T928
Test name
Test status
Simulation time 41353188 ps
CPU time 1.04 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:53 PM PDT 24
Peak memory 196516 kb
Host smart-7a7ef115-aa52-4701-af33-d657e56bab4b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842784251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2842784251
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.1103860320
Short name T942
Test name
Test status
Simulation time 252701949 ps
CPU time 1.32 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:51 PM PDT 24
Peak memory 196784 kb
Host smart-330f7a19-8eaf-4582-bd4e-d28eb2d7652d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103860320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.1103860320
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2304342033
Short name T911
Test name
Test status
Simulation time 101889399 ps
CPU time 1.3 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:51 PM PDT 24
Peak memory 196496 kb
Host smart-b958c415-3b23-4899-88de-578c3cfc4d5f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304342033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2304342033
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2547949578
Short name T879
Test name
Test status
Simulation time 97961332 ps
CPU time 1.59 seconds
Started Jun 23 05:27:54 PM PDT 24
Finished Jun 23 05:27:56 PM PDT 24
Peak memory 196604 kb
Host smart-5c0bcb08-dcff-40bc-b15b-0941add289af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2547949578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2547949578
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3939604707
Short name T921
Test name
Test status
Simulation time 114867791 ps
CPU time 0.88 seconds
Started Jun 23 05:27:49 PM PDT 24
Finished Jun 23 05:27:50 PM PDT 24
Peak memory 195488 kb
Host smart-906f180f-337b-4aa0-b85a-e429b42a213c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939604707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3939604707
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2401489771
Short name T848
Test name
Test status
Simulation time 365324528 ps
CPU time 1.6 seconds
Started Jun 23 05:27:51 PM PDT 24
Finished Jun 23 05:27:53 PM PDT 24
Peak memory 196720 kb
Host smart-169a071d-8545-4a05-8eb9-4854d91185d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2401489771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2401489771
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.653956040
Short name T907
Test name
Test status
Simulation time 178002257 ps
CPU time 1.26 seconds
Started Jun 23 05:27:56 PM PDT 24
Finished Jun 23 05:27:58 PM PDT 24
Peak memory 196220 kb
Host smart-5cb13dc7-6a62-4124-8b09-088726da43cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653956040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.653956040
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%