Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4162452	1			T22	1		T23	159		T24	1
all_pins[1]	4162452	1			T22	1		T23	159		T24	1
all_pins[2]	4162452	1			T22	1		T23	159		T24	1
all_pins[3]	4162452	1			T22	1		T23	159		T24	1
all_pins[4]	4162452	1			T22	1		T23	159		T24	1
all_pins[5]	4162452	1			T22	1		T23	159		T24	1
all_pins[6]	4162452	1			T22	1		T23	159		T24	1
all_pins[7]	4162452	1			T22	1		T23	159		T24	1
all_pins[8]	4162452	1			T22	1		T23	159		T24	1
all_pins[9]	4162452	1			T22	1		T23	159		T24	1
all_pins[10]	4162452	1			T22	1		T23	159		T24	1
all_pins[11]	4162452	1			T22	1		T23	159		T24	1
all_pins[12]	4162452	1			T22	1		T23	159		T24	1
all_pins[13]	4162452	1			T22	1		T23	159		T24	1
all_pins[14]	4162452	1			T22	1		T23	159		T24	1
all_pins[15]	4162452	1			T22	1		T23	159		T24	1
all_pins[16]	4162452	1			T22	1		T23	159		T24	1
all_pins[17]	4162452	1			T22	1		T23	159		T24	1
all_pins[18]	4162452	1			T22	1		T23	159		T24	1
all_pins[19]	4162452	1			T22	1		T23	159		T24	1
all_pins[20]	4162452	1			T22	1		T23	159		T24	1
all_pins[21]	4162452	1			T22	1		T23	159		T24	1
all_pins[22]	4162452	1			T22	1		T23	159		T24	1
all_pins[23]	4162452	1			T22	1		T23	159		T24	1
all_pins[24]	4162452	1			T22	1		T23	159		T24	1
all_pins[25]	4162452	1			T22	1		T23	159		T24	1
all_pins[26]	4162452	1			T22	1		T23	159		T24	1
all_pins[27]	4162452	1			T22	1		T23	159		T24	1
all_pins[28]	4162452	1			T22	1		T23	159		T24	1
all_pins[29]	4162452	1			T22	1		T23	159		T24	1
all_pins[30]	4162452	1			T22	1		T23	159		T24	1
all_pins[31]	4162452	1			T22	1		T23	159		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	82745608	1			T22	32		T23	3246		T24	32
values[0x1]	50452856	1			T23	1842		T27	1465		T29	1233
transitions[0x0=>0x1]	30233644	1			T23	1151		T27	870		T29	767
transitions[0x1=>0x0]	30233502	1			T23	1150		T27	869		T29	766

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2581599	1			T22	1		T23	97		T24	1
all_pins[0]	values[0x1]	1580853	1			T23	62		T27	49		T29	10
all_pins[0]	transitions[0x0=>0x1]	981412	1			T23	49		T27	29		T29	1
all_pins[0]	transitions[0x1=>0x0]	974621	1			T23	35		T27	30		T29	37
all_pins[1]	values[0x0]	2582561	1			T22	1		T23	93		T24	1
all_pins[1]	values[0x1]	1579891	1			T23	66		T27	31		T29	56
all_pins[1]	transitions[0x0=>0x1]	942414	1			T23	45		T27	14		T29	51
all_pins[1]	transitions[0x1=>0x0]	943376	1			T23	41		T27	32		T29	5
all_pins[2]	values[0x0]	2587890	1			T22	1		T23	84		T24	1
all_pins[2]	values[0x1]	1574562	1			T23	75		T27	38		T29	16
all_pins[2]	transitions[0x0=>0x1]	941497	1			T23	38		T27	26		T29	5
all_pins[2]	transitions[0x1=>0x0]	946826	1			T23	29		T27	19		T29	45
all_pins[3]	values[0x0]	2581762	1			T22	1		T23	126		T24	1
all_pins[3]	values[0x1]	1580690	1			T23	33		T27	54		T29	44
all_pins[3]	transitions[0x0=>0x1]	947408	1			T23	7		T27	36		T29	44
all_pins[3]	transitions[0x1=>0x0]	941280	1			T23	49		T27	20		T29	16
all_pins[4]	values[0x0]	2592107	1			T22	1		T23	104		T24	1
all_pins[4]	values[0x1]	1570345	1			T23	55		T27	38		T29	26
all_pins[4]	transitions[0x0=>0x1]	937932	1			T23	40		T27	12		T29	16
all_pins[4]	transitions[0x1=>0x0]	948277	1			T23	18		T27	28		T29	34
all_pins[5]	values[0x0]	2582192	1			T22	1		T23	92		T24	1
all_pins[5]	values[0x1]	1580260	1			T23	67		T27	28		T29	42
all_pins[5]	transitions[0x0=>0x1]	948668	1			T23	39		T27	21		T29	34
all_pins[5]	transitions[0x1=>0x0]	938753	1			T23	27		T27	31		T29	18
all_pins[6]	values[0x0]	2583445	1			T22	1		T23	109		T24	1
all_pins[6]	values[0x1]	1579007	1			T23	50		T27	59		T29	25
all_pins[6]	transitions[0x0=>0x1]	944199	1			T23	33		T27	40		T29	17
all_pins[6]	transitions[0x1=>0x0]	945452	1			T23	50		T27	9		T29	34
all_pins[7]	values[0x0]	2586853	1			T22	1		T23	71		T24	1
all_pins[7]	values[0x1]	1575599	1			T23	88		T27	46		T29	59
all_pins[7]	transitions[0x0=>0x1]	941106	1			T23	58		T27	22		T29	40
all_pins[7]	transitions[0x1=>0x0]	944514	1			T23	20		T27	35		T29	6
all_pins[8]	values[0x0]	2585137	1			T22	1		T23	86		T24	1
all_pins[8]	values[0x1]	1577315	1			T23	73		T27	63		T29	36
all_pins[8]	transitions[0x0=>0x1]	943939	1			T23	26		T27	42		T29	17
all_pins[8]	transitions[0x1=>0x0]	942223	1			T23	41		T27	25		T29	40
all_pins[9]	values[0x0]	2584522	1			T22	1		T23	111		T24	1
all_pins[9]	values[0x1]	1577930	1			T23	48		T27	48		T29	67
all_pins[9]	transitions[0x0=>0x1]	945133	1			T23	22		T27	30		T29	49
all_pins[9]	transitions[0x1=>0x0]	944518	1			T23	47		T27	45		T29	18
all_pins[10]	values[0x0]	2586424	1			T22	1		T23	110		T24	1
all_pins[10]	values[0x1]	1576028	1			T23	49		T27	55		T29	49
all_pins[10]	transitions[0x0=>0x1]	942667	1			T23	37		T27	37		T29	10
all_pins[10]	transitions[0x1=>0x0]	944569	1			T23	36		T27	30		T29	28
all_pins[11]	values[0x0]	2584005	1			T22	1		T23	124		T24	1
all_pins[11]	values[0x1]	1578447	1			T23	35		T27	48		T29	32
all_pins[11]	transitions[0x0=>0x1]	946070	1			T23	25		T27	19		T29	17
all_pins[11]	transitions[0x1=>0x0]	943651	1			T23	39		T27	26		T29	34
all_pins[12]	values[0x0]	2589449	1			T22	1		T23	88		T24	1
all_pins[12]	values[0x1]	1573003	1			T23	71		T27	56		T29	14
all_pins[12]	transitions[0x0=>0x1]	939862	1			T23	50		T27	27		T29	2
all_pins[12]	transitions[0x1=>0x0]	945306	1			T23	14		T27	19		T29	20
all_pins[13]	values[0x0]	2589635	1			T22	1		T23	108		T24	1
all_pins[13]	values[0x1]	1572817	1			T23	51		T27	23		T29	30
all_pins[13]	transitions[0x0=>0x1]	942036	1			T23	30		T27	13		T29	30
all_pins[13]	transitions[0x1=>0x0]	942222	1			T23	50		T27	46		T29	14
all_pins[14]	values[0x0]	2587282	1			T22	1		T23	105		T24	1
all_pins[14]	values[0x1]	1575170	1			T23	54		T27	62		T29	53
all_pins[14]	transitions[0x0=>0x1]	945185	1			T23	30		T27	45		T29	37
all_pins[14]	transitions[0x1=>0x0]	942832	1			T23	27		T27	6		T29	14
all_pins[15]	values[0x0]	2585972	1			T22	1		T23	101		T24	1
all_pins[15]	values[0x1]	1576480	1			T23	58		T27	44		T29	27
all_pins[15]	transitions[0x0=>0x1]	943188	1			T23	37		T27	29		T29	7
all_pins[15]	transitions[0x1=>0x0]	941878	1			T23	33		T27	47		T29	33
all_pins[16]	values[0x0]	2586716	1			T22	1		T23	100		T24	1
all_pins[16]	values[0x1]	1575736	1			T23	59		T27	46		T29	28
all_pins[16]	transitions[0x0=>0x1]	943208	1			T23	48		T27	29		T29	20
all_pins[16]	transitions[0x1=>0x0]	943952	1			T23	47		T27	27		T29	19
all_pins[17]	values[0x0]	2589025	1			T22	1		T23	109		T24	1
all_pins[17]	values[0x1]	1573427	1			T23	50		T27	35		T29	48
all_pins[17]	transitions[0x0=>0x1]	941264	1			T23	34		T27	19		T29	28
all_pins[17]	transitions[0x1=>0x0]	943573	1			T23	43		T27	30		T29	8
all_pins[18]	values[0x0]	2587676	1			T22	1		T23	83		T24	1
all_pins[18]	values[0x1]	1574776	1			T23	76		T27	36		T29	33
all_pins[18]	transitions[0x0=>0x1]	944268	1			T23	49		T27	23		T29	19
all_pins[18]	transitions[0x1=>0x0]	942919	1			T23	23		T27	22		T29	34
all_pins[19]	values[0x0]	2588216	1			T22	1		T23	103		T24	1
all_pins[19]	values[0x1]	1574236	1			T23	56		T27	67		T29	43
all_pins[19]	transitions[0x0=>0x1]	944172	1			T23	24		T27	46		T29	24
all_pins[19]	transitions[0x1=>0x0]	944712	1			T23	44		T27	15		T29	14
all_pins[20]	values[0x0]	2583292	1			T22	1		T23	116		T24	1
all_pins[20]	values[0x1]	1579160	1			T23	43		T27	56		T29	53
all_pins[20]	transitions[0x0=>0x1]	945210	1			T23	22		T27	28		T29	29
all_pins[20]	transitions[0x1=>0x0]	940286	1			T23	35		T27	39		T29	19
all_pins[21]	values[0x0]	2588396	1			T22	1		T23	99		T24	1
all_pins[21]	values[0x1]	1574056	1			T23	60		T27	64		T29	28
all_pins[21]	transitions[0x0=>0x1]	940603	1			T23	41		T27	27		T29	25
all_pins[21]	transitions[0x1=>0x0]	945707	1			T23	24		T27	19		T29	50
all_pins[22]	values[0x0]	2582170	1			T22	1		T23	114		T24	1
all_pins[22]	values[0x1]	1580282	1			T23	45		T27	29		T29	38
all_pins[22]	transitions[0x0=>0x1]	946508	1			T23	31		T27	21		T29	22
all_pins[22]	transitions[0x1=>0x0]	940282	1			T23	46		T27	56		T29	12
all_pins[23]	values[0x0]	2582392	1			T22	1		T23	107		T24	1
all_pins[23]	values[0x1]	1580060	1			T23	52		T27	32		T29	27
all_pins[23]	transitions[0x0=>0x1]	947515	1			T23	36		T27	22		T29	11
all_pins[23]	transitions[0x1=>0x0]	947737	1			T23	29		T27	19		T29	22
all_pins[24]	values[0x0]	2579066	1			T22	1		T23	68		T24	1
all_pins[24]	values[0x1]	1583386	1			T23	91		T27	43		T29	17
all_pins[24]	transitions[0x0=>0x1]	947812	1			T23	68		T27	24		T29	5
all_pins[24]	transitions[0x1=>0x0]	944486	1			T23	29		T27	13		T29	15
all_pins[25]	values[0x0]	2592038	1			T22	1		T23	122		T24	1
all_pins[25]	values[0x1]	1570414	1			T23	37		T27	36		T29	56
all_pins[25]	transitions[0x0=>0x1]	934314	1			T23	14		T27	18		T29	43
all_pins[25]	transitions[0x1=>0x0]	947286	1			T23	68		T27	25		T29	4
all_pins[26]	values[0x0]	2585308	1			T22	1		T23	88		T24	1
all_pins[26]	values[0x1]	1577144	1			T23	71		T27	71		T29	35
all_pins[26]	transitions[0x0=>0x1]	946636	1			T23	57		T27	46		T29	16
all_pins[26]	transitions[0x1=>0x0]	939906	1			T23	23		T27	11		T29	37
all_pins[27]	values[0x0]	2586183	1			T22	1		T23	106		T24	1
all_pins[27]	values[0x1]	1576269	1			T23	53		T27	37		T29	33
all_pins[27]	transitions[0x0=>0x1]	942912	1			T23	31		T27	9		T29	26
all_pins[27]	transitions[0x1=>0x0]	943787	1			T23	49		T27	43		T29	28
all_pins[28]	values[0x0]	2582942	1			T22	1		T23	103		T24	1
all_pins[28]	values[0x1]	1579510	1			T23	56		T27	43		T29	37
all_pins[28]	transitions[0x0=>0x1]	945251	1			T23	30		T27	35		T29	28
all_pins[28]	transitions[0x1=>0x0]	942010	1			T23	27		T27	29		T29	24
all_pins[29]	values[0x0]	2587740	1			T22	1		T23	127		T24	1
all_pins[29]	values[0x1]	1574712	1			T23	32		T27	50		T29	58
all_pins[29]	transitions[0x0=>0x1]	941393	1			T23	22		T27	29		T29	38
all_pins[29]	transitions[0x1=>0x0]	946191	1			T23	46		T27	22		T29	17
all_pins[30]	values[0x0]	2585365	1			T22	1		T23	82		T24	1
all_pins[30]	values[0x1]	1577087	1			T23	77		T27	27		T29	66
all_pins[30]	transitions[0x0=>0x1]	945926	1			T23	56		T27	15		T29	29
all_pins[30]	transitions[0x1=>0x0]	943551	1			T23	11		T27	38		T29	21
all_pins[31]	values[0x0]	2588248	1			T22	1		T23	110		T24	1
all_pins[31]	values[0x1]	1574204	1			T23	49		T27	51		T29	47
all_pins[31]	transitions[0x0=>0x1]	943936	1			T23	22		T27	37		T29	27
all_pins[31]	transitions[0x1=>0x0]	946819	1			T23	50		T27	13		T29	46