Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[1]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[2]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[3]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[4]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[5]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[6]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[7]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[8]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[9]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[10]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[11]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[12]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[13]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[14]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[15]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[16]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[17]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[18]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[19]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[20]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[21]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[22]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[23]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[24]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[25]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[26]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[27]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[28]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[29]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[30]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[31]	13753662	1			T22	380		T23	147		T24	531

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262214971

1

T22

2787

T23

2401

T24

11903

auto[1]

177902213

1

T22

9373

T23

2303

T24

5089

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

353796696

1

T22

8951

T23

4704

T24

9931

auto[1]

86320488

1

T22

3209

T24

7061

T25

3744

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

328929755

1

T22

6317

T23

4704

T24

10216

auto[1]

111187429

1

T22

5843

T24

6776

T25

7731

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5135380	1			T22	26		T23	77		T24	139
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3790311	1			T22	127		T23	70		T24	57
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1355407	1			T22	43		T24	135		T25	58
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1707239	1			T22	14		T24	82		T25	30
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	418724	1			T22	129		T25	166		T28	118
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1346601	1			T22	41		T24	118		T25	40
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5117937	1			T22	4		T23	81		T24	168
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3793309	1			T22	112		T23	66		T24	56
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1352773	1			T22	50		T24	128		T25	55
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1714530	1			T22	28		T24	83		T25	20
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	423944	1			T22	136		T25	124		T28	120
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1351169	1			T22	50		T24	96		T25	68
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5121366	1			T22	10		T23	69		T24	145
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3803305	1			T22	81		T23	78		T24	45
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1357887	1			T22	49		T24	142		T25	58
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1710582	1			T22	26		T24	84		T25	24
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	420648	1			T22	168		T25	150		T28	92
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1339874	1			T22	46		T24	115		T25	59
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5130019	1			T22	10		T23	81		T24	144
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3795650	1			T22	113		T23	66		T24	50
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1355725	1			T22	64		T24	97		T25	57
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1708904	1			T22	25		T24	132		T25	16
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	420086	1			T22	133		T25	144		T28	95
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1343278	1			T22	35		T24	108		T25	43
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5128097	1			T22	10		T23	65		T24	155
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3800500	1			T22	101		T23	82		T24	59
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1358049	1			T22	55		T24	98		T25	53
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1704737	1			T22	26		T24	105		T25	34
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	420169	1			T22	154		T25	191		T28	138
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1342110	1			T22	34		T24	114		T25	79
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5119966	1			T22	14		T23	75		T24	138
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3802983	1			T22	89		T23	72		T24	60
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1356715	1			T22	44		T24	129		T25	69
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1707757	1			T22	34		T24	100		T25	16
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	421034	1			T22	113		T25	132		T28	96
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1345207	1			T22	86		T24	104		T25	48
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5131464	1			T22	20		T23	70		T24	143
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3786947	1			T22	119		T23	77		T24	51
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1362008	1			T22	54		T24	105		T25	46
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1706068	1			T22	13		T24	88		T25	31
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	422031	1			T22	96		T25	169		T28	124
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1345144	1			T22	78		T24	144		T25	75
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5129989	1			T22	29		T23	77		T24	168
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3788228	1			T22	166		T23	70		T24	48
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1352026	1			T22	44		T24	88		T25	58
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1715614	1			T22	4		T24	111		T25	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	421841	1			T22	95		T25	119		T28	116
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1345964	1			T22	42		T24	116		T25	60
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5117745	1			T22	14		T23	82		T24	144
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3797894	1			T22	111		T23	65		T24	50
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1357842	1			T22	60		T24	109		T25	74
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1711151	1			T22	29		T24	100		T25	43
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	421839	1			T22	105		T25	155		T28	132
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1347191	1			T22	61		T24	128		T25	38
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5126934	1			T22	18		T23	76		T24	140
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3789976	1			T22	93		T23	71		T24	50
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1358411	1			T22	31		T24	114		T25	50
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1715109	1			T22	24		T24	108		T25	21
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	419966	1			T22	139		T25	165		T28	122
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1343266	1			T22	75		T24	119		T25	73
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5124412	1			T22	24		T23	73		T24	175
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3799798	1			T22	125		T23	74		T24	51
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1352557	1			T22	50		T24	85		T25	55
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1710922	1			T22	13		T24	116		T25	26
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	418670	1			T22	126		T25	184		T28	126
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1347303	1			T22	42		T24	104		T25	49
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5126400	1			T22	17		T23	71		T24	153
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3796142	1			T22	114		T23	76		T24	49
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1355635	1			T22	92		T24	114		T25	51
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1708915	1			T22	13		T24	117		T25	16
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	421244	1			T22	100		T25	116		T28	100
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1345326	1			T22	44		T24	98		T25	63
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5115768	1			T22	22		T23	70		T24	130
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3800229	1			T22	100		T23	77		T24	54
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1354120	1			T22	40		T24	120		T25	47
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1713959	1			T22	19		T24	114		T25	27
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	419718	1			T22	134		T25	197		T28	96
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1349868	1			T22	65		T24	113		T25	74
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5137685	1			T22	33		T23	64		T24	146
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3788938	1			T22	140		T23	83		T24	50
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1358984	1			T22	54		T24	96		T25	36
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1703315	1			T22	9		T24	114		T25	28
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	417847	1			T22	100		T25	154		T28	88
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1346893	1			T22	44		T24	125		T25	66
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5125527	1			T22	13		T23	82		T24	170
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3799472	1			T22	130		T23	65		T24	52
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1357523	1			T22	29		T24	101		T25	80
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1704638	1			T22	29		T24	112		T25	19
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	421164	1			T22	152		T25	75		T28	103
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1345338	1			T22	27		T24	96		T25	57
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5119004	1			T22	25		T23	72		T24	185
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3797410	1			T22	125		T23	75		T24	48
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1357950	1			T22	46		T24	110		T25	76
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1713803	1			T22	12		T24	94		T25	15
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	423009	1			T22	102		T25	117		T28	132
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1342486	1			T22	70		T24	94		T25	57
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5130462	1			T22	24		T23	65		T24	137
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3798789	1			T22	116		T23	82		T24	55
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1353080	1			T22	95		T24	140		T25	62
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1708102	1			T22	11		T24	83		T25	24
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	422250	1			T22	83		T25	169		T28	127
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1340979	1			T22	51		T24	116		T25	65
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5136546	1			T22	26		T23	78		T24	141
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3791222	1			T22	164		T23	69		T24	53
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1355002	1			T22	38		T24	133		T25	63
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1712657	1			T22	12		T24	80		T25	25
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	419222	1			T22	121		T25	196		T28	143
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1339013	1			T22	19		T24	124		T25	51
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5134851	1			T22	25		T23	69		T24	148
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3792200	1			T22	173		T23	78		T24	58
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1356749	1			T22	43		T24	102		T25	48
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1710454	1			T22	6		T24	109		T25	18
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	419407	1			T22	103		T25	122		T28	112
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1340001	1			T22	30		T24	114		T25	76
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5124063	1			T22	24		T23	84		T24	168
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3802084	1			T22	175		T23	63		T24	46
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1351946	1			T22	48		T24	110		T25	24
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1714753	1			T22	10		T24	120		T25	46
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	421620	1			T22	97		T25	197		T28	104
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1339196	1			T22	26		T24	87		T25	81
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5139627	1			T22	17		T23	66		T24	159
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3791674	1			T22	130		T23	81		T24	47
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1345846	1			T22	32		T24	93		T25	49
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1711776	1			T22	30		T24	128		T25	25
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	422845	1			T22	104		T25	148		T28	114
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1341894	1			T22	67		T24	104		T25	47
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5134510	1			T22	35		T23	67		T24	154
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3787814	1			T22	160		T23	80		T24	58
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1351419	1			T22	67		T24	120		T25	49
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1714118	1			T22	6		T24	107		T25	40
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	420349	1			T22	77		T25	209		T28	100
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1345452	1			T22	35		T24	92		T25	84
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5116893	1			T22	14		T23	72		T24	196
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3803660	1			T22	73		T23	75		T24	55
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1354974	1			T22	42		T24	124		T25	63
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1719075	1			T22	19		T24	72		T25	28
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	420345	1			T22	122		T25	161		T28	150
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1338715	1			T22	110		T24	84		T25	45
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5132242	1			T22	20		T23	70		T24	128
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3797239	1			T22	150		T23	77		T24	54
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1349406	1			T22	53		T24	109		T25	64
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1713683	1			T22	11		T24	132		T25	19
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	420657	1			T22	108		T25	137		T28	126
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1340435	1			T22	38		T24	108		T25	53
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5136556	1			T22	27		T23	85		T24	171
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3794328	1			T22	158		T23	62		T24	51
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1353514	1			T22	33		T24	90		T25	61
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1711318	1			T22	7		T24	132		T25	20
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	419723	1			T22	115		T25	132		T28	137
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1338223	1			T22	40		T24	87		T25	70
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5126312	1			T22	19		T23	76		T24	173
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3793092	1			T22	132		T23	71		T24	47
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1356407	1			T22	42		T24	99		T25	100
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1715867	1			T22	8		T24	106		T25	26
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	421265	1			T22	133		T25	131		T28	125
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1340719	1			T22	46		T24	106		T25	51
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5130867	1			T22	15		T23	89		T24	148
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3796566	1			T22	113		T23	58		T24	44
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1352614	1			T22	54		T24	119		T25	54
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1713365	1			T22	27		T24	102		T25	38
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	421674	1			T22	130		T25	189		T28	130
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1338576	1			T22	41		T24	118		T25	49
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5125573	1			T22	17		T23	66		T24	143
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3802846	1			T22	99		T23	81		T24	51
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1359157	1			T22	41		T24	125		T25	54
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1710263	1			T22	16		T24	100		T25	25
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	418850	1			T22	133		T25	158		T28	90
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1336973	1			T22	74		T24	112		T25	33
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5137896	1			T22	29		T23	72		T24	155
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3791043	1			T22	174		T23	75		T24	51
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1356602	1			T22	36		T24	106		T25	66
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1707952	1			T22	3		T24	121		T25	23
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	421335	1			T22	98		T25	111		T28	100
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1338834	1			T22	40		T24	98		T25	84
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5135264	1			T22	25		T23	86		T24	165
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3799542	1			T22	114		T23	61		T24	55
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1351666	1			T22	79		T24	115		T25	43
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1708591	1			T22	13		T24	90		T25	25
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	421849	1			T22	120		T25	168		T28	113
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1336750	1			T22	29		T24	106		T25	54
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5127399	1			T22	19		T23	84		T24	149
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3794514	1			T22	154		T23	63		T24	53
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1354562	1			T22	47		T24	134		T25	65
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1712438	1			T22	12		T24	85		T25	38
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	422823	1			T22	107		T25	215		T28	100
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1341926	1			T22	41		T24	110		T25	64
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5123192	1			T22	22		T23	87		T24	158
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3803774	1			T22	118		T23	60		T24	46
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1351774	1			T22	66		T24	136		T25	42
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1715040	1			T22	10		T24	114		T25	28
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	422428	1			T22	103		T25	189		T28	84
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1337454	1			T22	61		T24	77		T25	58

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal