Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[1]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[2]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[3]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[4]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[5]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[6]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[7]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[8]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[9]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[10]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[11]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[12]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[13]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[14]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[15]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[16]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[17]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[18]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[19]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[20]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[21]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[22]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[23]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[24]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[25]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[26]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[27]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[28]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[29]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[30]	13753662	1			T22	380		T23	147		T24	531
bins_for_gpio_bits[31]	13753662	1			T22	380		T23	147		T24	531

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262214971

1

T22

2787

T23

2401

T24

11903

auto[1]

177902213

1

T22

9373

T23

2303

T24

5089

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

262207147

1

T22

2787

T23

2401

T24

11896

auto[1]

177910037

1

T22

9373

T23

2303

T24

5096

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	7956628	1			T22	76		T23	77		T24	327
bins_for_gpio_bits[0]	auto[0]	auto[1]	241188	1			T22	7		T24	29		T25	13
bins_for_gpio_bits[0]	auto[1]	auto[0]	241398	1			T22	7		T24	29		T25	13
bins_for_gpio_bits[0]	auto[1]	auto[1]	5314448	1			T22	290		T23	70		T24	146
bins_for_gpio_bits[1]	auto[0]	auto[0]	7943789	1			T22	75		T23	81		T24	354
bins_for_gpio_bits[1]	auto[0]	auto[1]	241209	1			T22	7		T24	25		T25	11
bins_for_gpio_bits[1]	auto[1]	auto[0]	241451	1			T22	7		T24	25		T25	11
bins_for_gpio_bits[1]	auto[1]	auto[1]	5327213	1			T22	291		T23	66		T24	127
bins_for_gpio_bits[2]	auto[0]	auto[0]	7948863	1			T22	76		T23	69		T24	341
bins_for_gpio_bits[2]	auto[0]	auto[1]	240719	1			T22	9		T24	29		T25	14
bins_for_gpio_bits[2]	auto[1]	auto[0]	240972	1			T22	9		T24	30		T25	14
bins_for_gpio_bits[2]	auto[1]	auto[1]	5323108	1			T22	286		T23	78		T24	131
bins_for_gpio_bits[3]	auto[0]	auto[0]	7953562	1			T22	90		T23	81		T24	350
bins_for_gpio_bits[3]	auto[0]	auto[1]	240806	1			T22	9		T24	23		T25	13
bins_for_gpio_bits[3]	auto[1]	auto[0]	241086	1			T22	9		T24	23		T25	13
bins_for_gpio_bits[3]	auto[1]	auto[1]	5318208	1			T22	272		T23	66		T24	135
bins_for_gpio_bits[4]	auto[0]	auto[0]	7950076	1			T22	85		T23	65		T24	333
bins_for_gpio_bits[4]	auto[0]	auto[1]	240569	1			T22	6		T24	25		T25	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	240807	1			T22	6		T24	25		T25	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	5322210	1			T22	283		T23	82		T24	148
bins_for_gpio_bits[5]	auto[0]	auto[0]	7943187	1			T22	81		T23	75		T24	341
bins_for_gpio_bits[5]	auto[0]	auto[1]	240975	1			T22	11		T24	26		T25	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	241251	1			T22	11		T24	26		T25	15
bins_for_gpio_bits[5]	auto[1]	auto[1]	5328249	1			T22	277		T23	72		T24	138
bins_for_gpio_bits[6]	auto[0]	auto[0]	7958744	1			T22	76		T23	70		T24	306
bins_for_gpio_bits[6]	auto[0]	auto[1]	240596	1			T22	11		T24	30		T25	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	240796	1			T22	11		T24	30		T25	11
bins_for_gpio_bits[6]	auto[1]	auto[1]	5313526	1			T22	282		T23	77		T24	165
bins_for_gpio_bits[7]	auto[0]	auto[0]	7956379	1			T22	70		T23	77		T24	342
bins_for_gpio_bits[7]	auto[0]	auto[1]	241006	1			T22	7		T24	25		T25	14
bins_for_gpio_bits[7]	auto[1]	auto[0]	241250	1			T22	7		T24	25		T25	13
bins_for_gpio_bits[7]	auto[1]	auto[1]	5315027	1			T22	296		T23	70		T24	139
bins_for_gpio_bits[8]	auto[0]	auto[0]	7945037	1			T22	93		T23	82		T24	321
bins_for_gpio_bits[8]	auto[0]	auto[1]	241438	1			T22	10		T24	32		T25	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	241701	1			T22	10		T24	32		T25	12
bins_for_gpio_bits[8]	auto[1]	auto[1]	5325486	1			T22	267		T23	65		T24	146
bins_for_gpio_bits[9]	auto[0]	auto[0]	7959276	1			T22	68		T23	76		T24	334
bins_for_gpio_bits[9]	auto[0]	auto[1]	240908	1			T22	5		T24	27		T25	12
bins_for_gpio_bits[9]	auto[1]	auto[0]	241178	1			T22	5		T24	28		T25	12
bins_for_gpio_bits[9]	auto[1]	auto[1]	5312300	1			T22	302		T23	71		T24	142
bins_for_gpio_bits[10]	auto[0]	auto[0]	7945852	1			T22	81		T23	73		T24	348
bins_for_gpio_bits[10]	auto[0]	auto[1]	241779	1			T22	6		T24	28		T25	11
bins_for_gpio_bits[10]	auto[1]	auto[0]	242039	1			T22	6		T24	28		T25	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	5323992	1			T22	287		T23	74		T24	127
bins_for_gpio_bits[11]	auto[0]	auto[0]	7949814	1			T22	114		T23	71		T24	357
bins_for_gpio_bits[11]	auto[0]	auto[1]	240889	1			T22	8		T24	27		T25	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	241136	1			T22	8		T24	27		T25	10
bins_for_gpio_bits[11]	auto[1]	auto[1]	5321823	1			T22	250		T23	76		T24	120
bins_for_gpio_bits[12]	auto[0]	auto[0]	7942203	1			T22	73		T23	70		T24	339
bins_for_gpio_bits[12]	auto[0]	auto[1]	241392	1			T22	8		T24	24		T25	8
bins_for_gpio_bits[12]	auto[1]	auto[0]	241644	1			T22	8		T24	25		T25	8
bins_for_gpio_bits[12]	auto[1]	auto[1]	5328423	1			T22	291		T23	77		T24	143
bins_for_gpio_bits[13]	auto[0]	auto[0]	7959116	1			T22	86		T23	64		T24	325
bins_for_gpio_bits[13]	auto[0]	auto[1]	240596	1			T22	10		T24	30		T25	10
bins_for_gpio_bits[13]	auto[1]	auto[0]	240868	1			T22	10		T24	31		T25	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	5313082	1			T22	274		T23	83		T24	145
bins_for_gpio_bits[14]	auto[0]	auto[0]	7946634	1			T22	67		T23	82		T24	359
bins_for_gpio_bits[14]	auto[0]	auto[1]	240815	1			T22	4		T24	24		T25	15
bins_for_gpio_bits[14]	auto[1]	auto[0]	241054	1			T22	4		T24	24		T25	14
bins_for_gpio_bits[14]	auto[1]	auto[1]	5325159	1			T22	305		T23	65		T24	124
bins_for_gpio_bits[15]	auto[0]	auto[0]	7949758	1			T22	74		T23	72		T24	363
bins_for_gpio_bits[15]	auto[0]	auto[1]	240758	1			T22	9		T24	26		T25	13
bins_for_gpio_bits[15]	auto[1]	auto[0]	240999	1			T22	9		T24	26		T25	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	5322147	1			T22	288		T23	75		T24	116
bins_for_gpio_bits[16]	auto[0]	auto[0]	7950178	1			T22	115		T23	65		T24	330
bins_for_gpio_bits[16]	auto[0]	auto[1]	241205	1			T22	15		T24	30		T25	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	241466	1			T22	15		T24	30		T25	12
bins_for_gpio_bits[16]	auto[1]	auto[1]	5320813	1			T22	235		T23	82		T24	141
bins_for_gpio_bits[17]	auto[0]	auto[0]	7963371	1			T22	68		T23	78		T24	325
bins_for_gpio_bits[17]	auto[0]	auto[1]	240621	1			T22	8		T24	29		T25	8
bins_for_gpio_bits[17]	auto[1]	auto[0]	240834	1			T22	8		T24	29		T25	7
bins_for_gpio_bits[17]	auto[1]	auto[1]	5308836	1			T22	296		T23	69		T24	148
bins_for_gpio_bits[18]	auto[0]	auto[0]	7960671	1			T22	63		T23	69		T24	335
bins_for_gpio_bits[18]	auto[0]	auto[1]	241145	1			T22	11		T24	24		T25	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	241383	1			T22	11		T24	24		T25	11
bins_for_gpio_bits[18]	auto[1]	auto[1]	5310463	1			T22	295		T23	78		T24	148
bins_for_gpio_bits[19]	auto[0]	auto[0]	7949380	1			T22	75		T23	84		T24	369
bins_for_gpio_bits[19]	auto[0]	auto[1]	241168	1			T22	7		T24	28		T25	6
bins_for_gpio_bits[19]	auto[1]	auto[0]	241382	1			T22	7		T24	29		T25	6
bins_for_gpio_bits[19]	auto[1]	auto[1]	5321732	1			T22	291		T23	63		T24	105
bins_for_gpio_bits[20]	auto[0]	auto[0]	7956373	1			T22	71		T23	66		T24	351
bins_for_gpio_bits[20]	auto[0]	auto[1]	240629	1			T22	8		T24	29		T25	10
bins_for_gpio_bits[20]	auto[1]	auto[0]	240876	1			T22	8		T24	29		T25	9
bins_for_gpio_bits[20]	auto[1]	auto[1]	5315784	1			T22	293		T23	81		T24	122
bins_for_gpio_bits[21]	auto[0]	auto[0]	7958355	1			T22	95		T23	67		T24	352
bins_for_gpio_bits[21]	auto[0]	auto[1]	241418	1			T22	13		T24	29		T25	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	241692	1			T22	13		T24	29		T25	11
bins_for_gpio_bits[21]	auto[1]	auto[1]	5312197	1			T22	259		T23	80		T24	121
bins_for_gpio_bits[22]	auto[0]	auto[0]	7949821	1			T22	66		T23	72		T24	370
bins_for_gpio_bits[22]	auto[0]	auto[1]	240889	1			T22	9		T24	22		T25	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	241121	1			T22	9		T24	22		T25	10
bins_for_gpio_bits[22]	auto[1]	auto[1]	5321831	1			T22	296		T23	75		T24	117
bins_for_gpio_bits[23]	auto[0]	auto[0]	7954163	1			T22	71		T23	70		T24	337
bins_for_gpio_bits[23]	auto[0]	auto[1]	240925	1			T22	13		T24	32		T25	15
bins_for_gpio_bits[23]	auto[1]	auto[0]	241168	1			T22	13		T24	32		T25	15
bins_for_gpio_bits[23]	auto[1]	auto[1]	5317406	1			T22	283		T23	77		T24	130
bins_for_gpio_bits[24]	auto[0]	auto[0]	7959940	1			T22	58		T23	85		T24	369
bins_for_gpio_bits[24]	auto[0]	auto[1]	241212	1			T22	9		T24	23		T25	9
bins_for_gpio_bits[24]	auto[1]	auto[0]	241448	1			T22	9		T24	24		T25	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	5311062	1			T22	304		T23	62		T24	115
bins_for_gpio_bits[25]	auto[0]	auto[0]	7957284	1			T22	62		T23	76		T24	356
bins_for_gpio_bits[25]	auto[0]	auto[1]	241061	1			T22	7		T24	22		T25	15
bins_for_gpio_bits[25]	auto[1]	auto[0]	241302	1			T22	7		T24	22		T25	15
bins_for_gpio_bits[25]	auto[1]	auto[1]	5314015	1			T22	304		T23	71		T24	131
bins_for_gpio_bits[26]	auto[0]	auto[0]	7956150	1			T22	85		T23	89		T24	340
bins_for_gpio_bits[26]	auto[0]	auto[1]	240495	1			T22	11		T24	29		T25	11
bins_for_gpio_bits[26]	auto[1]	auto[0]	240696	1			T22	11		T24	29		T25	11
bins_for_gpio_bits[26]	auto[1]	auto[1]	5316321	1			T22	273		T23	58		T24	133
bins_for_gpio_bits[27]	auto[0]	auto[0]	7953484	1			T22	66		T23	66		T24	342
bins_for_gpio_bits[27]	auto[0]	auto[1]	241230	1			T22	8		T24	26		T25	10
bins_for_gpio_bits[27]	auto[1]	auto[0]	241509	1			T22	8		T24	26		T25	9
bins_for_gpio_bits[27]	auto[1]	auto[1]	5317439	1			T22	298		T23	81		T24	137
bins_for_gpio_bits[28]	auto[0]	auto[0]	7960910	1			T22	62		T23	72		T24	354
bins_for_gpio_bits[28]	auto[0]	auto[1]	241288	1			T22	6		T24	28		T25	10
bins_for_gpio_bits[28]	auto[1]	auto[0]	241540	1			T22	6		T24	28		T25	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	5309924	1			T22	306		T23	75		T24	121
bins_for_gpio_bits[29]	auto[0]	auto[0]	7954930	1			T22	107		T23	86		T24	342
bins_for_gpio_bits[29]	auto[0]	auto[1]	240398	1			T22	10		T24	28		T25	13
bins_for_gpio_bits[29]	auto[1]	auto[0]	240591	1			T22	10		T24	28		T25	12
bins_for_gpio_bits[29]	auto[1]	auto[1]	5317743	1			T22	253		T23	61		T24	133
bins_for_gpio_bits[30]	auto[0]	auto[0]	7952804	1			T22	68		T23	84		T24	343
bins_for_gpio_bits[30]	auto[0]	auto[1]	241369	1			T22	10		T24	25		T25	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	241595	1			T22	10		T24	25		T25	13
bins_for_gpio_bits[30]	auto[1]	auto[1]	5317894	1			T22	292		T23	63		T24	138
bins_for_gpio_bits[31]	auto[0]	auto[0]	7949000	1			T22	89		T23	87		T24	387
bins_for_gpio_bits[31]	auto[0]	auto[1]	240719	1			T22	9		T24	20		T25	7
bins_for_gpio_bits[31]	auto[1]	auto[0]	241006	1			T22	9		T24	21		T25	7
bins_for_gpio_bits[31]	auto[1]	auto[1]	5322937	1			T22	273		T23	60		T24	103