Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8124132 |
1 |
|
|
T22 |
192 |
|
T23 |
126 |
|
T24 |
317 |
| auto[1] |
5870466 |
1 |
|
|
T23 |
154 |
|
T27 |
125 |
|
T29 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13232475 |
1 |
|
|
T22 |
192 |
|
T23 |
269 |
|
T24 |
317 |
| auto[1] |
762123 |
1 |
|
|
T23 |
11 |
|
T27 |
3 |
|
T29 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8069983 |
1 |
|
|
T22 |
192 |
|
T23 |
141 |
|
T24 |
317 |
| auto[1] |
5924615 |
1 |
|
|
T23 |
139 |
|
T27 |
75 |
|
T29 |
97 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2586301 |
1 |
|
|
T23 |
69 |
|
T27 |
43 |
|
T29 |
81 |
| auto[1] |
auto[0] |
auto[1] |
382216 |
1 |
|
|
T23 |
8 |
|
T27 |
2 |
|
T29 |
7 |
| auto[1] |
auto[1] |
auto[0] |
2576191 |
1 |
|
|
T23 |
59 |
|
T27 |
29 |
|
T29 |
9 |
| auto[1] |
auto[1] |
auto[1] |
379907 |
1 |
|
|
T23 |
3 |
|
T27 |
1 |
|
T1 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8045087 |
1 |
|
|
T22 |
192 |
|
T23 |
149 |
|
T24 |
317 |
| auto[1] |
5949511 |
1 |
|
|
T23 |
131 |
|
T27 |
80 |
|
T29 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13228347 |
1 |
|
|
T22 |
192 |
|
T23 |
279 |
|
T24 |
317 |
| auto[1] |
766251 |
1 |
|
|
T23 |
1 |
|
T27 |
10 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8044313 |
1 |
|
|
T22 |
192 |
|
T23 |
212 |
|
T24 |
317 |
| auto[1] |
5950285 |
1 |
|
|
T23 |
68 |
|
T27 |
112 |
|
T29 |
43 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2585821 |
1 |
|
|
T23 |
25 |
|
T27 |
70 |
|
T29 |
11 |
| auto[1] |
auto[0] |
auto[1] |
381847 |
1 |
|
|
T27 |
6 |
|
T1 |
1 |
|
T12 |
12 |
| auto[1] |
auto[1] |
auto[0] |
2598213 |
1 |
|
|
T23 |
42 |
|
T27 |
32 |
|
T29 |
30 |
| auto[1] |
auto[1] |
auto[1] |
384404 |
1 |
|
|
T23 |
1 |
|
T27 |
4 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8090334 |
1 |
|
|
T22 |
192 |
|
T23 |
173 |
|
T24 |
317 |
| auto[1] |
5904264 |
1 |
|
|
T23 |
107 |
|
T27 |
111 |
|
T29 |
125 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13234255 |
1 |
|
|
T22 |
192 |
|
T23 |
270 |
|
T24 |
317 |
| auto[1] |
760343 |
1 |
|
|
T23 |
10 |
|
T27 |
9 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8075497 |
1 |
|
|
T22 |
192 |
|
T23 |
120 |
|
T24 |
317 |
| auto[1] |
5919101 |
1 |
|
|
T23 |
160 |
|
T27 |
141 |
|
T29 |
78 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2588750 |
1 |
|
|
T23 |
80 |
|
T27 |
70 |
|
T29 |
26 |
| auto[1] |
auto[0] |
auto[1] |
381333 |
1 |
|
|
T23 |
4 |
|
T27 |
3 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2570008 |
1 |
|
|
T23 |
70 |
|
T27 |
62 |
|
T29 |
48 |
| auto[1] |
auto[1] |
auto[1] |
379010 |
1 |
|
|
T23 |
6 |
|
T27 |
6 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072928 |
1 |
|
|
T22 |
192 |
|
T23 |
182 |
|
T24 |
317 |
| auto[1] |
5921670 |
1 |
|
|
T23 |
98 |
|
T27 |
111 |
|
T29 |
56 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13241820 |
1 |
|
|
T22 |
192 |
|
T23 |
272 |
|
T24 |
317 |
| auto[1] |
752778 |
1 |
|
|
T23 |
8 |
|
T27 |
7 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8130549 |
1 |
|
|
T22 |
192 |
|
T23 |
145 |
|
T24 |
317 |
| auto[1] |
5864049 |
1 |
|
|
T23 |
135 |
|
T27 |
103 |
|
T29 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2544120 |
1 |
|
|
T23 |
86 |
|
T27 |
44 |
|
T29 |
8 |
| auto[1] |
auto[0] |
auto[1] |
374197 |
1 |
|
|
T23 |
5 |
|
T27 |
5 |
|
T1 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2567151 |
1 |
|
|
T23 |
41 |
|
T27 |
52 |
|
T29 |
16 |
| auto[1] |
auto[1] |
auto[1] |
378581 |
1 |
|
|
T23 |
3 |
|
T27 |
2 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8097912 |
1 |
|
|
T22 |
192 |
|
T23 |
127 |
|
T24 |
317 |
| auto[1] |
5896686 |
1 |
|
|
T23 |
153 |
|
T27 |
141 |
|
T29 |
39 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13233792 |
1 |
|
|
T22 |
192 |
|
T23 |
273 |
|
T24 |
317 |
| auto[1] |
760806 |
1 |
|
|
T23 |
7 |
|
T27 |
7 |
|
T29 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8075632 |
1 |
|
|
T22 |
192 |
|
T23 |
181 |
|
T24 |
317 |
| auto[1] |
5918966 |
1 |
|
|
T23 |
99 |
|
T27 |
124 |
|
T29 |
89 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2586633 |
1 |
|
|
T23 |
33 |
|
T27 |
64 |
|
T29 |
56 |
| auto[1] |
auto[0] |
auto[1] |
382139 |
1 |
|
|
T23 |
1 |
|
T27 |
3 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2571527 |
1 |
|
|
T23 |
59 |
|
T27 |
53 |
|
T29 |
28 |
| auto[1] |
auto[1] |
auto[1] |
378667 |
1 |
|
|
T23 |
6 |
|
T27 |
4 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8105100 |
1 |
|
|
T22 |
192 |
|
T23 |
157 |
|
T24 |
317 |
| auto[1] |
5889498 |
1 |
|
|
T23 |
123 |
|
T27 |
47 |
|
T29 |
98 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13231258 |
1 |
|
|
T22 |
192 |
|
T23 |
275 |
|
T24 |
317 |
| auto[1] |
763340 |
1 |
|
|
T23 |
5 |
|
T27 |
7 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8057980 |
1 |
|
|
T22 |
192 |
|
T23 |
162 |
|
T24 |
317 |
| auto[1] |
5936618 |
1 |
|
|
T23 |
118 |
|
T27 |
78 |
|
T29 |
32 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2599306 |
1 |
|
|
T23 |
68 |
|
T27 |
57 |
|
T29 |
16 |
| auto[1] |
auto[0] |
auto[1] |
384367 |
1 |
|
|
T23 |
4 |
|
T27 |
4 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2573972 |
1 |
|
|
T23 |
45 |
|
T27 |
14 |
|
T29 |
15 |
| auto[1] |
auto[1] |
auto[1] |
378973 |
1 |
|
|
T23 |
1 |
|
T27 |
3 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072410 |
1 |
|
|
T22 |
192 |
|
T23 |
164 |
|
T24 |
317 |
| auto[1] |
5922188 |
1 |
|
|
T23 |
116 |
|
T27 |
133 |
|
T29 |
123 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13232894 |
1 |
|
|
T22 |
192 |
|
T23 |
274 |
|
T24 |
317 |
| auto[1] |
761704 |
1 |
|
|
T23 |
6 |
|
T27 |
5 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072194 |
1 |
|
|
T22 |
192 |
|
T23 |
139 |
|
T24 |
317 |
| auto[1] |
5922404 |
1 |
|
|
T23 |
141 |
|
T27 |
108 |
|
T29 |
98 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2584288 |
1 |
|
|
T23 |
86 |
|
T27 |
32 |
|
T29 |
22 |
| auto[1] |
auto[0] |
auto[1] |
382707 |
1 |
|
|
T23 |
4 |
|
T27 |
1 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2576412 |
1 |
|
|
T23 |
49 |
|
T27 |
71 |
|
T29 |
72 |
| auto[1] |
auto[1] |
auto[1] |
378997 |
1 |
|
|
T23 |
2 |
|
T27 |
4 |
|
T29 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8085459 |
1 |
|
|
T22 |
192 |
|
T23 |
166 |
|
T24 |
317 |
| auto[1] |
5909139 |
1 |
|
|
T23 |
114 |
|
T27 |
72 |
|
T29 |
48 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13232515 |
1 |
|
|
T22 |
192 |
|
T23 |
269 |
|
T24 |
317 |
| auto[1] |
762083 |
1 |
|
|
T23 |
11 |
|
T27 |
10 |
|
T29 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072235 |
1 |
|
|
T22 |
192 |
|
T23 |
145 |
|
T24 |
317 |
| auto[1] |
5922363 |
1 |
|
|
T23 |
135 |
|
T27 |
102 |
|
T29 |
90 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2578706 |
1 |
|
|
T23 |
72 |
|
T27 |
57 |
|
T29 |
63 |
| auto[1] |
auto[0] |
auto[1] |
380807 |
1 |
|
|
T23 |
6 |
|
T27 |
7 |
|
T29 |
6 |
| auto[1] |
auto[1] |
auto[0] |
2581574 |
1 |
|
|
T23 |
52 |
|
T27 |
35 |
|
T29 |
19 |
| auto[1] |
auto[1] |
auto[1] |
381276 |
1 |
|
|
T23 |
5 |
|
T27 |
3 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8083249 |
1 |
|
|
T22 |
192 |
|
T23 |
144 |
|
T24 |
317 |
| auto[1] |
5911349 |
1 |
|
|
T23 |
136 |
|
T27 |
99 |
|
T29 |
66 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13237017 |
1 |
|
|
T22 |
192 |
|
T23 |
268 |
|
T24 |
317 |
| auto[1] |
757581 |
1 |
|
|
T23 |
12 |
|
T27 |
3 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8097695 |
1 |
|
|
T22 |
192 |
|
T23 |
117 |
|
T24 |
317 |
| auto[1] |
5896903 |
1 |
|
|
T23 |
163 |
|
T27 |
93 |
|
T29 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2568828 |
1 |
|
|
T23 |
77 |
|
T27 |
63 |
|
T29 |
28 |
| auto[1] |
auto[0] |
auto[1] |
377999 |
1 |
|
|
T23 |
7 |
|
T27 |
2 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2570494 |
1 |
|
|
T23 |
74 |
|
T27 |
27 |
|
T29 |
12 |
| auto[1] |
auto[1] |
auto[1] |
379582 |
1 |
|
|
T23 |
5 |
|
T27 |
1 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8079436 |
1 |
|
|
T22 |
192 |
|
T23 |
146 |
|
T24 |
317 |
| auto[1] |
5915162 |
1 |
|
|
T23 |
134 |
|
T27 |
69 |
|
T29 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13234542 |
1 |
|
|
T22 |
192 |
|
T23 |
273 |
|
T24 |
317 |
| auto[1] |
760056 |
1 |
|
|
T23 |
7 |
|
T27 |
5 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8077165 |
1 |
|
|
T22 |
192 |
|
T23 |
161 |
|
T24 |
317 |
| auto[1] |
5917433 |
1 |
|
|
T23 |
119 |
|
T27 |
95 |
|
T29 |
89 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2587456 |
1 |
|
|
T23 |
54 |
|
T27 |
59 |
|
T29 |
39 |
| auto[1] |
auto[0] |
auto[1] |
381637 |
1 |
|
|
T23 |
6 |
|
T27 |
4 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2569921 |
1 |
|
|
T23 |
58 |
|
T27 |
31 |
|
T29 |
44 |
| auto[1] |
auto[1] |
auto[1] |
378419 |
1 |
|
|
T23 |
1 |
|
T27 |
1 |
|
T29 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8110583 |
1 |
|
|
T22 |
192 |
|
T23 |
120 |
|
T24 |
317 |
| auto[1] |
5884015 |
1 |
|
|
T23 |
160 |
|
T27 |
98 |
|
T29 |
60 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13232562 |
1 |
|
|
T22 |
192 |
|
T23 |
271 |
|
T24 |
317 |
| auto[1] |
762036 |
1 |
|
|
T23 |
9 |
|
T27 |
10 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8071990 |
1 |
|
|
T22 |
192 |
|
T23 |
135 |
|
T24 |
317 |
| auto[1] |
5922608 |
1 |
|
|
T23 |
145 |
|
T27 |
103 |
|
T29 |
66 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2589971 |
1 |
|
|
T23 |
56 |
|
T27 |
58 |
|
T29 |
42 |
| auto[1] |
auto[0] |
auto[1] |
382570 |
1 |
|
|
T23 |
4 |
|
T27 |
6 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2570601 |
1 |
|
|
T23 |
80 |
|
T27 |
35 |
|
T29 |
22 |
| auto[1] |
auto[1] |
auto[1] |
379466 |
1 |
|
|
T23 |
5 |
|
T27 |
4 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8125345 |
1 |
|
|
T22 |
192 |
|
T23 |
140 |
|
T24 |
317 |
| auto[1] |
5869253 |
1 |
|
|
T23 |
140 |
|
T27 |
135 |
|
T29 |
81 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13233982 |
1 |
|
|
T22 |
192 |
|
T23 |
271 |
|
T24 |
317 |
| auto[1] |
760616 |
1 |
|
|
T23 |
9 |
|
T27 |
8 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8079837 |
1 |
|
|
T22 |
192 |
|
T23 |
112 |
|
T24 |
317 |
| auto[1] |
5914761 |
1 |
|
|
T23 |
168 |
|
T27 |
125 |
|
T29 |
84 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2588667 |
1 |
|
|
T23 |
84 |
|
T27 |
40 |
|
T29 |
26 |
| auto[1] |
auto[0] |
auto[1] |
381960 |
1 |
|
|
T23 |
4 |
|
T27 |
3 |
|
T12 |
27 |
| auto[1] |
auto[1] |
auto[0] |
2565478 |
1 |
|
|
T23 |
75 |
|
T27 |
77 |
|
T29 |
54 |
| auto[1] |
auto[1] |
auto[1] |
378656 |
1 |
|
|
T23 |
5 |
|
T27 |
5 |
|
T29 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8071746 |
1 |
|
|
T22 |
192 |
|
T23 |
86 |
|
T24 |
317 |
| auto[1] |
5922852 |
1 |
|
|
T23 |
194 |
|
T27 |
102 |
|
T29 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13238713 |
1 |
|
|
T22 |
192 |
|
T23 |
277 |
|
T24 |
317 |
| auto[1] |
755885 |
1 |
|
|
T23 |
3 |
|
T27 |
5 |
|
T29 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8100655 |
1 |
|
|
T22 |
192 |
|
T23 |
169 |
|
T24 |
317 |
| auto[1] |
5893943 |
1 |
|
|
T23 |
111 |
|
T27 |
133 |
|
T29 |
40 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2563694 |
1 |
|
|
T23 |
35 |
|
T27 |
55 |
|
T29 |
22 |
| auto[1] |
auto[0] |
auto[1] |
377675 |
1 |
|
|
T27 |
2 |
|
T29 |
3 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2574364 |
1 |
|
|
T23 |
73 |
|
T27 |
73 |
|
T29 |
15 |
| auto[1] |
auto[1] |
auto[1] |
378210 |
1 |
|
|
T23 |
3 |
|
T27 |
3 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8087580 |
1 |
|
|
T22 |
192 |
|
T23 |
182 |
|
T24 |
317 |
| auto[1] |
5907018 |
1 |
|
|
T23 |
98 |
|
T27 |
119 |
|
T29 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13235377 |
1 |
|
|
T22 |
192 |
|
T23 |
272 |
|
T24 |
317 |
| auto[1] |
759221 |
1 |
|
|
T23 |
8 |
|
T27 |
5 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8086030 |
1 |
|
|
T22 |
192 |
|
T23 |
164 |
|
T24 |
317 |
| auto[1] |
5908568 |
1 |
|
|
T23 |
116 |
|
T27 |
90 |
|
T29 |
94 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2580412 |
1 |
|
|
T23 |
89 |
|
T27 |
37 |
|
T29 |
32 |
| auto[1] |
auto[0] |
auto[1] |
381352 |
1 |
|
|
T23 |
7 |
|
T27 |
1 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2568935 |
1 |
|
|
T23 |
19 |
|
T27 |
48 |
|
T29 |
56 |
| auto[1] |
auto[1] |
auto[1] |
377869 |
1 |
|
|
T23 |
1 |
|
T27 |
4 |
|
T29 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8108521 |
1 |
|
|
T22 |
192 |
|
T23 |
132 |
|
T24 |
317 |
| auto[1] |
5886077 |
1 |
|
|
T23 |
148 |
|
T27 |
150 |
|
T29 |
72 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13232891 |
1 |
|
|
T22 |
192 |
|
T23 |
269 |
|
T24 |
317 |
| auto[1] |
761707 |
1 |
|
|
T23 |
11 |
|
T27 |
7 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8075873 |
1 |
|
|
T22 |
192 |
|
T23 |
141 |
|
T24 |
317 |
| auto[1] |
5918725 |
1 |
|
|
T23 |
139 |
|
T27 |
105 |
|
T29 |
93 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2569121 |
1 |
|
|
T23 |
64 |
|
T27 |
29 |
|
T29 |
43 |
| auto[1] |
auto[0] |
auto[1] |
379590 |
1 |
|
|
T23 |
7 |
|
T27 |
4 |
|
T29 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2587897 |
1 |
|
|
T23 |
64 |
|
T27 |
69 |
|
T29 |
48 |
| auto[1] |
auto[1] |
auto[1] |
382117 |
1 |
|
|
T23 |
4 |
|
T27 |
3 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8049272 |
1 |
|
|
T22 |
192 |
|
T23 |
181 |
|
T24 |
317 |
| auto[1] |
5945326 |
1 |
|
|
T23 |
99 |
|
T27 |
92 |
|
T29 |
73 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13231645 |
1 |
|
|
T22 |
192 |
|
T23 |
273 |
|
T24 |
317 |
| auto[1] |
762953 |
1 |
|
|
T23 |
7 |
|
T27 |
10 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8061443 |
1 |
|
|
T22 |
192 |
|
T23 |
203 |
|
T24 |
317 |
| auto[1] |
5933155 |
1 |
|
|
T23 |
77 |
|
T27 |
140 |
|
T29 |
113 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2572430 |
1 |
|
|
T23 |
56 |
|
T27 |
79 |
|
T29 |
46 |
| auto[1] |
auto[0] |
auto[1] |
379045 |
1 |
|
|
T23 |
6 |
|
T27 |
5 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2597772 |
1 |
|
|
T23 |
14 |
|
T27 |
51 |
|
T29 |
61 |
| auto[1] |
auto[1] |
auto[1] |
383908 |
1 |
|
|
T23 |
1 |
|
T27 |
5 |
|
T29 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8111826 |
1 |
|
|
T22 |
192 |
|
T23 |
163 |
|
T24 |
317 |
| auto[1] |
5882772 |
1 |
|
|
T23 |
117 |
|
T27 |
61 |
|
T29 |
53 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13234290 |
1 |
|
|
T22 |
192 |
|
T23 |
267 |
|
T24 |
317 |
| auto[1] |
760308 |
1 |
|
|
T23 |
13 |
|
T27 |
7 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8079065 |
1 |
|
|
T22 |
192 |
|
T23 |
88 |
|
T24 |
317 |
| auto[1] |
5915533 |
1 |
|
|
T23 |
192 |
|
T27 |
83 |
|
T29 |
85 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2587827 |
1 |
|
|
T23 |
118 |
|
T27 |
64 |
|
T29 |
55 |
| auto[1] |
auto[0] |
auto[1] |
382503 |
1 |
|
|
T23 |
11 |
|
T27 |
7 |
|
T29 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2567398 |
1 |
|
|
T23 |
61 |
|
T27 |
12 |
|
T29 |
24 |
| auto[1] |
auto[1] |
auto[1] |
377805 |
1 |
|
|
T23 |
2 |
|
T29 |
2 |
|
T1 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8063405 |
1 |
|
|
T22 |
192 |
|
T23 |
91 |
|
T24 |
317 |
| auto[1] |
5931193 |
1 |
|
|
T23 |
189 |
|
T27 |
104 |
|
T29 |
50 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13231941 |
1 |
|
|
T22 |
192 |
|
T23 |
274 |
|
T24 |
317 |
| auto[1] |
762657 |
1 |
|
|
T23 |
6 |
|
T27 |
7 |
|
T29 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8064332 |
1 |
|
|
T22 |
192 |
|
T23 |
156 |
|
T24 |
317 |
| auto[1] |
5930266 |
1 |
|
|
T23 |
124 |
|
T27 |
106 |
|
T29 |
79 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2582338 |
1 |
|
|
T23 |
45 |
|
T27 |
51 |
|
T29 |
50 |
| auto[1] |
auto[0] |
auto[1] |
380999 |
1 |
|
|
T23 |
3 |
|
T27 |
2 |
|
T29 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2585271 |
1 |
|
|
T23 |
73 |
|
T27 |
48 |
|
T29 |
23 |
| auto[1] |
auto[1] |
auto[1] |
381658 |
1 |
|
|
T23 |
3 |
|
T27 |
5 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8125790 |
1 |
|
|
T22 |
192 |
|
T23 |
161 |
|
T24 |
317 |
| auto[1] |
5868808 |
1 |
|
|
T23 |
119 |
|
T27 |
101 |
|
T29 |
103 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13233600 |
1 |
|
|
T22 |
192 |
|
T23 |
270 |
|
T24 |
317 |
| auto[1] |
760998 |
1 |
|
|
T23 |
10 |
|
T27 |
5 |
|
T29 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8071453 |
1 |
|
|
T22 |
192 |
|
T23 |
142 |
|
T24 |
317 |
| auto[1] |
5923145 |
1 |
|
|
T23 |
138 |
|
T27 |
112 |
|
T29 |
57 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2607014 |
1 |
|
|
T23 |
84 |
|
T27 |
66 |
|
T29 |
15 |
| auto[1] |
auto[0] |
auto[1] |
386183 |
1 |
|
|
T23 |
6 |
|
T27 |
3 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2555133 |
1 |
|
|
T23 |
44 |
|
T27 |
41 |
|
T29 |
39 |
| auto[1] |
auto[1] |
auto[1] |
374815 |
1 |
|
|
T23 |
4 |
|
T27 |
2 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8103056 |
1 |
|
|
T22 |
192 |
|
T23 |
114 |
|
T24 |
317 |
| auto[1] |
5891542 |
1 |
|
|
T23 |
166 |
|
T27 |
140 |
|
T29 |
60 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13233194 |
1 |
|
|
T22 |
192 |
|
T23 |
269 |
|
T24 |
317 |
| auto[1] |
761404 |
1 |
|
|
T23 |
11 |
|
T27 |
10 |
|
T29 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8072270 |
1 |
|
|
T22 |
192 |
|
T23 |
164 |
|
T24 |
317 |
| auto[1] |
5922328 |
1 |
|
|
T23 |
116 |
|
T27 |
137 |
|
T29 |
93 |