Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8075194 |
1 |
|
|
T22 |
192 |
|
T23 |
114 |
|
T24 |
317 |
| auto[1] |
5919404 |
1 |
|
|
T23 |
166 |
|
T27 |
61 |
|
T29 |
88 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13231315 |
1 |
|
|
T22 |
192 |
|
T23 |
272 |
|
T24 |
317 |
| auto[1] |
763283 |
1 |
|
|
T23 |
8 |
|
T27 |
6 |
|
T29 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8060396 |
1 |
|
|
T22 |
192 |
|
T23 |
140 |
|
T24 |
317 |
| auto[1] |
5934202 |
1 |
|
|
T23 |
140 |
|
T27 |
69 |
|
T29 |
97 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2587708 |
1 |
|
|
T23 |
56 |
|
T27 |
44 |
|
T29 |
50 |
| auto[1] |
auto[0] |
auto[1] |
382244 |
1 |
|
|
T23 |
3 |
|
T27 |
3 |
|
T29 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2583211 |
1 |
|
|
T23 |
76 |
|
T27 |
19 |
|
T29 |
43 |
| auto[1] |
auto[1] |
auto[1] |
381039 |
1 |
|
|
T23 |
5 |
|
T27 |
3 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |