Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8071468 |
1 |
|
|
T22 |
192 |
|
T23 |
164 |
|
T24 |
317 |
| auto[1] |
5923130 |
1 |
|
|
T23 |
116 |
|
T27 |
122 |
|
T29 |
71 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13237374 |
1 |
|
|
T22 |
192 |
|
T23 |
273 |
|
T24 |
317 |
| auto[1] |
757224 |
1 |
|
|
T23 |
7 |
|
T27 |
6 |
|
T29 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8090876 |
1 |
|
|
T22 |
192 |
|
T23 |
168 |
|
T24 |
317 |
| auto[1] |
5903722 |
1 |
|
|
T23 |
112 |
|
T27 |
94 |
|
T29 |
91 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2561758 |
1 |
|
|
T23 |
53 |
|
T27 |
38 |
|
T29 |
45 |
| auto[1] |
auto[0] |
auto[1] |
376293 |
1 |
|
|
T23 |
4 |
|
T27 |
3 |
|
T29 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2584740 |
1 |
|
|
T23 |
52 |
|
T27 |
50 |
|
T29 |
41 |
| auto[1] |
auto[1] |
auto[1] |
380931 |
1 |
|
|
T23 |
3 |
|
T27 |
3 |
|
T29 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |