Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8084981 |
1 |
|
|
T22 |
192 |
|
T23 |
93 |
|
T24 |
317 |
| auto[1] |
5909617 |
1 |
|
|
T23 |
187 |
|
T27 |
129 |
|
T29 |
72 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13230361 |
1 |
|
|
T22 |
192 |
|
T23 |
276 |
|
T24 |
317 |
| auto[1] |
764237 |
1 |
|
|
T23 |
4 |
|
T27 |
8 |
|
T29 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8052758 |
1 |
|
|
T22 |
192 |
|
T23 |
176 |
|
T24 |
317 |
| auto[1] |
5941840 |
1 |
|
|
T23 |
104 |
|
T27 |
153 |
|
T29 |
61 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614224 |
1 |
|
|
T23 |
24 |
|
T27 |
58 |
|
T29 |
25 |
| auto[1] |
auto[0] |
auto[1] |
386028 |
1 |
|
|
T27 |
4 |
|
T29 |
2 |
|
T1 |
5 |
| auto[1] |
auto[1] |
auto[0] |
2563379 |
1 |
|
|
T23 |
76 |
|
T27 |
87 |
|
T29 |
33 |
| auto[1] |
auto[1] |
auto[1] |
378209 |
1 |
|
|
T23 |
4 |
|
T27 |
4 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |