Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8089484 |
1 |
|
|
T22 |
192 |
|
T23 |
144 |
|
T24 |
317 |
| auto[1] |
5905114 |
1 |
|
|
T23 |
136 |
|
T27 |
114 |
|
T29 |
140 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13240135 |
1 |
|
|
T22 |
192 |
|
T23 |
267 |
|
T24 |
317 |
| auto[1] |
754463 |
1 |
|
|
T23 |
13 |
|
T29 |
2 |
|
T1 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8124096 |
1 |
|
|
T22 |
192 |
|
T23 |
95 |
|
T24 |
317 |
| auto[1] |
5870502 |
1 |
|
|
T23 |
185 |
|
T27 |
102 |
|
T29 |
44 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2550794 |
1 |
|
|
T23 |
79 |
|
T27 |
41 |
|
T29 |
1 |
| auto[1] |
auto[0] |
auto[1] |
374380 |
1 |
|
|
T23 |
6 |
|
T1 |
5 |
|
T12 |
22 |
| auto[1] |
auto[1] |
auto[0] |
2565245 |
1 |
|
|
T23 |
93 |
|
T27 |
61 |
|
T29 |
41 |
| auto[1] |
auto[1] |
auto[1] |
380083 |
1 |
|
|
T23 |
7 |
|
T29 |
2 |
|
T1 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |