Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8124132 |
1 |
|
|
T22 |
192 |
|
T23 |
126 |
|
T24 |
317 |
| auto[1] |
5870466 |
1 |
|
|
T23 |
154 |
|
T27 |
125 |
|
T29 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11543486 |
1 |
|
|
T22 |
192 |
|
T23 |
195 |
|
T24 |
317 |
| auto[1] |
2451112 |
1 |
|
|
T23 |
85 |
|
T27 |
24 |
|
T29 |
62 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8052838 |
1 |
|
|
T22 |
192 |
|
T23 |
118 |
|
T24 |
317 |
| auto[1] |
5941760 |
1 |
|
|
T23 |
162 |
|
T27 |
89 |
|
T29 |
107 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1753254 |
1 |
|
|
T23 |
34 |
|
T27 |
19 |
|
T29 |
45 |
| auto[1] |
auto[0] |
auto[1] |
1227863 |
1 |
|
|
T23 |
27 |
|
T27 |
13 |
|
T29 |
54 |
| auto[1] |
auto[1] |
auto[0] |
1737394 |
1 |
|
|
T23 |
43 |
|
T27 |
46 |
|
T1 |
44 |
| auto[1] |
auto[1] |
auto[1] |
1223249 |
1 |
|
|
T23 |
58 |
|
T27 |
11 |
|
T29 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |